static void set_sw_LED1(struct rtl8192cd_priv *priv, int flag) { #ifdef RTL8190_SWGPIO_LED if (LED_ROUTE) set_swGpio_LED(priv, 1, flag); #else #if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) #ifdef CONFIG_RTL_92D_SUPPORT if (GET_CHIP_VER(priv) == VERSION_8192D) { if (flag) RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV_92D); else RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff); } else #endif { if (flag) RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV); else RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff); } #endif #endif }
static void set_sw_LED0(struct rtl8192cd_priv *priv, int flag) { #ifdef RTL8190_SWGPIO_LED if (LED_ROUTE) set_swGpio_LED(priv, 0, flag); #else if ((GET_CHIP_VER(priv) == VERSION_8188E)||(GET_CHIP_VER(priv) == VERSION_8192E)) { if (flag) RTLWIFINIC_GPIO_write(5, 0); else RTLWIFINIC_GPIO_write(5, 1); } else if ((GET_CHIP_VER(priv) == VERSION_8812E)) { if (flag) RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV); else RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff); } else if (GET_CHIP_VER(priv) == VERSION_8881A) { if (flag) writel(readl(0xb800350c) | BIT(24), 0xb800350c); else writel(readl(0xb800350c) & ~BIT(24), 0xb800350c); } else { if (flag) RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffffff0) | LED0SV); else RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffffff0); } #endif }
static void set_sw_LED1(struct rtl8192cd_priv *priv, int flag) { #ifdef RTL8190_SWGPIO_LED if (LED_ROUTE) set_swGpio_LED(priv, 1, flag); #else if ((GET_CHIP_VER(priv) == VERSION_8188E)||(GET_CHIP_VER(priv) == VERSION_8192E)) { #ifdef RTLWIFINIC_GPIO_CONTROL if (flag) RTLWIFINIC_GPIO_write(5, 0); else RTLWIFINIC_GPIO_write(5, 1); #endif } #if defined(CONFIG_RTL_92D_SUPPORT) else if (GET_CHIP_VER(priv) == VERSION_8192D) { if (flag) RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV_92D); else RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff); } #endif else if (GET_CHIP_VER(priv) == VERSION_8192C){ if (flag) RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffff0ff) | LED1SV); else RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffff0ff); } #endif }
static void rtl8169_hw_start(struct eth_device *dev) { u32 i; #ifdef DEBUG_RTL8169 int stime = currticks(); printf ("%s\n", __FUNCTION__); #endif #if 0 /* Soft reset the chip. */ RTL_W8(ChipCmd, CmdReset); /* Check that the chip has finished the reset. */ for (i = 1000; i > 0; i--) { if ((RTL_R8(ChipCmd) & CmdReset) == 0) break; else udelay(10); } #endif RTL_W8(Cfg9346, Cfg9346_Unlock); RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); RTL_W8(EarlyTxThres, EarlyTxThld); /* For gigabit rtl8169 */ RTL_W16(RxMaxSize, RxPacketMaxSize); /* Set Rx Config register */ i = rtl8169_rx_config | (RTL_R32(RxConfig) & rtl_chip_info[tpc->chipset].RxConfigMask); RTL_W32(RxConfig, i); /* Set DMA burst size and Interframe Gap Time */ RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift)); tpc->cur_rx = 0; RTL_W32(TxDescStartAddr, (unsigned long)tpc->TxDescArray); RTL_W32(RxDescStartAddr, (unsigned long)tpc->RxDescArray); RTL_W8(Cfg9346, Cfg9346_Lock); udelay(10); RTL_W32(RxMissed, 0); rtl8169_set_rx_mode(dev); /* no early-rx interrupts */ RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); #ifdef DEBUG_RTL8169 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); #endif }
static void rtl8169_set_rx_mode(struct net_device *dev) { struct rtl8169_private *tp = dev->priv; void *ioaddr = tp->mmio_addr; unsigned long flags; u32 mc_filter[2]; /* Multicast hash filter */ int i, rx_mode; u32 tmp = 0; if (dev->flags & IFF_PROMISC) { /* Unconditionally log net taps. */ printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name); rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys; mc_filter[1] = mc_filter[0] = 0xffffffff; } else if ((dev->mc_count > multicast_filter_limit) || (dev->flags & IFF_ALLMULTI)) { /* Too many to filter perfectly -- accept all multicasts. */ rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; mc_filter[1] = mc_filter[0] = 0xffffffff; } else { struct dev_mc_list *mclist; rx_mode = AcceptBroadcast | AcceptMyPhys; mc_filter[1] = mc_filter[0] = 0; for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; i++, mclist = mclist->next) { int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); rx_mode |= AcceptMulticast; } } spin_lock_irqsave(&tp->lock, flags); tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset]. RxConfigMask); RTL_W32(RxConfig, tmp); RTL_W32(MAR0 + 0, mc_filter[0]); RTL_W32(MAR0 + 4, mc_filter[1]); spin_unlock_irqrestore(&tp->lock, flags); }
/************************************************************************** HALT - Turn off ethernet interface ***************************************************************************/ static void rtl_halt(struct eth_device *dev) { int i; #ifdef DEBUG_RTL8169 printf ("%s\n", __FUNCTION__); #endif ioaddr = dev->iobase; /* Stop the chip's Tx and Rx DMA processes. */ RTL_W8(ChipCmd, 0x00); /* Disable interrupts by clearing the interrupt mask. */ RTL_W16(IntrMask, 0x0000); RTL_W32(RxMissed, 0); tpc->TxDescArrays = NULL; tpc->RxDescArrays = NULL; tpc->TxDescArray = NULL; tpc->RxDescArray = NULL; for (i = 0; i < NUM_RX_DESC; i++) { tpc->RxBufferRing[i] = NULL; } }
static int rtl8169_suspend(struct pci_dev *pdev, u32 state) { struct net_device *dev = pci_get_drvdata(pdev); struct rtl8169_private *tp = dev->priv; void *ioaddr = tp->mmio_addr; unsigned long flags; if (!netif_running(dev)) return 0; netif_device_detach(dev); netif_stop_queue(dev); spin_lock_irqsave(&tp->lock, flags); /* Disable interrupts, stop Rx and Tx */ RTL_W16(IntrMask, 0); RTL_W8(ChipCmd, 0); /* Update the error counts. */ tp->stats.rx_missed_errors += RTL_R32(RxMissed); RTL_W32(RxMissed, 0); spin_unlock_irqrestore(&tp->lock, flags); return 0; }
__inline__ void DMDP_RTL_W32(unsigned int phy, unsigned int reg, unsigned int val32) { struct rtl8192cd_priv *priv; //printk("++++++++++++++++++++++++++%s(%x, %x)++++++++++++++++++++++++++\n", __FUNCTION__, reg, val32); if (phy >= NUM_WLAN_IFACE || phy < 0) { printk("%s: phy index[%d] out of bound !!\n", __FUNCTION__, phy); return; } priv = (struct rtl8192cd_priv *)if_priv[phy]; RTL_W32(reg, val32); }
static void set_sw_LED0(struct rtl8192cd_priv *priv, int flag) { #ifdef RTL8190_SWGPIO_LED if (LED_ROUTE) set_swGpio_LED(priv, 0, flag); #else #if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) if (flag) RTL_W32(LEDCFG, (RTL_R32(LEDCFG) & 0xfffffff0) | LED0SV); else RTL_W32(LEDCFG, RTL_R32(LEDCFG) & 0xfffffff0); #elif defined(CONFIG_RTL_88E_SUPPORT) if (flag) RTLWIFINIC_GPIO_write(5, 0); else RTLWIFINIC_GPIO_write(5, 1); #endif #endif }
static void rtl8169_set_rx_mode(void) { u32 mc_filter[2]; /* Multicast hash filter */ int rx_mode; u32 tmp = 0; #ifdef DEBUG_RTL8169 printf ("%s\n", __FUNCTION__); #endif /* IFF_ALLMULTI */ /* Too many to filter perfectly -- accept all multicasts. */ rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; mc_filter[1] = mc_filter[0] = 0xffffffff; tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & rtl_chip_info[tpc->chipset].RxConfigMask); RTL_W32(RxConfig, tmp); RTL_W32(MAR0 + 0, mc_filter[0]); RTL_W32(MAR0 + 4, mc_filter[1]); }
/** * rtl8169_get_stats - Get rtl8169 read/write statistics * @dev: The Ethernet Device to get statistics for * * Get TX/RX statistics for rtl8169 */ static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) { struct rtl8169_private *tp = dev->priv; void *ioaddr = tp->mmio_addr; unsigned long flags; if (netif_running(dev)) { spin_lock_irqsave(&tp->lock, flags); tp->stats.rx_missed_errors += RTL_R32(RxMissed); RTL_W32(RxMissed, 0); spin_unlock_irqrestore(&tp->lock, flags); } return &tp->stats; }
void mdio_write(int RegAddr, int value) { int i; RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); udelay(1000); for (i = 2000; i > 0; i--) { /* Check if the RTL8169 has completed writing to the specified MII register */ if (!(RTL_R32(PHYAR) & 0x80000000)) { break; } else { udelay(100); } } }
static int mdio_read(void *ioaddr, int RegAddr) { int i, value = -1; RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); udelay(1000); for (i = 2000; i > 0; i--) { // Check if the RTL8169 has completed retrieving data from the specified MII register if (RTL_R32(PHYAR) & 0x80000000) { value = (int) (RTL_R32(PHYAR) & 0xFFFF); break; } udelay(100); } return value; }
VOID ODM_Write4Byte( IN PDM_ODM_T pDM_Odm, IN u4Byte RegAddr, IN u4Byte Data ) { #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) prtl8192cd_priv priv = pDM_Odm->priv; RTL_W32(RegAddr, Data); #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) PADAPTER Adapter = pDM_Odm->Adapter; rtw_write32(Adapter,RegAddr, Data); #elif(DM_ODM_SUPPORT_TYPE & ODM_MP) PADAPTER Adapter = pDM_Odm->Adapter; PlatformEFIOWrite4Byte(Adapter, RegAddr, Data); #endif }
void ODM_Write4Byte( PDM_ODM_T pDM_Odm, u32 RegAddr, u32 Data ) { #if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) prtl8192cd_priv priv = pDM_Odm->priv; RTL_W32(RegAddr, Data); #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) struct rtw_adapter * Adapter = pDM_Odm->Adapter; rtw_write32(Adapter,RegAddr, Data); #elif(DM_ODM_SUPPORT_TYPE & ODM_MP) struct rtw_adapter * Adapter = pDM_Odm->Adapter; PlatformEFIOWrite4Byte(Adapter, RegAddr, Data); #endif }
static int rtl8169_close(struct net_device *dev) { struct rtl8169_private *tp = dev->priv; struct pci_dev *pdev = tp->pci_dev; void *ioaddr = tp->mmio_addr; netif_stop_queue(dev); rtl8169_delete_timer(dev); spin_lock_irq(&tp->lock); /* Stop the chip's Tx and Rx DMA processes. */ RTL_W8(ChipCmd, 0x00); /* Disable interrupts by clearing the interrupt mask. */ RTL_W16(IntrMask, 0x0000); /* Update the error counts. */ tp->stats.rx_missed_errors += RTL_R32(RxMissed); RTL_W32(RxMissed, 0); spin_unlock_irq(&tp->lock); synchronize_irq(dev->irq); free_irq(dev->irq, dev); rtl8169_tx_clear(tp); rtl8169_rx_clear(tp); pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, tp->RxPhyAddr); pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, tp->TxPhyAddr); tp->TxDescArray = NULL; tp->RxDescArray = NULL; return 0; }
static void rtl_halt_common(unsigned long dev_iobase) { int i; #ifdef DEBUG_RTL8169 printf ("%s\n", __FUNCTION__); #endif ioaddr = dev_iobase; /* Stop the chip's Tx and Rx DMA processes. */ RTL_W8(ChipCmd, 0x00); /* Disable interrupts by clearing the interrupt mask. */ RTL_W16(IntrMask, 0x0000); RTL_W32(RxMissed, 0); for (i = 0; i < NUM_RX_DESC; i++) { tpc->RxBufferRing[i] = NULL; } }
void enable_sw_LED(struct rtl8192cd_priv *priv, int init) { #if defined(HW_ANT_SWITCH) || defined(SW_ANT_SWITCH) int b23 = RTL_R32(LEDCFG) & BIT(23); #endif if (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) if (!(OPMODE & WIFI_STATION_STATE)) // if it is not Client mode , then run orignal 12 type LED_TYPE = LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA ; // configure mac to use SW LED #if defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT) if (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | LED2EN | LED2SV); #ifdef CONFIG_RTL_92D_SUPPORT else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX_92D) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA)) RTL_W32(LEDCFG, LED2DIS_92D | LED2SV_92D); else if (LED_TYPE == LEDTYPE_SW_LED1_GPIO9_LINKTXRX_92D) RTL_W32(LEDCFG, LED1DIS_92D | LED1SV_92D); #endif else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA)) RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | GP8_LED | LED2EN | LED2SV); else RTL_W32(LEDCFG, LED2SV | LED1SV | LED0SV); #elif defined(CONFIG_RTL_88E_SUPPORT) RTLWIFINIC_GPIO_config(5, 0x10); #endif priv->pshare->LED_Interval = LED_INTERVAL_TIME; priv->pshare->LED_Toggle = 0; priv->pshare->LED_ToggleStart = LED_OFF; priv->pshare->LED_tx_cnt_log = 0; priv->pshare->LED_rx_cnt_log = 0; priv->pshare->LED_tx_cnt = 0; priv->pshare->LED_rx_cnt = 0; if ((LED_TYPE == LEDTYPE_SW_ENABLE_TXRXDATA) || (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA)) { set_sw_LED0(priv, LED_ON); set_sw_LED1(priv, LED_OFF); if (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA) priv->pshare->LED_ToggleStart = LED_ON; } else if (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA) { set_sw_LED2(priv, LED_ON); priv->pshare->LED_ToggleStart = LED_ON; } else if (LED_TYPE == LEDTYPE_SW_ADATA_GDATA) { priv->pshare->LED_ToggleStart = LED_ON; if (priv->pshare->curr_band == BAND_5G) { set_sw_LED0(priv, LED_ON); set_sw_LED1(priv, LED_OFF); } else { // 11G set_sw_LED0(priv, LED_OFF); set_sw_LED1(priv, LED_ON); } } else if (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA_1) { set_sw_LED0(priv, LED_OFF); set_sw_LED1(priv, LED_ON); priv->pshare->LED_ToggleStart = LED_ON; } else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) ) { set_sw_LED2(priv, LED_ON); priv->pshare->LED_ToggleStart = LED_ON; } else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA)) { set_sw_LED2(priv, LED_OFF); } else { set_sw_LED0(priv, LED_OFF); set_sw_LED1(priv, LED_OFF); set_sw_LED2(priv, LED_OFF); } #if defined(HW_ANT_SWITCH) || defined(SW_ANT_SWITCH) RTL_W32(LEDCFG, b23 | RTL_R32(LEDCFG)); #endif if (init) { #ifdef __KERNEL__ init_timer(&priv->pshare->LED_Timer); priv->pshare->LED_Timer.expires = jiffies + priv->pshare->LED_Interval; priv->pshare->LED_Timer.data = (unsigned long) priv; priv->pshare->LED_Timer.function = &LED_Interval_timeout; #elif defined(__ECOS) init_timer(&priv->pshare->LED_Timer, (unsigned long)priv, LED_Interval_timeout); #endif mod_timer(&priv->pshare->LED_Timer, jiffies + priv->pshare->LED_Interval); } }
static void rtl8169_hw_start(pci_dev_t dev) #endif { u32 i; #ifdef DEBUG_RTL8169 int stime = currticks(); printf ("%s\n", __FUNCTION__); #endif #if 0 /* Soft reset the chip. */ RTL_W8(ChipCmd, CmdReset); /* Check that the chip has finished the reset. */ for (i = 1000; i > 0; i--) { if ((RTL_R8(ChipCmd) & CmdReset) == 0) break; else udelay(10); } #endif RTL_W8(Cfg9346, Cfg9346_Unlock); /* RTL-8169sb/8110sb or previous version */ if (tpc->chipset <= 5) RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); RTL_W8(EarlyTxThres, EarlyTxThld); /* For gigabit rtl8169 */ RTL_W16(RxMaxSize, RxPacketMaxSize); /* Set Rx Config register */ i = rtl8169_rx_config | (RTL_R32(RxConfig) & rtl_chip_info[tpc->chipset].RxConfigMask); RTL_W32(RxConfig, i); /* Set DMA burst size and Interframe Gap Time */ RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift)); tpc->cur_rx = 0; #ifdef CONFIG_DM_ETH RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)tpc->TxDescArray)); #else RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)tpc->TxDescArray)); #endif RTL_W32(TxDescStartAddrHigh, (unsigned long)0); #ifdef CONFIG_DM_ETH RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys( dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); #else RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( dev, (pci_addr_t)(unsigned long)tpc->RxDescArray)); #endif RTL_W32(RxDescStartAddrHigh, (unsigned long)0); /* RTL-8169sc/8110sc or later version */ if (tpc->chipset > 5) RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); RTL_W8(Cfg9346, Cfg9346_Lock); udelay(10); RTL_W32(RxMissed, 0); rtl8169_set_rx_mode(); /* no early-rx interrupts */ RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); #ifdef DEBUG_RTL8169 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); #endif }
void enable_sw_LED(struct rtl8192cd_priv *priv, int init) { #if (defined(HW_ANT_SWITCH) || defined(SW_ANT_SWITCH))&&( defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT)) int b23 = RTL_R32(LEDCFG) & BIT(23); #endif if (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) if (!(OPMODE & WIFI_STATION_STATE)) // if it is not Client mode , then run orignal 12 type LED_TYPE = LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA ; // configure mac to use SW LED #if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE) //mark_ecos if ((GET_CHIP_VER(priv) == VERSION_8188E)||(GET_CHIP_VER(priv) == VERSION_8192E)) { #ifdef RTLWIFINIC_GPIO_CONTROL RTLWIFINIC_GPIO_config(5, 0x10); #endif } else #endif if (GET_CHIP_VER(priv) == VERSION_8812E) RTL_W32(LEDCFG, BIT(13) | LED1SV); else if (GET_CHIP_VER(priv) == VERSION_8881A) { writel(readl(0xb8000044) | BIT(15) | BIT(16), 0xb8000044); writel(readl(0xb8003500) & ~BIT(24), 0xb8003500); writel(readl(0xb8003508) | BIT(24), 0xb8003508); writel(readl(0xb800350c) | BIT(24), 0xb800350c); } else { if (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | LED2EN | LED2SV); else if (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA) RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | LED2EN | LED2SV); #ifdef CONFIG_RTL_92D_SUPPORT else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX_92D) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA_92D)) RTL_W32(LEDCFG,(RTL_R32(LEDCFG)&0xFF00FFFF)| LED2DIS_92D | LED2SV_92D); else if (LED_TYPE == LEDTYPE_SW_LED1_GPIO9_LINKTXRX_92D) RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFFFF00FF)|LED1DIS_92D | LED1SV_92D); #endif else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA)) RTL_W32(LEDCFG, (RTL_R32(LEDCFG)&0xFF00FFFF) | GP8_LED | LED2EN | LED2SV); else RTL_W32(LEDCFG, LED2SV | LED1SV | LED0SV); } priv->pshare->LED_Interval = LED_INTERVAL_TIME; priv->pshare->LED_Toggle = 0; priv->pshare->LED_ToggleStart = LED_OFF; priv->pshare->LED_tx_cnt_log = 0; priv->pshare->LED_rx_cnt_log = 0; priv->pshare->LED_tx_cnt = 0; priv->pshare->LED_rx_cnt = 0; if ((LED_TYPE == LEDTYPE_SW_ENABLE_TXRXDATA) || (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA)) { set_sw_LED0(priv, LED_ON); set_sw_LED1(priv, LED_OFF); if (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA) priv->pshare->LED_ToggleStart = LED_ON; } else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_ENABLETXRXDATA_92D)) { set_sw_LED2(priv, LED_ON); priv->pshare->LED_ToggleStart = LED_ON; } else if (LED_TYPE == LEDTYPE_SW_ADATA_GDATA) { priv->pshare->LED_ToggleStart = LED_ON; if (priv->pshare->curr_band == BAND_5G) { set_sw_LED0(priv, LED_ON); set_sw_LED1(priv, LED_OFF); } else { // 11G set_sw_LED0(priv, LED_OFF); set_sw_LED1(priv, LED_ON); } } else if (LED_TYPE == LEDTYPE_SW_ENABLETXRXDATA_1) { set_sw_LED0(priv, LED_OFF); set_sw_LED1(priv, LED_ON); priv->pshare->LED_ToggleStart = LED_ON; } else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ENABLETXRXDATA) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_ASOCTXRXDATA) ) { set_sw_LED2(priv, LED_ON); priv->pshare->LED_ToggleStart = LED_ON; } else if ((LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRX) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO10_LINKTXRX) || (LED_TYPE == LEDTYPE_SW_LED2_GPIO8_LINKTXRXDATA)) { set_sw_LED2(priv, LED_OFF); } else { set_sw_LED0(priv, LED_OFF); set_sw_LED1(priv, LED_OFF); set_sw_LED2(priv, LED_OFF); } #if (defined(HW_ANT_SWITCH) || defined(SW_ANT_SWITCH))&&( defined(CONFIG_RTL_92C_SUPPORT) || defined(CONFIG_RTL_92D_SUPPORT)) RTL_W32(LEDCFG, b23 | RTL_R32(LEDCFG)); #endif if (init) { #ifdef __KERNEL__ init_timer(&priv->pshare->LED_Timer); priv->pshare->LED_Timer.data = (unsigned long) priv; priv->pshare->LED_Timer.function = &LED_Interval_timeout; #elif defined(__ECOS) init_timer(&priv->pshare->LED_Timer, (unsigned long)priv, LED_Interval_timeout); #endif mod_timer(&priv->pshare->LED_Timer, jiffies + priv->pshare->LED_Interval); } }
static void rtl8169_hw_start(struct net_device *dev) { struct rtl8169_private *tp = dev->priv; void *ioaddr = tp->mmio_addr; u32 i; /* Soft reset the chip. */ RTL_W8(ChipCmd, CmdReset); /* Check that the chip has finished the reset. */ for (i = 1000; i > 0; i--) { if ((RTL_R8(ChipCmd) & CmdReset) == 0) break; else udelay(10); } RTL_W8(Cfg9346, Cfg9346_Unlock); RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); RTL_W8(EarlyTxThres, EarlyTxThld); // For gigabit rtl8169 RTL_W16(RxMaxSize, RxPacketMaxSize); // Set Rx Config register i = rtl8169_rx_config | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset]. RxConfigMask); RTL_W32(RxConfig, i); /* Set DMA burst size and Interframe Gap Time */ RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift)); tp->cp_cmd |= RTL_R16(CPlusCmd); RTL_W16(CPlusCmd, tp->cp_cmd); if (tp->mac_version == RTL_GIGA_MAC_VER_D) { dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14 MUST be 1\n"); tp->cp_cmd |= (1 << 14) | PCIMulRW; RTL_W16(CPlusCmd, tp->cp_cmd); } tp->cur_rx = 0; RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK)); RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK)); RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); RTL_W8(Cfg9346, Cfg9346_Lock); udelay(10); RTL_W32(RxMissed, 0); rtl8169_set_rx_mode(dev); /* no early-rx interrupts */ RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); /* Enable all known interrupts by setting the interrupt mask. */ RTL_W16(IntrMask, rtl8169_intr_mask); netif_start_queue(dev); }
static int OOB_set_ip_mac(struct rtl8168_private *tp, struct sockaddr_in *sa, u8 *mac) { u32 data; if (tp->mcfg == CFG_METHOD_13) { OCP_write(tp, 0xF, 0xd0, be32_to_cpu(sa->sin_addr.s_addr)); memcpy(&data, mac, 4); OCP_write(tp, 0xF, 0x00, le32_to_cpu(data)); data = 0; memcpy(&data, mac + 4, 2); OCP_write(tp, 0x3, 0x04, le32_to_cpu(data)); OOB_notify(tp, OOB_CMD_SET_IPMAC); } else if (tp->mcfg == CFG_METHOD_17) { void __iomem *ioaddr = tp->mmio_addr; struct net_device *dev = tp->dev; u32 rx_mode; rx_mode = RTL_R32(RxConfig); if (netif_running(dev)) { netif_stop_queue(dev); RTL_W32(RxConfig, rx_mode & ~0x3f); while ((RTL_R8(0xd3) & (BIT_5 | BIT_4)) != ((BIT_5 | BIT_4))) udelay(20); RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); // } else { // unsigned long flags; // // spin_lock_irqsave(&tp->phy_lock, flags); // mdio_write(tp, 0x1f, 0x0000); // data = mdio_read(tp, MII_CTRL1000); // data &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); // mdio_write(tp, MII_CTRL1000, data); // mdio_write(tp, 0x00, 0x9200); // spin_unlock_irqrestore(&tp->phy_lock, flags); // // ssleep(3); // RTL_W16(IntrStatus, RTL_R16(IntrStatus)); // // RTL_W32(MAR0, 0); // RTL_W32(MAR0 + 4, 0); // RTL_W16(RxMaxSize, 0x05f3); } RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7); rtl8168_eri_write(ioaddr, 0x180, 4, 0x06080888, ERIAR_ExGMAC); rtl8168_eri_write(ioaddr, 0x184, 4, 0xdd860008, ERIAR_ExGMAC); memcpy(&data, mac, 2); rtl8168_eri_write(ioaddr, 0xf0, 4, (le32_to_cpu(data) << 16), ERIAR_ExGMAC); memcpy(&data, mac + 2, 4); rtl8168_eri_write(ioaddr, 0xf4, 4, le32_to_cpu(data), ERIAR_ExGMAC); rtl8168_eri_write(ioaddr, 0x190, 4, 0x3c110600, ERIAR_ExGMAC); rtl8168_eri_write(ioaddr, 0x194, 4, 0x2c32332b, ERIAR_ExGMAC); rtl8168_eri_write(ioaddr, 0x198, 4, 0x003a0201, ERIAR_ExGMAC); rtl8168_eri_write(ioaddr, 0x19c, 4, 0x00000000, ERIAR_ExGMAC); rtl8168_eri_write(ioaddr, 0x1f0, 4, cpu_to_le32(sa->sin_addr.s_addr), ERIAR_ExGMAC); memcpy(&data, mac, 4); rtl8168_eri_write(ioaddr, 0x258, 4, le32_to_cpu(data), ERIAR_ExGMAC); memcpy(&data, mac + 4, 2); rtl8168_eri_write(ioaddr, 0x25c, 2, le32_to_cpu(data), ERIAR_ExGMAC); RTL_W8(0xe0, RTL_R8(0xe0) | BIT_6); while (!(RTL_R8(0xd3) & BIT_1)) udelay(20); RTL_W32(0xb0, 0x9800e035); RTL_W32(0xb0, 0x9801e034); RTL_W32(0xb0, 0x9802e019); RTL_W32(0xb0, 0x98039918); RTL_W32(0xb0, 0x9804c011); RTL_W32(0xb0, 0x98057100); RTL_W32(0xb0, 0x9806499f); RTL_W32(0xb0, 0x9807f011); RTL_W32(0xb0, 0x9808c00e); RTL_W32(0xb0, 0x98097100); RTL_W32(0xb0, 0x980A4995); RTL_W32(0xb0, 0x980Bf00d); RTL_W32(0xb0, 0x980C4895); RTL_W32(0xb0, 0x980D9900); RTL_W32(0xb0, 0x980Ec009); RTL_W32(0xb0, 0x980F7100); RTL_W32(0xb0, 0x98104890); RTL_W32(0xb0, 0x98119900); RTL_W32(0xb0, 0x98124810); RTL_W32(0xb0, 0x98139900); RTL_W32(0xb0, 0x9814e004); RTL_W32(0xb0, 0x9815d44e); RTL_W32(0xb0, 0x9816d506); RTL_W32(0xb0, 0x9817c0b4); RTL_W32(0xb0, 0x9818c002); RTL_W32(0xb0, 0x9819b800); RTL_W32(0xb0, 0x981A0500); RTL_W32(0xb0, 0x981B1a26); RTL_W32(0xb0, 0x981Ca4ca); RTL_W32(0xb0, 0x981D21bc); RTL_W32(0xb0, 0x981E25bc); RTL_W32(0xb0, 0x981F1305); RTL_W32(0xb0, 0x9820f00d); RTL_W32(0xb0, 0x9821c213); RTL_W32(0xb0, 0x98227340); RTL_W32(0xb0, 0x982349b0); RTL_W32(0xb0, 0x9824f009); RTL_W32(0xb0, 0x98251a3a); RTL_W32(0xb0, 0x9826a4ca); RTL_W32(0xb0, 0x982721b9); RTL_W32(0xb0, 0x982825b9); RTL_W32(0xb0, 0x98291303); RTL_W32(0xb0, 0x982Af006); RTL_W32(0xb0, 0x982B1309); RTL_W32(0xb0, 0x982Cf004); RTL_W32(0xb0, 0x982Dc306); RTL_W32(0xb0, 0x982E1a26); RTL_W32(0xb0, 0x982Fbb00); RTL_W32(0xb0, 0x9830c302); RTL_W32(0xb0, 0x9831bb00); RTL_W32(0xb0, 0x98320f3e); RTL_W32(0xb0, 0x98330f4e); RTL_W32(0xb0, 0x9834c0ae); RTL_W32(0xb0, 0x98351800); RTL_W32(0xb0, 0x9836b800); RTL_W32(0xb0, 0xfe173000); RTL_W32(0xb0, 0xfe1604ff); RTL_W32(0xb0, 0xfe150f4d); data = rtl8168_eri_read(ioaddr, 0xd6, 1, ERIAR_ExGMAC); rtl8168_eri_write(ioaddr, 0xd6, 1, data | BIT_0, ERIAR_ExGMAC); if (netif_running(dev)) { rtl8168_init_ring_indexes(tp); RTL_W8(ChipCmd, CmdRxEnb | CmdTxEnb); RTL_W32(RxConfig, rx_mode); netif_wake_queue(dev); } else { RTL_W8(0xD3, RTL_R8(0xD3) | BIT_7); // data = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC); // data &= ~BIT_0; // rtl8168_eri_write( ioaddr, 0xDC, 1, data, ERIAR_ExGMAC); // data |= BIT_0; // rtl8168_eri_write( ioaddr, 0xDC, 1, data, ERIAR_ExGMAC); RTL_W32(RxConfig, rx_mode | 0x0e); } } else { return -EFAULT; } return 0; }
int ARFBRefresh(struct rtl8192cd_priv *priv, PSTATION_RA_INFO pRaInfo) { // Wilson 2011/10/26 unsigned int MaskFromReg; unsigned char i,j; // Test for Wilson RTL_W16(REG_88E_TXRPT_TIM, DefaultTxRPTTiming); //200ms RTL_W32(DARFRC, 0x04020100); RTL_W32(DARFRC+4, 0x0a080706); switch(pRaInfo->RateID) { case RATR_INX_WIRELESS_NGB: pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff015; break; case RATR_INX_WIRELESS_NG: pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff010; break; case RATR_INX_WIRELESS_NB: pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff005; break; case RATR_INX_WIRELESS_N: pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0f8ff000; break; case RATR_INX_WIRELESS_GB: pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff5; break; case RATR_INX_WIRELESS_G: pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x00000ff0; break; case RATR_INX_WIRELESS_B: pRaInfo->RAUseRate=(pRaInfo->RateMask)&0x0000000d; break; case 12: MaskFromReg=RTL_R32(ARFR0); pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; break; case 13: MaskFromReg=RTL_R32(ARFR1); pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; break; case 14: MaskFromReg=RTL_R32(ARFR2); pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; break; case 15: MaskFromReg=RTL_R32(ARFR3); pRaInfo->RAUseRate=(pRaInfo->RateMask)&MaskFromReg; break; default: pRaInfo->RAUseRate=(pRaInfo->RateMask); break; } // Highest rate if (pRaInfo->RAUseRate) { for (i=RATESIZE;i>=0;i--) { if((pRaInfo->RAUseRate)&BIT(i)) { pRaInfo->HighestRate=i; break; } } } else { pRaInfo->HighestRate=0; } // Lowest rate if (pRaInfo->RAUseRate) { for (i=0;i<RATESIZE;i++) { if((pRaInfo->RAUseRate)&BIT(i)) { pRaInfo->LowestRate=i; break; } } } else { pRaInfo->LowestRate=0; } #if 0 pRaInfo->RAWaitingCounter=0; pRaInfo->RAExtendCounter=0; #endif /* panic_printk("%s %d: RateID=%d RateMask=%8.8x RAUseRate=%8.8x HighestRate=%d\n", __FUNCTION__, __LINE__, pRaInfo->RateID, pRaInfo->RateMask, pRaInfo->RAUseRate, pRaInfo->HighestRate);*/ return 0; }