/* Call the host environment interface to provide a user hook opportunity. */
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT16 Data16;
FcnData = Data;
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
/* Get SB MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch(MemData->ParameterListPtr->DDR3Voltage){
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_25:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_5:
default:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
}
return Status;
}
/* PCIE slot reset control */
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr;
UINT8 Data8;
UINT16 Data16;
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16=Data8<<8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16|=Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId)
{
case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
Status = AGESA_SUCCESS;
break;
}
break;
}
return Status;
}
/* Call the host environment interface to provide a user hook opportunity. */
AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 AcpiMmioAddr;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT16 Data16;
UINT8 TempData8;
FcnData = Data;
MemData = ConfigPtr;
Status = AGESA_SUCCESS;
/* Get SB800 MMIO Base (AcpiMmioAddr) */
WriteIo8 (0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16 = Data8<<8;
WriteIo8 (0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16 |= Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~BIT5;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
TempData8 &= 0x23;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
switch(MemData->ParameterListPtr->DDR3Voltage){
case VOLT1_35:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_25:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
break;
case VOLT1_5:
default:
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
Data8 |= (UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
Data8 &= ~(UINT8)BIT6;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
}
// disable memory clear for boot time reduction
MemData->ParameterListPtr->EnableMemClr = FALSE;
return Status;
}
/* PCIE slot reset control */
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr;
UINT8 Data8;
UINT16 Data16;
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB800 MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16=Data8<<8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16|=Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
switch (ResetInfo->ResetId)
{
case 4:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
}
break;
case 6:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
}
break;
case 7:
switch (ResetInfo->ResetControl) {
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02
Status = AGESA_SUCCESS;
break;
}
break;
}
return Status;
}
/* PCIE slot reset control */
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr;
UINT32 AcpiMmioAddr;
UINT8 Data8;
UINT16 Data16;
FcnData = Data;
ResetInfo = ConfigPtr;
// Get SB MMIO Base (AcpiMmioAddr)
WriteIo8(0xCD6, 0x27);
Data8 = ReadIo8(0xCD7);
Data16=Data8<<8;
WriteIo8(0xCD6, 0x26);
Data8 = ReadIo8(0xCD7);
Data16|=Data8;
AcpiMmioAddr = (UINT32)Data16 << 16;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
if (ResetInfo->ResetControl == DeassertSlotReset) {
if (ResetInfo->ResetId & (BIT2+BIT3)) { //de-assert
// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
if (Data8 & BIT7) {
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
while (!(Data8 & BIT7)) {
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
}
// GPIO44: PE_GPIO0 MXM Reset
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
Status = AGESA_SUCCESS;
}
} else {
Status = AGESA_UNSUPPORTED;
}
// Travis
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
//DE-Assert ALL PCIE RESET
// APU GPP0 (Dev 4)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
// APU GPP1 (Dev 5)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
// APU GPP2 (Dev 6)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
// APU GPP3 (Dev 7)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
Data8 |= BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
} else {
if (ResetInfo->ResetId & (BIT2+BIT3)) { //Pcie Slot Reset is supported
// GPIO44: PE_GPIO0 MXM Reset
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
Status = AGESA_SUCCESS;
}
// Travis
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
Data8 &= ~(UINT8)BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
//Assert ALL PCIE RESET
// APU GPP0 (Dev 4)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
// APU GPP1 (Dev 5)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
// APU GPP2 (Dev 6)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
// APU GPP3 (Dev 7)
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
Data8 &= ~(UINT8)BIT6;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
}
return Status;
}
