uint8 ReadMiscOutReg() { if (gInfo.sharedInfo->chipType == S3_TRIO64) return ReadPIO_8(0x3cc); return INREG8(0x83cc); }
uint8 ReadSeqReg(uint8 index) { if (gInfo.sharedInfo->chipType == S3_TRIO64) { WritePIO_8(0x3c4, index); return ReadPIO_8(0x3c5); } OUTREG8(0x83c4, index); return INREG8(0x83c5); }
void WriteSeqReg(uint8 index, uint8 value, uint8 mask) { // Write a value to a Sequencer reg using a mask. The mask selects the // bits to be modified. if (gInfo.sharedInfo->chipType == S3_TRIO64) { WritePIO_8(0x3c4, index); WritePIO_8(0x3c5, (ReadPIO_8(0x3c5) & ~mask) | (value & mask)); } else { OUTREG8(0x83c4, index); OUTREG8(0x83c5, (INREG8(0x83c5) & ~mask) | (value & mask)); } }
status_t Virge_Init(void) { TRACE("Virge_Init()\n"); SharedInfo& si = *gInfo.sharedInfo; // Use PIO for following operations since MMIO may not be currently enabled. WritePIO_8(VGA_ENABLE, ReadPIO_8(VGA_ENABLE) | 0x01); // enable VGA WritePIO_8(MISC_OUT_W, ReadPIO_8(MISC_OUT_R) | 0x01); // enable color // Set linear base register to the PCI register value; // some DX chipsets don't seem to do it automatically. WritePIO_8(CRTC_INDEX, 0x59); WritePIO_8(CRTC_DATA, (uint32)(si.videoMemPCI) >> 24); WritePIO_8(CRTC_INDEX, 0x5A); WritePIO_8(CRTC_DATA, (uint32)(si.videoMemPCI) >> 16); // Enable MMIO. WritePIO_8(CRTC_INDEX, 0x53); WritePIO_8(CRTC_DATA, ReadPIO_8(CRTC_DATA) | 0x8); if (si.chipType == S3_TRIO_3D) WriteCrtcReg(0x40, 0x01, 0x01); // Detect amount of installed ram. uint8 config1 = ReadCrtcReg(0x36); // get amount of vram installed uint8 config2 = ReadCrtcReg(0x37); // get amount of off-screen ram // Compute the amount of video memory and offscreen memory. int ramOffScreenMB = 0; // off screen memory size in megabytes int ramSizeMB = 0; // memory size in megabytes if (si.chipType == S3_VIRGE_VX) { switch ((config2 & 0x60) >> 5) { case 1: ramOffScreenMB = 4; break; case 2: ramOffScreenMB = 2; break; } switch ((config1 & 0x60) >> 5) { case 0: ramSizeMB = 2; break; case 1: ramSizeMB = 4; break; case 2: ramSizeMB = 6; break; case 3: ramSizeMB = 8; break; } ramSizeMB -= ramOffScreenMB; } else if (si.chipType == S3_TRIO_3D_2X) {