void check_maca(void) {
safe_irq_disable(MACA);
static volatile uint32_t last_time;
static volatile uint32_t last_entry;
volatile uint32_t i;
#if DEBUG_MACA
volatile uint32_t count;
#endif
/* if *MACA_CLK == last_time */
/* try waiting for one clock period */
/* since maybe check_maca is getting called quickly */
for(i=0; (i < 1024) && (*MACA_CLK == last_time); i++) {
continue;
}
if(*MACA_CLK == last_time) {
PRINTF("check maca: maca_clk stopped, restarting\n");
/* clock isn't running */
ResumeMACASync();
*INTFRC = (1<<INT_NUM_MACA);
} else {
if((last_time > (*MACA_SFTCLK + RECV_SOFTIMEOUT)) &&
(last_time > (*MACA_CPLCLK + CPL_TIMEOUT))) {
PRINTF("check maca: complete clocks expired\n");
/* all complete clocks have expired */
/* check that maca entry is changing */
/* if not, do call the isr to restart the cycle */
if(last_entry == maca_entry) {
PRINTF("check maca: forcing isr\n");
*INTFRC = (1<<INT_NUM_MACA);
}
}
}
last_entry = maca_entry;
last_time = *MACA_CLK;
#if DEBUG_MACA
if((count = count_packets()) != NUM_PACKETS) {
PRINTF("check maca: count_packets %d\n", count);
Print_Packets("check_maca");
#if PACKET_STATS
for(i=0; i<NUM_PACKETS; i++) {
printf("packet 0x%lx seen %d post_tx %d get_free %d rxd %d\n",
(uint32_t) &packet_pool[i],
packet_pool[i].seen,
packet_pool[i].post_tx,
packet_pool[i].get_free,
packet_pool[i].rxd);
}
#endif
if(bit_is_set(*NIPEND, INT_NUM_MACA)) {
*INTFRC = (1 << INT_NUM_MACA);
}
}
#endif /* DEBUG_MACA */
irq_restore();
}
void maca_isr(void) {
// print_packets("maca_isr");
maca_entry++;
if (bit_is_set(*MACA_STATUS, maca_status_ovr))
{ PRINTF("maca overrun\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_busy))
{ PRINTF("maca busy\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_crc))
{ PRINTF("maca crc error\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_to))
{ PRINTF("maca timeout\n\r"); }
if (data_indication_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_di);
if (dma_rx != &dummy_ack && dma_rx != &dummy_rx)
{
dma_rx->length = *MACA_GETRXLVL - 2; /* packet length does not include FCS */
dma_rx->lqi = get_lqi();
dma_rx->rx_time = *MACA_TIMESTAMP;
/* check if received packet needs an ack */
if(prm_mode == AUTOACK && (dma_rx->data[1] & 0x20)) {
/* this wait is necessary to auto-ack */
volatile uint32_t wait_clk;
wait_clk = *MACA_CLK + 200;
while(*MACA_CLK < wait_clk) { continue; }
}
if(maca_rx_callback != 0) { maca_rx_callback(dma_rx); }
add_to_rx(dma_rx);
}
dma_rx = 0;
}
if (filter_failed_irq()) {
PRINTF("maca filter failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_flt);
}
if (checksum_failed_irq()) {
PRINTF("maca checksum failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_crc);
}
if (softclock_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_sftclk);
}
if (poll_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_poll);
}
if(action_complete_irq()) {
/* PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE)); */
if(last_post == TX_POST) {
tx_head->status = get_field(*MACA_STATUS,CODE);
#if MACA_INSERT_ACK
/* Having sent a message with the acknowledge request flag set the
* MACA hardware will only give a tx success indication if the message
* was acknowledged by the remote node. We need to detect this
* condition and inject an ACK packet into the internal receive stream
* as the higher layers are expecting to see an ACK packet.*/
if(tx_head->status == SUCCESS && (tx_head->data[0] & MAC_ACK_REQUEST_FLAG)) {
/* Create the dummy ack packet */
static volatile packet_t *ack_p;
if(ack_p = get_free_packet()) {
ack_p->length = 3;
ack_p->offset = 1;
ack_p->data[0] = 3;
ack_p->data[1] = 0x02;
ack_p->data[2] = 0;
ack_p->data[3] = *MACA_TXSEQNR;
insert_at_rx_head(ack_p);
}
}
#endif
if(maca_tx_callback != 0) { maca_tx_callback(tx_head); }
dma_tx = 0;
free_tx_head();
last_post = NO_POST;
}
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_acpl);
}
decode_status();
if (*MACA_IRQ != 0)
{ PRINTF("*MACA_IRQ %x\n\r", (unsigned int)*MACA_IRQ); }
if(tx_head != 0) {
post_tx();
} else {
post_receive();
}
}
void decode_status(void) {
volatile uint32_t code;
code = get_field(*MACA_STATUS,CODE);
/* PRINTF("status code 0x%x\n\r",code); */
switch(code)
{
case ABORTED:
{
PRINTF("maca: aborted\n\r");
ResumeMACASync();
break;
}
case NOT_COMPLETED:
{
PRINTF("maca: not completed\n\r");
ResumeMACASync();
break;
}
case CODE_TIMEOUT:
{
PRINTF("maca: timeout\n\r");
ResumeMACASync();
break;
}
case NO_ACK:
{
PRINTF("maca: no ack\n\r");
ResumeMACASync();
break;
}
case EXT_TIMEOUT:
{
PRINTF("maca: ext timeout\n\r");
ResumeMACASync();
break;
}
case EXT_PND_TIMEOUT:
{
PRINTF("maca: ext pnd timeout\n\r");
ResumeMACASync();
break;
}
case SUCCESS:
{
//PRINTF("maca: success\n\r");
ResumeMACASync();
break;
}
default:
{
PRINTF("status: %x", (unsigned int)*MACA_STATUS);
ResumeMACASync();
}
}
}
void maca_isr(void) {
// print_packets("maca_isr");
maca_entry++;
if (bit_is_set(*MACA_STATUS, maca_status_ovr))
{ PRINTF("maca overrun\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_busy))
{ PRINTF("maca busy\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_crc))
{ PRINTF("maca crc error\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_to))
{ PRINTF("maca timeout\n\r"); }
if (data_indication_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_di);
dma_rx->length = *MACA_GETRXLVL - 2; /* packet length does not include FCS */
// PRINTF("maca data ind %x %d\n\r", dma_rx, dma_rx->length);
if(maca_rx_callback != 0) { maca_rx_callback(dma_rx); }
add_to_rx(dma_rx);
dma_rx = 0;
}
if (filter_failed_irq()) {
PRINTF("maca filter failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_flt);
}
if (checksum_failed_irq()) {
PRINTF("maca checksum failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_crc);
}
if (softclock_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_sftclk);
}
if (poll_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_poll);
}
if(action_complete_irq()) {
/* PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE)); */
if(last_post == TX_POST) {
if(maca_tx_callback != 0) { maca_tx_callback(tx_head); }
dma_tx = 0;
free_tx_head();
last_post = NO_POST;
}
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_acpl);
}
decode_status();
if (*MACA_IRQ != 0)
{ PRINTF("*MACA_IRQ %x\n\r", *MACA_IRQ); }
if(tx_head != 0) {
post_tx();
} else {
post_receive();
}
}
void maca_isr(void) {
// print_packets("maca_isr");
maca_entry++;
if (bit_is_set(*MACA_STATUS, maca_status_ovr))
{ PRINTF("maca overrun\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_busy))
{ PRINTF("maca busy\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_crc))
{ PRINTF("maca crc error\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_to))
{ PRINTF("maca timeout\n\r"); }
if (data_indication_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_di);
dma_rx->length = *MACA_GETRXLVL - 2; /* packet length does not include FCS */
dma_rx->lqi = get_lqi();
dma_rx->rx_time = *MACA_TIMESTAMP;
/* check if received packet needs an ack */
if(dma_rx->data[1] & 0x20) {
/* this wait is necessary to auto-ack */
volatile uint32_t wait_clk;
wait_clk = *MACA_CLK + 200;
while(*MACA_CLK < wait_clk) { continue; }
}
if(maca_rx_callback != 0) { maca_rx_callback(dma_rx); }
add_to_rx(dma_rx);
dma_rx = 0;
}
if (filter_failed_irq()) {
PRINTF("maca filter failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_flt);
}
if (checksum_failed_irq()) {
PRINTF("maca checksum failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_crc);
}
if (softclock_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_sftclk);
}
if (poll_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_poll);
}
if(action_complete_irq()) {
/* PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE)); */
if(last_post == TX_POST) {
tx_head->status = get_field(*MACA_STATUS,CODE);
if(maca_tx_callback != 0) { maca_tx_callback(tx_head); }
dma_tx = 0;
free_tx_head();
last_post = NO_POST;
}
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_acpl);
}
decode_status();
if (*MACA_IRQ != 0)
{ PRINTF("*MACA_IRQ %x\n\r", (unsigned int)*MACA_IRQ); }
if(tx_head != 0) {
post_tx();
} else {
post_receive();
}
}
