void asm_S9xOpcode_IRQ(void) { #ifdef __debug_c_irq__ printf("irq\n"); #endif // S9xUnpackStatus(); // not needed if (!CheckEmulation()) { PushB (Registers.PB); PushW (CPU.PC - CPU.PCBase); // S9xPackStatus (); // not needed PushB (Registers.PL); ClearDecimal (); SetIRQ (); Registers.PB = 0; // ICPU.ShiftedPB = 0; // unused #ifdef USE_SA1 if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40)) S9xSetPCBase (Memory.FillRAM [0x220e] | (Memory.FillRAM [0x220f] << 8)); else #endif S9xSetPCBase (S9xGetWord (0xFFEE)); #ifdef VAR_CYCLES CPU.Cycles += TWO_CYCLES; #else CPU.Cycles += 8; #endif } else { PushW (CPU.PC - CPU.PCBase); // S9xPackStatus (); // not needed PushB (Registers.PL); ClearDecimal (); SetIRQ (); Registers.PB = 0; // ICPU.ShiftedPB = 0; // unused #ifdef USE_SA1 if (Settings.SA1 && (Memory.FillRAM [0x2209] & 0x40)) S9xSetPCBase (Memory.FillRAM [0x220e] | (Memory.FillRAM [0x220f] << 8)); else #endif S9xSetPCBase (S9xGetWord (0xFFFE)); #ifdef VAR_CYCLES CPU.Cycles += ONE_CYCLE; #else CPU.Cycles += 6; #endif } // S9xPackStatus(); // not needed }
static INLINE bool8 HDMAReadLineCount (int d) { /* CPU.InDMA is set, so S9xGetXXX() / S9xSetXXX() incur no charges. */ uint8 line; line = S9xGetByte((DMA[d].ABank << 16) + DMA[d].Address); CPU.Cycles += SLOW_ONE_CYCLE; DMA[d].LineCount = 128; if (!line) { DMA[d].Repeat = FALSE; if (DMA[d].HDMAIndirectAddressing) { if (PPU.HDMA & (0xfe << d)) { DMA[d].Address++; CPU.Cycles += (SLOW_ONE_CYCLE << 1); } else CPU.Cycles += SLOW_ONE_CYCLE; DMA[d].IndirectAddress = S9xGetWord((DMA[d].ABank << 16) + DMA[d].Address, WRAP_NONE); DMA[d].Address++; } DMA[d].Address++; HDMAMemPointers[d] = NULL; return (FALSE); } else if (line == 0x80) DMA[d].Repeat = TRUE; else { DMA[d].Repeat = !(line & 0x80); DMA[d].LineCount = line & 0x7f; } DMA[d].Address++; DMA[d].DoTransfer = TRUE; if (DMA[d].HDMAIndirectAddressing) { CPU.Cycles += (SLOW_ONE_CYCLE << 1); DMA[d].IndirectAddress = S9xGetWord((DMA[d].ABank << 16) + DMA[d].Address, WRAP_NONE); DMA[d].Address += 2; HDMAMemPointers[d] = S9xGetMemPointer((DMA[d].IndirectBank << 16) + DMA[d].IndirectAddress); } else HDMAMemPointers[d] = S9xGetMemPointer((DMA[d].ABank << 16) + DMA[d].Address); return (TRUE); }
uint16 asm_S9xGetWord(uint32 Address) { #ifdef __debug_c_io__ printf("gw\n"); #endif return S9xGetWord(Address); }
static void S9xSoftResetCPU (void) { CPU.Cycles = 182; // Or 188. This is the cycle count just after the jump to the Reset Vector. CPU.PrevCycles = CPU.Cycles; CPU.V_Counter = 0; CPU.Flags = CPU.Flags & (DEBUG_MODE_FLAG | TRACE_FLAG); CPU.PCBase = NULL; CPU.NMILine = FALSE; CPU.IRQLine = FALSE; CPU.IRQTransition = FALSE; CPU.IRQLastState = FALSE; CPU.IRQExternal = FALSE; CPU.IRQPending = Timings.IRQPendCount; CPU.MemSpeed = SLOW_ONE_CYCLE; CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; CPU.FastROMSpeed = SLOW_ONE_CYCLE; CPU.InDMA = FALSE; CPU.InHDMA = FALSE; CPU.InDMAorHDMA = FALSE; CPU.InWRAMDMAorHDMA = FALSE; CPU.HDMARanInDMA = 0; CPU.CurrentDMAorHDMAChannel = -1; CPU.WhichEvent = HC_RENDER_EVENT; CPU.NextEvent = Timings.RenderPos; CPU.WaitingForInterrupt = FALSE; CPU.AutoSaveTimer = 0; CPU.SRAMModified = FALSE; Registers.PBPC = 0; Registers.PB = 0; Registers.PCw = S9xGetWord(0xfffc); OpenBus = Registers.PCh; Registers.D.W = 0; Registers.DB = 0; Registers.SH = 1; Registers.SL -= 3; Registers.XH = 0; Registers.YH = 0; ICPU.ShiftedPB = 0; ICPU.ShiftedDB = 0; SetFlags(MemoryFlag | IndexFlag | IRQ | Emulation); ClearFlags(Decimal); Timings.InterlaceField = FALSE; Timings.H_Max = Timings.H_Max_Master; Timings.V_Max = Timings.V_Max_Master; Timings.NMITriggerPos = 0xffff; if (Model->_5A22 == 2) Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v2; else Timings.WRAMRefreshPos = SNES_WRAM_REFRESH_HC_v1; S9xSetPCBase(Registers.PBPC); ICPU.S9xOpcodes = S9xOpcodesE1; ICPU.S9xOpLengths = S9xOpLengthsM1X1; S9xUnpackStatus(); }
void S9xResetCPU () { CPUPack.Registers.PB = 0; CPUPack.Registers.PC = S9xGetWord (0xFFFC); CPUPack.Registers.D.W = 0; CPUPack.Registers.DB = 0; CPUPack.Registers.SH = 1; CPUPack.Registers.SL = 0xFF; CPUPack.Registers.XH = 0; CPUPack.Registers.YH = 0; CPUPack.Registers.P.W = 0; CPUPack.ICPU.ShiftedPB = 0; CPUPack.ICPU.ShiftedDB = 0; SetFlags (MemoryFlag | IndexFlag | IRQ | Emulation); ClearFlags (Decimal); CPUPack.CPU.Flags = CPUPack.CPU.Flags & (DEBUG_MODE_FLAG | TRACE_FLAG); CPUPack.CPU.BranchSkip = FALSE; CPUPack.CPU.NMIActive = FALSE; CPUPack.CPU.IRQActive = FALSE; CPUPack.CPU.WaitingForInterrupt = FALSE; CPUPack.CPU.InDMA = FALSE; CPUPack.CPU.WhichEvent = HBLANK_START_EVENT; S9x_Current_HBlank_Event=S9xDoHBlankProcessing_HBLANK_START_EVENT; CPUPack.CPU.PC = NULL; CPUPack.CPU.PCBase = NULL; CPUPack.CPU.PCAtOpcodeStart = NULL; CPUPack.CPU.WaitAddress = NULL; CPUPack.CPU.WaitCounter = 0; CPUPack.CPU.Cycles = 0; old_cpu_cycles=0; cpu_glob_cycles=0; CPUPack.CPU.NextEvent = Settings.HBlankStart; CPUPack.CPU.V_Counter = 0; CPUPack.CPU.MemSpeed = SLOW_ONE_CYCLE; CPUPack.CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; CPUPack.CPU.FastROMSpeed = SLOW_ONE_CYCLE; CPUPack.CPU.AutoSaveTimer = 0; CPUPack.CPU.SRAMModified = FALSE; // CPUPack.CPU.NMITriggerPoint = 4; // Set when ROM image loaded CPUPack.CPU.BRKTriggered = FALSE; //CPUPack.CPU.TriedInterleavedMode2 = FALSE; // Reset when ROM image loaded CPUPack.CPU.NMICycleCount = 0; CPUPack.CPU.IRQCycleCount = 0; S9xSetPCBase (CPUPack.Registers.PC); #ifndef VAR_CYCLES CPUPack.ICPU.Speed = S9xE1M1X1; #endif CPUPack.ICPU.S9xOpcodes = S9xOpcodesM1X1; CPUPack.ICPU.CPUExecuting = TRUE; S9xUnpackStatus(); }
void S9xResetCPU() { ICPU.Registers.PB = 0; ICPU.Registers.PC = S9xGetWord(0xFFFC); ICPU.Registers.D.W = 0; ICPU.Registers.DB = 0; ICPU.Registers.SH = 1; ICPU.Registers.SL = 0xFF; ICPU.Registers.XH = 0; ICPU.Registers.YH = 0; ICPU.Registers.P.W = 0; ICPU.ShiftedPB = 0; ICPU.ShiftedDB = 0; SetFlags(MemoryFlag | IndexFlag | IRQ | Emulation); ClearFlags(Decimal); CPU.Flags = CPU.Flags & (DEBUG_MODE_FLAG | TRACE_FLAG); CPU.BranchSkip = false; CPU.NMIActive = false; CPU.IRQActive = false; CPU.WaitingForInterrupt = false; CPU.InDMA = false; CPU.WhichEvent = HBLANK_START_EVENT; CPU.PC = NULL; CPU.PCBase = NULL; CPU.PCAtOpcodeStart = NULL; CPU.WaitAddress = NULL; CPU.WaitCounter = 0; CPU.Cycles = 0; CPU.NextEvent = Settings.HBlankStart; CPU.V_Counter = 0; CPU.MemSpeed = SLOW_ONE_CYCLE; CPU.MemSpeedx2 = SLOW_ONE_CYCLE * 2; CPU.FastROMSpeed = SLOW_ONE_CYCLE; CPU.AutoSaveTimer = 0; CPU.SRAMModified = false; // CPU.NMITriggerPoint = 4; // Set when ROM image loaded CPU.BRKTriggered = false; //CPU.TriedInterleavedMode2 = false; // Reset when ROM image loaded CPU.NMICycleCount = 0; CPU.IRQCycleCount = 0; S9xSetPCBase(ICPU.Registers.PC); ICPU.S9xOpcodes = S9xOpcodesE1; ICPU.CPUExecuting = true; S9xUnpackStatus(); }