///
/// read one or more word(s) from the VS1001 Control registers
///
void vs1001::read(uint8 address, uint16 count, uint16 *pData)
{
uint8 i;
#ifdef VS1000_NEW
SBI( xDCS_PORT, xDCS_PIN ); // xDCS hi
#else
CBI( BSYNC_PORT, BSYNC_PIN ); // byte sync lo
#endif
CBI( MP3_PORT, MP3_PIN); // xCS lo
write_byte_spi(VS1001_READ);
write_byte_spi(address);
while (count--)
{
*pData = write_byte_spi(0) << 8;
*pData++ |= write_byte_spi(0);
}
SBI( MP3_PORT, MP3_PIN); // xCS hi
//this is absolutely neccessary!
//delay(5); //wait 5 microseconds after sending data to control port
for (i=0;i<8;i++)
asm volatile("nop");
}
///
/// send a byte to the VS1001 MPEG stream
///
void vs1001::send_data(unsigned char b)
{
char i;
#ifdef VS1000_NEW
CBI( xDCS_PORT, xDCS_PIN ); // XDCS lo
#else
SBI( BSYNC_PORT, BSYNC_PIN ); // byte sync hi
#endif
// outp(b, SPDR); // send data
SPDR = b; // send data
// release BSYNC before end of byte
#ifndef VS1000_NEW
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
CBI( BSYNC_PORT, BSYNC_PIN ); // byte sync lo
#endif
// wait for data to be sent
loop_until_bit_is_set(SPSR, SPIF);
//release xDCS after byte has been sent
#ifdef VS1000_NEW
SBI( xDCS_PORT, xDCS_PIN ); // byte XDCS hi
#endif
i = SPDR; // clear SPIF
}
///
/// write one or more word(s) to the VS1001 Control registers
///
void vs1001::write(uint8 address, uint16 count, uint16 *pData)
{
uint8 i;
#ifdef VS1000_NEW
SBI( xDCS_PORT, xDCS_PIN ); // xDCS hi
#else
CBI( BSYNC_PORT, BSYNC_PIN ); // byte sync lo
#endif
CBI( MP3_PORT, MP3_PIN); // xCS lo
write_byte_spi(VS1001_WRITE);
write_byte_spi(address);
while (count--)
{
write_byte_spi((uint8)((*pData) >> 8));
write_byte_spi((uint8)*pData);
pData++;
}
SBI( MP3_PORT, MP3_PIN); // xCS hi
//this is absolutely neccessary!
//delay(5); //wait 5 microseconds after sending data to control port
for (i=0;i<16;i++)
asm volatile("nop");
//Note: VS1011e sets DREQ low after each SCI operation. The duration depends on the operation. It is
// not allowed to start a new SCI/SDI operation before DREQ is high again.
loop_until_bit_is_set(DREQ_PORT, DREQ_PIN);
}
static void capifs_put_super(struct super_block *sb)
{
struct capifs_sb_info *sbi = SBI(sb);
struct inode *inode;
int i;
for ( i = 0 ; i < sbi->max_ncci ; i++ ) {
if ( (inode = sbi->nccis[i].inode) ) {
if (atomic_read(&inode->i_count) != 1 )
printk("capifs_put_super: badness: entry %d count %d\n",
i, (unsigned)atomic_read(&inode->i_count));
inode->i_nlink--;
iput(inode);
}
}
*sbi->back = sbi->next;
if ( sbi->next )
SBI(sbi->next)->back = sbi->back;
kfree(sbi->nccis);
kfree(sbi);
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,3,51)
MOD_DEC_USE_COUNT;
#endif
}
void MarlinSerial::begin(long baud) {
uint16_t baud_setting;
bool useU2X = true;
#if F_CPU == 16000000UL && SERIAL_PORT == 0
// hard-coded exception for compatibility with the bootloader shipped
// with the Duemilanove and previous boards and the firmware on the 8U2
// on the Uno and Mega 2560.
if (baud == 57600) {
useU2X = false;
}
#endif
if (useU2X) {
M_UCSRxA = _BV(M_U2Xx);
baud_setting = (F_CPU / 4 / baud - 1) / 2;
}
else {
M_UCSRxA = 0;
baud_setting = (F_CPU / 8 / baud - 1) / 2;
}
// assign the baud_setting, a.k.a. ubbr (USART Baud Rate Register)
M_UBRRxH = baud_setting >> 8;
M_UBRRxL = baud_setting;
SBI(M_UCSRxB, M_RXENx);
SBI(M_UCSRxB, M_TXENx);
SBI(M_UCSRxB, M_RXCIEx);
}
SBI opcja_tekst::EventProc(sf::Event event)
{
//cout << "otrzymano event";
//cout << "dla elem: "<< dan->elem->AktTresc() << "\n";
if (event.Type==sf::Event::MouseButtonPressed)
{
return SBI(true);
}
if (event.Type==sf::Event::KeyPressed)
{
cout << "otrzymano klawiszowy event";
if (event.Key.Code==sf::Key::Return||event.Key.Code==sf::Key::Escape||event.Key.Code==sf::Key::Left||event.Key.Code==sf::Key::Right)
return SBI(true);
cout << " nie exituje... \n";
if (dan->czyliczba&&(((char)event.Key.Code>=(char)sf::Key::Num0&&(char)event.Key.Code<=(char)sf::Key::Num9)||event.Key.Code==sf::Key::Up||event.Key.Code==sf::Key::Down))//
{
cout << " edytujesz liczbe :) ";
dan->elem->EdycjaUserLiczby(dan->min,dan->max,event.Key.Code);
}
if ((((char)event.Key.Code>='a'&&(char)event.Key.Code<='z')||((char)event.Key.Code>='0'&&(char)event.Key.Code<='9')||event.Key.Code==sf::Key::Period||event.Key.Code==sf::Key::Back)&&!(dan->czyliczba))
{
cout << "edytujesz klawisz :) ";
dan->elem->EdycjaUserStringa(event.Key.Code,event.Key.Shift,dan->min, dan->max);
}
}
return SBI();
}
///
/// send a burst of 32 data bytes to the VS1001 MPEG stream
///
void vs1001::send_32(unsigned char *p)
{
int j;
#ifdef VS1000_NEW
CBI( xDCS_PORT, xDCS_PIN ); // xDCS lo
#else
SBI( BSYNC_PORT, BSYNC_PIN ); // byte sync hi
#endif
for (j=0;j<31;j++)
{
SPDR = *p++ ; // send data
// wait for data to be sent
loop_until_bit_is_set(SPSR, SPIF);
}
SPDR = *p++ ; // send last byte
#ifndef VS1000_NEW
// release BSYNC before last bit of last byte.
asm volatile("nop");
asm volatile("nop");
asm volatile("nop");
CBI( BSYNC_PORT, BSYNC_PIN ); // byte sync lo
#endif
// wait for data to be sent
loop_until_bit_is_set(SPSR, SPIF);
#ifdef VS1000_NEW
SBI( xDCS_PORT, xDCS_PIN ); // xDCS hi
#endif
j = SPDR; // clear SPIF
}
/// reset the VS1001
void vs1001::reset(reset_e r)
{
uint16 buf[2];
if (r == SOFT_RESET)
{
// delay(200); // 200 mS
SPSR = (0<<SPI2X); //set spi to Fosc/4
// set SW reset bit
buf[0] = SM_RESET ;
vs1001::write(SCI_MODE,1,buf); // set bit 2
delay(2); // 2 mS
while( !((DREQ_PORT) & (1<<DREQ_PIN)) ); //wait for DREQ
CBI( MP3_PORT, MP3_PIN); // output low (select MP3)
#ifdef VS1000_NEW
//send a pulse to ensure BSYNC Counter has been reset
CBI( xDCS_PORT, xDCS_PIN ); // output Low
SBI( xDCS_PORT, xDCS_PIN ); // output High
#else
//send a pulse to ensure BSYNC Counter has been reset
SBI( BSYNC_PORT, BSYNC_PIN ); // output High
CBI( BSYNC_PORT, BSYNC_PIN ); // output low
#endif
SBI( MP3_PORT, MP3_PIN); // output hi (deselect MP3)
#ifdef VS1000_NEW
buf[0] = SM_SDINEW ;
vs1001::write(SCI_MODE,1, buf);
#endif
// set CLOCKF for 24.576 MHz
// change to doubler //nick 7/7/04
buf[0] = 0x9800;
vs1001::write(SCI_CLOCKF,1,buf);
vs1001::write(SCI_CLOCKF,1,buf);
#ifdef VS1001
// Force clock doubler see pg32 of VS10XX appl.notes
buf[0] = 0x8008;
vs1001::write(SCI_INT_FCTLH,1,buf);
#endif
while( !((DREQ_PORT) & (1<<DREQ_PIN)) ); //wait for DREQ
vs1001::nulls(32);
SPSR = (1<<SPI2X); //set spi to Fosc/2
}
else if (r == HARD_RESET)
{
CBI(RESET_PORT, RESET_PIN); // RESET- lo
delay(1); // 1 mS
SBI(RESET_PORT, RESET_PIN); // RESET- hi
delay(5); // 5 mS
}
}
void devpts_pty_new(int number, kdev_t device)
{
struct super_block *sb = devpts_mnt->mnt_sb;
struct devpts_sb_info *sbi = SBI(sb);
struct inode *inode;
if ( sbi->inodes[number] )
return; /* Already registered, this does happen */
inode = new_inode(sb);
if (!inode)
return;
inode->i_ino = number+2;
inode->i_blocks = 0;
inode->i_blksize = 1024;
inode->i_uid = sbi->setuid ? sbi->uid : current->fsuid;
inode->i_gid = sbi->setgid ? sbi->gid : current->fsgid;
inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME;
init_special_inode(inode, S_IFCHR|sbi->mode, kdev_t_to_nr(device));
if ( sbi->inodes[number] ) {
iput(inode);
return;
}
sbi->inodes[number] = inode;
}
static bool ss_stream_can_push(StreamSlave *obj,
StreamCanPushNotifyFn notify,
void *notify_opaque)
{
SlaveBootInt *s = SBI(obj);
/* FIXME: Check for SMAP mode
* Add AXI Slave interface
* Add JTAG Interface
*/
if (!s->smap_busy) {
smap_data_rdwr(s);
}
if (sbi_can_receive_from_dma(s)) {
/* return false and store the notify opts */
s->notify = notify;
s->notify_opaque = notify_opaque;
return false;
} else {
/* Read to receive */
s->notify = NULL;
s->notify_opaque = NULL;
return true;
}
}
void capifs_new_ncci(char type, unsigned int num, kdev_t device)
{
struct super_block *sb;
struct capifs_sb_info *sbi;
struct capifs_ncci *np;
ino_t ino;
for ( sb = mounts ; sb ; sb = sbi->next ) {
sbi = SBI(sb);
for (ino = 0, np = sbi->nccis ; ino < sbi->max_ncci; ino++, np++) {
if (np->used == 0) {
np->used = 1;
np->type = type;
np->num = num;
np->kdev = device;
break;
}
}
if ((np->inode = iget(sb, ino+2)) != 0) {
struct inode *inode = np->inode;
inode->i_uid = sbi->setuid ? sbi->uid : current->fsuid;
inode->i_gid = sbi->setgid ? sbi->gid : current->fsgid;
inode->i_mode = sbi->mode | S_IFCHR;
inode->i_rdev = np->kdev;
inode->i_nlink++;
}
}
}
static void capifs_read_inode(struct inode *inode)
{
ino_t ino = inode->i_ino;
struct capifs_sb_info *sbi = SBI(inode->i_sb);
inode->i_mode = 0;
inode->i_nlink = 0;
inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME;
inode->i_blocks = 0;
inode->i_blksize = 1024;
inode->i_uid = inode->i_gid = 0;
if ( ino == 1 ) {
inode->i_mode = S_IFDIR | S_IRUGO | S_IXUGO | S_IWUSR;
inode->i_op = &capifs_root_inode_operations;
inode->i_fop = &capifs_root_operations;
inode->i_nlink = 2;
return;
}
ino -= 2;
if ( ino >= sbi->max_ncci )
return; /* Bogus */
init_special_inode(inode, S_IFCHR, 0);
return;
}
void capifs_free_ncci(char type, unsigned int num)
{
struct super_block *sb;
struct capifs_sb_info *sbi;
struct inode *inode;
struct capifs_ncci *np;
ino_t ino;
for ( sb = mounts ; sb ; sb = sbi->next ) {
sbi = SBI(sb);
for (ino = 0, np = sbi->nccis ; ino < sbi->max_ncci; ino++, np++) {
if (!np->used || np->type != type || np->num != num)
continue;
if (np->inode) {
inode = np->inode;
np->inode = 0;
np->used = 0;
inode->i_nlink--;
iput(inode);
break;
}
}
}
}
/**
* M165: Set multiple mix factors for a mixing extruder.
* Omitted factors will be set to 0.
* The mix is normalized and stored in the current virtual tool.
*
* A[factor] Mix factor for extruder stepper 1
* B[factor] Mix factor for extruder stepper 2
* C[factor] Mix factor for extruder stepper 3
* D[factor] Mix factor for extruder stepper 4
* H[factor] Mix factor for extruder stepper 5
* I[factor] Mix factor for extruder stepper 6
*/
void GcodeSuite::M165() {
// Get mixing parameters from the GCode
// The total "must" be 1.0 (but it will be normalized)
// If no mix factors are given, the old mix is preserved
const char mixing_codes[] = { 'A', 'B'
#if MIXING_STEPPERS > 2
, 'C'
#if MIXING_STEPPERS > 3
, 'D'
#if MIXING_STEPPERS > 4
, 'H'
#if MIXING_STEPPERS > 5
, 'I'
#endif // MIXING_STEPPERS > 5
#endif // MIXING_STEPPERS > 4
#endif // MIXING_STEPPERS > 3
#endif // MIXING_STEPPERS > 2
};
uint8_t mix_bits = 0;
MIXER_STEPPER_LOOP(i) {
if (parser.seenval(mixing_codes[i])) {
SBI(mix_bits, i);
mixer.set_collector(i, parser.value_float());
}
}
// If any mixing factors were included, clear the rest
// If none were included, preserve the last mix
if (mix_bits) {
MIXER_STEPPER_LOOP(i)
if (!TEST(mix_bits, i)) mixer.set_collector(i, 0.0f);
mixer.normalize();
}
}
// Returns a 10bit value
unsigned int get_val(void)
{
unsigned int res;
// Start the free running conversion
SBI(ADCSRA, ADSC);
// Wait for conversion to finish (ADIF == interrupt flag == 1)
while ((ADCSRA & (1 << ADIF)) == 0);
//res = ADCH;
//res = res << 8;
//res = res | ADCL;
res = 0L | ADCW;
// Clear the interrupt flag
SBI(ADCSRA, ADIF);
return res;
}
static void ss_sbi_receive(void *opaque, const uint8_t *buf, int size)
{
SlaveBootInt *s = SBI(opaque);
uint32_t free = fifo_num_free(&s->fifo);
while (s->BusWidthDetectCounter < 16) {
/* First 16 bytes are used by harware for input port width
* detection. We dont need to do that, so discard without
* copying them to buffer
*/
s->BusWidthDetectCounter++;
buf++;
size--;
if (!size) {
break;
}
}
DPRINT("%s: Payload of size: %d recv\n", __func__, size);
if (size <= free) {
fifo_push_all(&s->fifo, buf, size);
if (IF_BURST(free)) {
ss_stream_notify(s);
DEP_AF_DP32(s->regs, SBI_IRQ_STATUS, DATA_RDY, 1);
}
if (IF_NON_BURST(free)) {
ss_stream_notify(s);
DEP_AF_DP32(s->regs, SBI_IRQ_STATUS, DATA_RDY, 1);
}
}
ss_update_busy_line(s);
sbi_update_irq(s);
}
void capifs_new_ncci(char type, unsigned int num, kdev_t device)
{
struct super_block *sb;
struct capifs_sb_info *sbi;
struct capifs_ncci *np;
ino_t ino;
for ( sb = mounts ; sb ; sb = sbi->next ) {
sbi = SBI(sb);
for (ino = 0, np = sbi->nccis ; ino < sbi->max_ncci; ino++, np++) {
if (np->used == 0) {
np->used = 1;
np->type = type;
np->num = num;
np->kdev = device;
break;
}
}
if ( ino >= sbi->max_ncci )
continue;
if ((np->inode = capifs_new_inode(sb)) != NULL) {
struct inode *inode = np->inode;
inode->i_uid = sbi->setuid ? sbi->uid : current->fsuid;
inode->i_gid = sbi->setgid ? sbi->gid : current->fsgid;
inode->i_nlink = 1;
inode->i_ino = ino + 2;
init_special_inode(inode, sbi->mode|S_IFCHR, np->kdev);
}
}
}
/*** Chardev Stream handlers */
static int ss_sbi_can_receive(void *opaque)
{
SlaveBootInt *s = SBI(opaque);
uint32_t num = fifo_num_free(&s->fifo);
uint32_t recvb = 0;
if (s->cs || s->rdwr) {
/* Data lines are in tristate when cs is high or
* Master is in Read back mode
* */
return 0;
}
/* Check for Busy Line
* Check on Fifo Space
*/
if (DEP_AF_EX32(s->regs, SBI_CTRL, ENABLE) &&
!DEP_AF_EX32(s->regs, SBI_MODE, SELECT)) {
if (IF_BURST(num)) {
recvb = (1 << DEP_AF_EX32(s->regs, SMAP_CTRL, BURST_SIZE)) *
1024;
} else if (num >= 4) {
recvb = 4;
}
/* if busy line is low */
if (!s->busy_line) {
return recvb;
}
}
return 0;
}
static uint64_t sbi_irq_disable_prew(DepRegisterInfo *reg, uint64_t val64)
{
SlaveBootInt *s = SBI(reg->opaque);
uint32_t val = val64;
s->regs[R_SBI_IRQ_MASK] |= val;
return 0;
}
static uint64_t sbi_irq_trigger_prew(DepRegisterInfo *reg, uint64_t val64)
{
SlaveBootInt *s = SBI(reg->opaque);
uint32_t val = val64;
s->regs[R_SBI_IRQ_STATUS] |= val;
return 0;
}
void _lcd_mixer_cycle_mix() {
uint16_t bits = 0;
MIXER_STEPPER_LOOP(i) if (mixer.collector[i]) SBI(bits, i);
bits = (bits + 1) & (_BV(MIXING_STEPPERS) - 1);
if (!bits) ++bits;
MIXER_STEPPER_LOOP(i) mixer.collector[i] = TEST(bits, i) ? 10.0f : 0.0f;
ui.refresh();
}
// Pass the result of the endstop test
void Endstops::test_dual_z_endstops(EndstopEnum es1, EndstopEnum es2) {
byte z_test = TEST_ENDSTOP(es1) | (TEST_ENDSTOP(es2) << 1); // bit 0 for Z, bit 1 for Z2
if (stepper.current_block->steps[Z_AXIS] > 0) {
stepper.endstop_triggered(Z_AXIS);
SBI(endstop_hit_bits, Z_MIN);
if (!stepper.performing_homing || (z_test == 0x3)) //if not performing home or if both endstops were trigged during homing...
stepper.kill_current_block();
}
}
void MarlinSerial::write(const uint8_t c) {
_written = true;
CRITICAL_SECTION_START;
bool emty = (tx_buffer.head == tx_buffer.tail);
CRITICAL_SECTION_END;
// If the buffer and the data register is empty, just write the byte
// to the data register and be done. This shortcut helps
// significantly improve the effective datarate at high (>
// 500kbit/s) bitrates, where interrupt overhead becomes a slowdown.
if (emty && TEST(M_UCSRxA, M_UDREx)) {
CRITICAL_SECTION_START;
M_UDRx = c;
SBI(M_UCSRxA, M_TXCx);
CRITICAL_SECTION_END;
return;
}
const uint8_t i = (tx_buffer.head + 1) & (TX_BUFFER_SIZE - 1);
// If the output buffer is full, there's nothing for it other than to
// wait for the interrupt handler to empty it a bit
while (i == tx_buffer.tail) {
if (!TEST(SREG, SREG_I)) {
// Interrupts are disabled, so we'll have to poll the data
// register empty flag ourselves. If it is set, pretend an
// interrupt has happened and call the handler to free up
// space for us.
if (TEST(M_UCSRxA, M_UDREx))
_tx_udr_empty_irq();
}
else {
// nop, the interrupt handler will free up space for us
}
}
tx_buffer.buffer[tx_buffer.head] = c;
{ CRITICAL_SECTION_START;
tx_buffer.head = i;
SBI(M_UCSRxB, M_UDRIEx);
CRITICAL_SECTION_END;
}
return;
}
/*
* Revalidate is called on every cache lookup. We use it to check that
* the pty really does still exist. Never revalidate negative dentries;
* for simplicity (fix later?)
*/
static int devpts_revalidate(struct dentry * dentry, int flags)
{
struct devpts_sb_info *sbi;
if ( !dentry->d_inode )
return 0;
sbi = SBI(dentry->d_inode->i_sb);
return ( sbi->inodes[dentry->d_inode->i_ino - 2] == dentry->d_inode );
}
/*
* Revalidate is called on every cache lookup. We use it to check that
* the ncci really does still exist. Never revalidate negative dentries;
* for simplicity (fix later?)
*/
static int capifs_revalidate(struct dentry * dentry, int flags)
{
struct capifs_sb_info *sbi;
if ( !dentry->d_inode )
return 0;
sbi = SBI(dentry->d_inode->i_sb);
return ( sbi->nccis[dentry->d_inode->i_ino - 2].inode == dentry->d_inode );
}
SBI gra_screen::Work()
{
if (Timer_c.GetElapsedTime()-osttime-korektatime>1)
{
korektatime=Timer_c.GetElapsedTime()-osttime;
}
osttime=Timer_c.GetElapsedTime()-korektatime;
if (pozres)
Reseter();
if (dan->wynmax>0&&(wynl>=dan->wynmax||wynp>=dan->wynmax))
return SBI(true,0,Brak,(void *)(new menu_screen::init_form(true)),2);
if (zam)
return SBI(true,0,Brak,(void *)(new menu_screen::init_form(true)),2);
pozres=false;
if (pilka_ob->GetX()<bl)
{
pozres=true;
wynp++;
wynik_obp.SetText(IntToString(wynp));
Gol_screen::init_form * wskaz;
if (wynp>=dan->wynmax)
wskaz=new Gol_screen::init_form(false,"zielony\nwygral!");
else
wskaz=new Gol_screen::init_form(false);
return SBI(false,6,Interakcji,(void *)wskaz);
}
if (pilka_ob->GetX()>bp)
{
pozres=true;
wynl++;
wynik_obl.SetText(IntToString(wynl));
Gol_screen::init_form * wskaz;
if (wynl>=dan->wynmax)
wskaz=new Gol_screen::init_form(true,"niebieski\nwygral!");
else
wskaz=new Gol_screen::init_form(true);
return SBI(false,6,Interakcji,(void *)wskaz);
}
if (Timer_c.GetElapsedTime()-korektatime>=dan->czasmax)
{
if (wynl>wynp)
{
Gol_screen::init_form * wskaz=new Gol_screen::init_form(true,"niebieski\nwygral!",true);
zam=true;
return SBI(false,6,Interakcji,(void *)wskaz);
}
else if (wynl<wynp)
{
Gol_screen::init_form * wskaz=new Gol_screen::init_form(false,"zielony\nwygral!",true);
zam=true;
return SBI(false,6,Interakcji,(void *)wskaz);
}
}
return SBI();
}
/* Constructor */
MAX3421E::MAX3421E( void )
{
// initialize SPI pins
pinMode( SCK_PIN, OUTPUT );
pinMode( MISO_PIN, INPUT );
pinMode( MOSI_PIN, OUTPUT );
pinMode( SS_PIN, OUTPUT );
digitalWrite( SCK_PIN, HIGH );
digitalWrite( MOSI_PIN, HIGH );
digitalWrite( SS_PIN, HIGH );
// initialize pins
pinMode( INT_PIN, INPUT );
pinMode( GPX_PIN, INPUT );
pinMode( RST_PIN, OUTPUT );
setRST( HIGH );
if (SPI_SAUxEN == 0) {
#ifdef WORKAROUND_READ_MODIFY_WRITE
SBI2(SFR2_PER0, SFR2_BIT_SAUxEN); /* supply SAUx clock */
#else
SPI_SAUxEN = 1U; /* supply SAUx clock */
#endif
NOP();
NOP();
NOP();
NOP();
SPI_SPSx = 0x0001U;
}
#ifdef WORKAROUND_READ_MODIFY_WRITE
SPI_STx |= SPI_CHx; /* disable CSIxx */
CBI(SFR_IFxx, SFR_BIT_CSIIFxx); /* clear INTCSIxx interrupt flag */
SBI(SFR_MKxx, SFR_BIT_CSIMKxx); /* disable INTCSIxx interrupt */
CBI(SFR_PR1xx, SFR_BIT_CSIPR1xx); /* set INTCSIxx high priority */
CBI(SFR_PR0xx, SFR_BIT_CSIPR0xx);
#else
SPI_STx |= SPI_CHx; /* disable CSIxx */
SPI_CSIIFxx = 0U; /* clear INTCSIxx interrupt flag */
SPI_CSIMKxx = 1U; /* disable INTCSIxx interrupt */
SPI_CSIPR1xx = 0U; /* set INTCSIxx high priority */
SPI_CSIPR0xx = 0U;
#endif
SPI_SIRxx = 0x0007U; /* clear error flag */
SPI_SMRxx = 0x0020U;
SPI_SCRxx = 0xF007U;
SPI_SDRxx = 0x0200U;
SPI_SOx |= SPI_CHx << 8; /* CSIxx clock initial level */
SPI_SOx &= ~SPI_CHx; /* CSIxx SO initial level */
SPI_SOEx |= SPI_CHx; /* enable CSIxx output */
SPI_SSx |= SPI_CHx; /* enable CSIxx */
}
static void sbi_ctrl_postw(DepRegisterInfo *reg, uint64_t val64)
{
SlaveBootInt *s = SBI(reg->opaque);
uint32_t val = val64;
if (val & R_SBI_CTRL_SOFT_RST_MASK) {
ss_reset(DEVICE(s));
DEP_AF_DP32(s->regs, SBI_CTRL, SOFT_RST, 0);
}
ss_update_busy_line(s);
}
void devpts_pty_kill(int number)
{
struct super_block *sb = devpts_mnt->mnt_sb;
struct devpts_sb_info *sbi = SBI(sb);
struct inode *inode = sbi->inodes[number];
if ( inode ) {
sbi->inodes[number] = NULL;
inode->i_nlink--;
iput(inode);
}
}
static size_t ss_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
uint32_t attr)
{
SlaveBootInt *s = SBI(obj);
uint32_t free = fifo_num_free(&s->fifo);
/* FIXME: Implement Other Interfaces mentioned above */
fifo_push_all(&s->fifo, buf, free);
ss_update_busy_line(s);
sbi_update_irq(s);
return free > len ? len : free;
}
