static void prvSetupHardware( void ) { /* Configuration taken from the ST code. Set Flash banks size & address */ FMI_BankRemapConfig( 4, 2, 0, 0x80000 ); /* FMI Waite States */ FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH ); /* Configure the FPLL = 96MHz, and APB to 48MHz. */ SCU_PCLKDivisorConfig( SCU_PCLK_Div2 ); SCU_PLLFactorsConfig( 192, 25, 2 ); SCU_PLLCmd( ENABLE ); SCU_MCLKSourceConfig( SCU_MCLK_PLL ); WDG_Cmd( DISABLE ); VIC_DeInit(); /* GPIO8 clock source enable, used by the LCD. */ SCU_APBPeriphClockConfig(__GPIO8, ENABLE); GPIO_DeInit(GPIO8); /* GPIO 9 clock source enable, used by the LCD. */ SCU_APBPeriphClockConfig(__GPIO9, ENABLE); GPIO_DeInit(GPIO9); /* Enable VIC clock */ SCU_AHBPeriphClockConfig(__VIC, ENABLE); SCU_AHBPeriphReset(__VIC, DISABLE); /* Peripheral initialisation. */ vParTestInitialise(); }
void systemInit(void) { //Default configuration SCU_MCLKSourceConfig(SCU_MCLK_OSC); //Configure the FMI FMI_Config(FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH); //Configure PLL factors SCU_PLLFactorsConfig(192, 25, 2); //Enable PLL and wait for the the PLL to lock SCU_PLLCmd(ENABLE); //Set clock dividers SCU_RCLKDivisorConfig(SCU_RCLK_Div1); SCU_HCLKDivisorConfig(SCU_HCLK_Div1); SCU_FMICLKDivisorConfig(SCU_FMICLK_Div1); SCU_PCLKDivisorConfig(SCU_PCLK_Div2); //Switch to PLL clock SCU_MCLKSourceConfig(SCU_MCLK_PLL); //Enable VIC clock SCU_AHBPeriphClockConfig(__VIC, ENABLE); //Reset VIC peripheral VIC_DeInit(); //Assign default vectors VIC_InitDefaultVectors(); }
static void platform_config_scu() { volatile u16 i = 0xFFFF; while (i-- > 0); // SCU initialization SCU_MCLKSourceConfig(SCU_MCLK_OSC); SCU_PLLFactorsConfig(192,25,2); /* PLL = 96 MHz */ SCU_PLLCmd(ENABLE); /* PLL Enabled */ SCU_MCLKSourceConfig(SCU_MCLK_PLL); /* MCLK = PLL */ SCU_PFQBCCmd( ENABLE ); /* Set the RCLK Clock divider to max speed*/ SCU_RCLKDivisorConfig(SCU_RCLK_Div1); /* Set the PCLK Clock to MCLK/2 */ SCU_PCLKDivisorConfig(SCU_PCLK_Div2); /* Set the HCLK Clock to MCLK */ SCU_HCLKDivisorConfig(SCU_HCLK_Div1); /* Set the BRCLK Clock to MCLK */ SCU_BRCLKDivisorConfig(SCU_BRCLK_Div1); // Enable VIC clock SCU_AHBPeriphClockConfig(__VIC, ENABLE); SCU_AHBPeriphReset(__VIC, DISABLE); // Enable the UART clocks SCU_APBPeriphClockConfig(__UART_ALL, ENABLE); // Enable the timer clocks SCU_APBPeriphClockConfig(__TIM01, ENABLE); SCU_APBPeriphReset(__TIM01, DISABLE); SCU_APBPeriphClockConfig(__TIM23, ENABLE); SCU_APBPeriphReset(__TIM23, DISABLE); // Enable the GPIO clocks SCU_APBPeriphClockConfig(__GPIO_ALL, ENABLE); // Enable the WIU clock SCU_APBPeriphClockConfig(__WIU, ENABLE); SCU_APBPeriphReset(__WIU, DISABLE); // Enable the I2C clocks SCU_APBPeriphClockConfig(__I2C0, ENABLE); SCU_APBPeriphReset(__I2C0, DISABLE); SCU_APBPeriphClockConfig(__I2C1, ENABLE); SCU_APBPeriphReset(__I2C1, DISABLE); // Enable the ADC clocks SCU_APBPeriphClockConfig(__ADC, ENABLE); // Enable the SSP clocks SCU_APBPeriphClockConfig(__SSP0,ENABLE); SCU_APBPeriphReset(__SSP0,DISABLE); SCU_APBPeriphClockConfig(__SSP1,ENABLE); SCU_APBPeriphReset(__SSP1,DISABLE); }
/* Private functions ---------------------------------------------------------*/ void System_Setup(void) { SCU_MCLKSourceConfig(SCU_MCLK_OSC); SCU_PCLKDivisorConfig(SCU_PCLK_Div2); SCU_PLLFactorsConfig(128,25,4); SCU_PLLCmd(ENABLE); SCU_MCLKSourceConfig(SCU_MCLK_PLL); SCU_APBPeriphClockConfig(__CAN, ENABLE); SCU_APBPeriphClockConfig(__GPIO0, ENABLE); SCU_APBPeriphClockConfig(__GPIO1, ENABLE); SCU_APBPeriphClockConfig(__GPIO3, ENABLE); SCU_APBPeriphClockConfig(__GPIO5, ENABLE); SCU_AHBPeriphClockConfig(__VIC, ENABLE); SCU_APBPeriphReset(__CAN, DISABLE); SCU_APBPeriphReset(__GPIO0, DISABLE); SCU_APBPeriphReset(__GPIO1, DISABLE); SCU_APBPeriphReset(__GPIO3, DISABLE); SCU_APBPeriphReset(__GPIO5, DISABLE); SCU_AHBPeriphReset(__VIC, DISABLE); }