void
idt_init(void) {
extern uintptr_t __vectors[];
int i;
for (i = 0; i < sizeof(idt) / sizeof(struct gatedesc); i ++) {
SETGATE(idt[i], 1, GD_KTEXT, __vectors[i], DPL_KERNEL);
}
SETGATE(idt[T_SYSCALL], 1, GD_KTEXT, __vectors[T_SYSCALL], DPL_USER);
SETGATE(idt[T_BRKPT], 0, GD_KTEXT, __vectors[T_BRKPT], DPL_USER);
lidt(&idt_pd);
}
void
tvinit(void)
{
int i;
for(i = 0; i < 256; i++)
SETGATE(idt[i], 0, SEG_KCODE<<3, vectors[i], 0);
SETGATE(idt[T_SYSCALL], 1, SEG_KCODE<<3, vectors[T_SYSCALL], DPL_USER);
initlock(&tickslock, "time");
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
// void th0();
// void th1();
// void th3();
// void th4();
// void th5();
// void th6();
// void th7();
// void th8();
// void th9();
// void th10();
// void th11();
// void th12();
// void th13();
// void th14();
// void th16();
// SETGATE(idt[0], 0, GD_KT, th0, 0);
// SETGATE(idt[1], 0, GD_KT, th1, 0);
// SETGATE(idt[3], 0, GD_KT, th3, 0);
// SETGATE(idt[4], 0, GD_KT, th4, 0);
// SETGATE(idt[5], 0, GD_KT, th5, 0);
// SETGATE(idt[6], 0, GD_KT, th6, 0);
// SETGATE(idt[7], 0, GD_KT, th7, 0);
// SETGATE(idt[8], 0, GD_KT, th8, 0);
// SETGATE(idt[9], 0, GD_KT, th9, 0);
// SETGATE(idt[10], 0, GD_KT, th10, 0);
// SETGATE(idt[11], 0, GD_KT, th11, 0);
// SETGATE(idt[12], 0, GD_KT, th12, 0);
// SETGATE(idt[13], 0, GD_KT, th13, 0);
// SETGATE(idt[14], 0, GD_KT, th14, 0);
// SETGATE(idt[16], 0, GD_KT, th16, 0);
// Challenge:
extern void (*funs[])();
cprintf("funs %x\n", funs);
cprintf("funs[0] %x\n", funs[0]);
cprintf("funs[48] %x\n", funs[48]);
int i;
for (i = 0; i <= 16; ++i)
if (i==T_BRKPT)
SETGATE(idt[i], 0, GD_KT, funs[i], 3)
else if (i!=2 && i!=15) {
SETGATE(idt[i], 0, GD_KT, funs[i], 0);
}
SETGATE(idt[48], 0, GD_KT, funs[48], 3);
// Per-CPU setup
trap_init_percpu();
}
/* idt_init - initialize IDT to each of the entry points in kern/trap/vectors.S */
void
idt_init(void) {
extern uintptr_t __vectors[];
int i;
for (i = 0; i < sizeof(idt) / sizeof(struct gatedesc); i ++) {
SETGATE(idt[i], 0, GD_KTEXT, __vectors[i], DPL_KERNEL);
}
// set for switch from user to kernel
SETGATE(idt[T_SWITCH_TOK], 0, GD_KTEXT, __vectors[T_SWITCH_TOK], DPL_USER);
// load the IDT
lidt(&idt_pd);
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 2: Your code here.
//extern char* t_brkpt_lbl;
extern char t_brkpt_lbl[];
SETGATE(idt[3], 0, GD_KT, t_brkpt_lbl, 3);
// Hint: Must this gate be accessible from userlevel?
// LAB 3: Your code here.
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
int i;
for (i = 0; i < 51; ++i) {
SETGATE(idt[i], 0, GD_KT, traps[i], 0);
}
SETGATE(idt[T_BRKPT], 0, GD_KT, traps[T_BRKPT], 3);
SETGATE(idt[T_SYSCALL], 0, GD_KT, traps[T_SYSCALL], 3);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
// vectors[] is defined in kern/trapentry.S
// see the comments there for important information about its data layout
extern unsigned int vectors[];
extern void T_DEFAULT_HANDLER(), T_SYSCALL_HANDLER(), T_BRKPT_HANDLER(); // trap handlers defined in kern/trapentry.S that we must make special references to
int i;
unsigned int *vector = vectors;
// iterate through all possible 256 vectors, defining an IDT entry for each one
// at each step, vector points to the next defined trap number that has yet to be set in the IDT
// here we rely on the fact that, in kern/trapentry.S, TRAPHANDLER was called with increasing trap numbers
for(i = 0; i < 256; i++) {
if (*vector == i) {
/*
* in this case, vector points to the trap number we must now set in the IDT,
* and vector+1 points to the address of the trap handler for this trap
*/
if (i >= IRQ_OFFSET && i < IRQ_OFFSET + 16) {
// processor never checks DPL of the IDT entry when invoking a hardware interrupt handler
SETGATE(idt[i], 0, GD_KT, *(vector+1), 3);
}
else {
SETGATE(idt[i], 0, GD_KT, *(vector+1), 0);
}
vector += 2; // make vector point to the next trap
}
else {
/*
* in this case, there is no defined trap for this vector
* set the IDT entry to point to the default trap handler
*/
SETGATE(idt[i], 0, GD_KT, &T_DEFAULT_HANDLER, 0);
}
}
// these are special, since they are traps we allow the user to call
SETGATE(idt[T_SYSCALL], 0, GD_KT, &T_SYSCALL_HANDLER, 3);
SETGATE(idt[T_BRKPT], 0, GD_KT, &T_BRKPT_HANDLER, 3);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
int i=0;
for (; i< MAX_IDT ; i++){
SETGATE(idt[i], 0, GD_KT, trap_handler[i], 0);
}
// init break point
SETGATE(idt[T_BRKPT], 0, GD_KT, trap_handler[T_BRKPT], 3);
// init syscall
SETGATE(idt[T_SYSCALL], 0, GD_KT, trap_handler[T_SYSCALL], 3);
// Per-CPU setup
trap_init_percpu();
}
/* idt_init - initialize IDT to each of the entry points in kern/trap/vectors.S */
void
idt_init(void) {
extern uintptr_t __vectors[];
int i;
for (i = 0; i < sizeof(idt) / sizeof(struct gatedesc); i ++) {
SETGATE(idt[i], 0, GD_KTEXT, __vectors[i], DPL_KERNEL);
}
// load the IDT
lidt(&idt_pd);
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE],0,GD_KT,DIV_HANDLER,3);
SETGATE(idt[T_BRKPT],0,GD_KT,BRKPT_HANDLER,3);
SETGATE(idt[T_GPFLT],0,GD_KT,GPFLT_HANDLER,3);
SETGATE(idt[T_SYSCALL],0,GD_KT,SYSCALL_HANDLER,3);
SETGATE(idt[T_PGFLT],0,GD_KT,PGFLT_HANDLER,3);
SETGATE(idt[IRQ_OFFSET+IRQ_TIMER],0,GD_KT,IRQ_TIMER_HANDLER,3);
SETGATE(idt[IRQ_OFFSET+IRQ_KBD],0,GD_KT,IRQ_KBD_HANDLER,3);
SETGATE(idt[IRQ_OFFSET+IRQ_SERIAL],0,GD_KT,IRQ_SERIAL_HANDLER,3);
SETGATE(idt[IRQ_OFFSET+IRQ_SPURIOUS],0,GD_KT,IRQ_SPURIOUS_HANDLER,3);
SETGATE(idt[IRQ_OFFSET+IRQ_IDE],0,GD_KT,IRQ_IDE_HANDLER,3);
// Per-CPU setup
trap_init_percpu();
}
/* idt_init - initialize IDT to each of the entry points in kern/trap/vectors.S */
void
idt_init(void) {
/* LAB1 YOUR CODE : STEP 2 */
/* (1) Where are the entry addrs of each Interrupt Service Routine (ISR)?
* All ISR's entry addrs are stored in __vectors. where is uintptr_t __vectors[] ?
* __vectors[] is in kern/trap/vector.S which is produced by tools/vector.c
* (try "make" command in lab1, then you will find vector.S in kern/trap DIR)
* You can use "extern uintptr_t __vectors[];" to define this extern variable which will be used later.
* (2) Now you should setup the entries of ISR in Interrupt Description Table (IDT).
* Can you see idt[256] in this file? Yes, it's IDT! you can use SETGATE macro to setup each item of IDT
* (3) After setup the contents of IDT, you will let CPU know where is the IDT by using 'lidt' instruction.
* You don't know the meaning of this instruction? just google it! and check the libs/x86.h to know more.
* Notice: the argument of lidt is idt_pd. try to find it!
*/
int i = 0;
for(i = 0; i < 256; i++) {
SETGATE(idt[i], 0, GD_KTEXT, __vectors[i], DPL_KERNEL);
}
SETGATE(idt[T_SYSCALL], 1, GD_KTEXT, __vectors[T_SYSCALL], DPL_USER);
lidt(&idt_pd);
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
int i = 0;
for ( ; i < 52; i++) {
SETGATE(idt[i], 0, GD_KT, thandlers[i], 0);
}
// Change DPL for break point
SETGATE(idt[T_BRKPT], 0, GD_KT, thandlers[T_BRKPT], 3);
// Change DPL for syscall
SETGATE(idt[T_SYSCALL], 0, GD_KT, thandlers[T_SYSCALL], 3);
// Per-CPU setup
trap_init_percpu();
}
/**
* this function initializes the interrupt descript table
*
*/
void rt_hw_idt_init(void)
{
extern void Xdefault;
int i, j, func;
for(i=0; i<MAX_HANDLERS; i++)
{
isr_table[i] = rt_hw_interrupt_handle;
}
// install a default handler
for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++)
SETGATE(idt[i], 0, GD_KT, &Xdefault, 0);
/*install trap handler*/
for(i = 0; i < 16; i++)
{
func = (int)trap_func[i];
SETGATE(idt[i], 0, GD_KT, func, 0);
}
func = (int)trap_func[3];
SETGATE(idt[3], 0, GD_KT, func, 3);
i = 0;
/*install exteral interrupt handler*/
for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++)
{
func = (int)hdinterrupt_func[i];
SETGATE(idt[j], 0, GD_KT, func, 0);
i++;
}
// Load the IDT
asm volatile("lidt idt_pd + 2");
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
//---------------------------------------- Lab3 ------------------------------------------------------------
//------------------------------------Lab3-Challenge----------------------------------------------------------
extern uint32_t vec[];
void tid48();
int i;
for (i = 0; i != 20; i++) {
if (i == 3){
SETGATE(idt[i], 0, GD_KT, vec[i], 3);
}
else
SETGATE(idt[i], 0, GD_KT, vec[i], 0);
}
//------------------------------------Lab3-Challenge----------------------------------------------------------
SETGATE(idt[48], 0, GD_KT, tid48, 3);
//---------------------------------------- Lab3 ------------------------------------------------------------
//------------ Lab4 ----------------------------------------------------------------------------------------
extern void tid32();
extern void tid33();
extern void tid36();
extern void tid39();
extern void tid46();
extern void tid51();
SETGATE(idt[32], 0, GD_KT, tid32, 0);
SETGATE(idt[33], 0, GD_KT, tid33, 0);
SETGATE(idt[36], 0, GD_KT, tid36, 0);
SETGATE(idt[39], 0, GD_KT, tid39, 0);
SETGATE(idt[46], 0, GD_KT, tid46, 0);
SETGATE(idt[51], 0, GD_KT, tid51, 0);
//------------ Lab4 ----------------------------------------------------------------------------------------
// Per-CPU setup
trap_init_percpu();
}
/* idt_init - initialize IDT to each of the entry points in kern/trap/vectors.S */
void
idt_init(void) {
/* LAB1 2013011303 : STEP 2 */
/* (1) Where are the entry addrs of each Interrupt Service Routine (ISR)?
* All ISR's entry addrs are stored in __vectors. where is uintptr_t __vectors[] ?
* __vectors[] is in kern/trap/vector.S which is produced by tools/vector.c
* (try "make" command in lab1, then you will find vector.S in kern/trap DIR)
* You can use "extern uintptr_t __vectors[];" to define this extern variable which will be used later.
* (2) Now you should setup the entries of ISR in Interrupt Description Table (IDT).
* Can you see idt[256] in this file? Yes, it's IDT! you can use SETGATE macro to setup each item of IDT
* (3) After setup the contents of IDT, you will let CPU know where is the IDT by using 'lidt' instruction.
* You don't know the meaning of this instruction? just google it! and check the libs/x86.h to know more.
* Notice: the argument of lidt is idt_pd. try to find it!
*/
extern uintptr_t __vectors[];
int i;
for (i = 0; i < 256; i++)
SETGATE(idt[i], 0, GD_KTEXT, __vectors[i], i == T_SYSCALL ? DPL_USER : DPL_KERNEL);
lidt(&idt_pd);
/* LAB5 2013011303*/
//you should update your lab1 code (just add ONE or TWO lines of code), let user app to use syscall to get the service of ucore
//so you should setup the syscall interrupt gate in here
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE], 0, GD_KT, t_divide, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, t_debug, 0);
SETGATE(idt[T_NMI], 0, GD_KT, t_nmi, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, t_brkpt, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, t_oflow, 0);
SETGATE(idt[T_BOUND], 0, GD_KT, t_bound, 0);
SETGATE(idt[T_ILLOP], 0, GD_KT, t_illop, 0);
SETGATE(idt[T_DEVICE], 0, GD_KT, t_device, 0);
SETGATE(idt[T_DBLFLT], 0, GD_KT, t_dblflt, 0);
SETGATE(idt[T_TSS], 0, GD_KT, t_tss, 0);
SETGATE(idt[T_SEGNP], 0, GD_KT, t_segnp, 0);
SETGATE(idt[T_STACK], 0, GD_KT, t_stack, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, t_gpflt, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, t_pgflt, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, t_fperr, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, t_align, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, t_mchk, 0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, t_simderr, 0);
SETGATE(idt[T_SYSCALL], 0, GD_KT, t_syscall, 3);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
/* extern void trap_handler0();
extern void trap_handler1();
extern void trap_handler2();
extern void trap_handler3();
extern void trap_handler4();
extern void trap_handler6();
extern void trap_handler7();
extern void trap_handler8();
extern void trap_handler9();
extern void trap_handler10();
extern void trap_handler11();
extern void trap_handler12();
extern void trap_handler13();
extern void trap_handler14();
extern void trap_handler16();
extern void trap_handler17();
extern void trap_handler18();
extern void trap_handler19();*/
// LAB 3: Your code here.
/*
SETGATE(idt[0], 0, GD_KT, trap_handler0, 0);
SETGATE(idt[1], 0, GD_KT, trap_handler1, 0);
SETGATE(idt[2], 0, GD_KT, trap_handler2, 0);
SETGATE(idt[3], 0, GD_KT, trap_handler3, 0);
SETGATE(idt[4], 0, GD_KT, trap_handler4, 0);
SETGATE(idt[6], 0, GD_KT, trap_handler6, 0);
SETGATE(idt[7], 0, GD_KT, trap_handler7, 0);
SETGATE(idt[8], 0, GD_KT, trap_handler8, 0);
SETGATE(idt[10], 0, GD_KT, trap_handler10, 0);
SETGATE(idt[11], 0, GD_KT, trap_handler11, 0);
SETGATE(idt[12], 0, GD_KT, trap_handler12, 0);
SETGATE(idt[13], 0, GD_KT, trap_handler13, 0);
SETGATE(idt[14], 0, GD_KT, trap_handler14, 0);
SETGATE(idt[16], 0, GD_KT, trap_handler16, 0);
SETGATE(idt[17], 0, GD_KT, trap_handler17, 0);
SETGATE(idt[18], 0, GD_KT, trap_handler18, 0);
SETGATE(idt[19], 0, GD_KT, trap_handler19, 0);
*/
extern uint32_t vectors[];
extern void trap_handler48();
extern void irq_handler32();
extern void irq_handler33();
extern void irq_handler36();
extern void irq_handler39();
extern void irq_handler46();
extern void irq_handler51();
int i;
for (i = 0; i < 20; i++) {
if (i == T_BRKPT) {
SETGATE(idt[i], 0, GD_KT, vectors[i], 3);
} else {
SETGATE(idt[i], 0, GD_KT, vectors[i], 0);
}
}
SETGATE(idt[48], 0, GD_KT, trap_handler48, 3);
SETGATE(idt[IRQ_OFFSET + IRQ_TIMER], 0, GD_KT, irq_handler32, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_KBD], 0, GD_KT, irq_handler33, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_SERIAL], 0, GD_KT, irq_handler36, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_SPURIOUS], 0, GD_KT, irq_handler39, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_IDE], 0, GD_KT, irq_handler46, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_ERROR], 0, GD_KT, irq_handler51, 0);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE], 0, GD_KT, _divide_error, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, _debug, 0);
SETGATE(idt[T_NMI], 0, GD_KT, _non_maskable_interrupt, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, _breakpoint, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, _overflow, 0);
SETGATE(idt[T_BOUND], 0, GD_KT, _bound_range_exceeded, 0);
SETGATE(idt[T_ILLOP], 0, GD_KT, _invalid_opcode, 0);
SETGATE(idt[T_DEVICE], 0, GD_KT, _device_not_available, 0);
SETGATE(idt[T_DBLFLT], 0, GD_KT, _double_fault, 0);
SETGATE(idt[T_TSS], 0, GD_KT, _invalid_tss, 0);
SETGATE(idt[T_SEGNP], 0, GD_KT, _segment_not_present, 0);
SETGATE(idt[T_STACK], 0, GD_KT, _stack_fault, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, _general_protection, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, _page_fault, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, _x87_fpu_error, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, _alignment_check, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, _machine_check, 0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, _simd_fp_exception, 0);
SETGATE(idt[T_SYSCALL], 0, GD_KT, syscall, 3);
SETGATE(idt[IRQ_OFFSET + 0], 0, GD_KT, _irq0, 0);
SETGATE(idt[IRQ_OFFSET + 1], 0, GD_KT, _irq1, 0);
SETGATE(idt[IRQ_OFFSET + 2], 0, GD_KT, _irq2, 0);
SETGATE(idt[IRQ_OFFSET + 3], 0, GD_KT, _irq3, 0);
SETGATE(idt[IRQ_OFFSET + 4], 0, GD_KT, _irq4, 0);
SETGATE(idt[IRQ_OFFSET + 5], 0, GD_KT, _irq5, 0);
SETGATE(idt[IRQ_OFFSET + 6], 0, GD_KT, _irq6, 0);
SETGATE(idt[IRQ_OFFSET + 7], 0, GD_KT, _irq7, 0);
SETGATE(idt[IRQ_OFFSET + 8], 0, GD_KT, _irq8, 0);
SETGATE(idt[IRQ_OFFSET + 9], 0, GD_KT, _irq9, 0);
SETGATE(idt[IRQ_OFFSET + 10], 0, GD_KT, _irq10, 0);
SETGATE(idt[IRQ_OFFSET + 11], 0, GD_KT, _irq11, 0);
SETGATE(idt[IRQ_OFFSET + 12], 0, GD_KT, _irq12, 0);
SETGATE(idt[IRQ_OFFSET + 13], 0, GD_KT, _irq13, 0);
SETGATE(idt[IRQ_OFFSET + 14], 0, GD_KT, _irq14, 0);
SETGATE(idt[IRQ_OFFSET + 15], 0, GD_KT, _irq15, 0);
extern void sysenter_handler();
wrmsr(0x174, GD_KT, 0);
wrmsr(0x175, KSTACKTOP, 0);
wrmsr(0x176, sysenter_handler, 0);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE], 0, GD_KT, t_divide, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, t_debug, 0);
SETGATE(idt[T_NMI], 0, GD_KT, t_nmi, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, t_brkpt, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, t_oflow, 0);
SETGATE(idt[T_BOUND], 0, GD_KT, t_bound, 0);
SETGATE(idt[T_ILLOP], 0, GD_KT, t_illop, 0);
SETGATE(idt[T_DEVICE], 0, GD_KT, t_device, 0);
SETGATE(idt[T_DBLFLT], 0, GD_KT, t_dblflt, 0);
SETGATE(idt[T_TSS], 0, GD_KT, t_tss, 0);
SETGATE(idt[T_SEGNP], 0, GD_KT, t_segnp, 0);
SETGATE(idt[T_STACK], 0, GD_KT, t_stack, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, t_gpflt, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, t_pgflt, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, t_fperr, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, t_align, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, t_mchk, 0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, t_simderr, 0);
SETGATE(idt[T_SYSCALL], 0, GD_KT, t_syscall, 3);
SETGATE(idt[IRQ_OFFSET + IRQ_TIMER], 0, GD_KT, irq_timer, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_KBD], 0, GD_KT, irq_kbd, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_SERIAL], 0, GD_KT, irq_serial, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_SPURIOUS], 0, GD_KT, irq_spurious, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_IDE], 0, GD_KT, irq_ide, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_ERROR], 0, GD_KT, irq_error, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_E1000], 0, GD_KT, irq_e1000, 0);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
void th0();
void th1();
void th3();
void th4();
void th5();
void th6();
void th7();
void th8();
void th9();
void th10();
void th11();
void th12();
void th13();
void th14();
void th16();
void th48();
void th32();
void th33();
void th34();
void th35();
void th36();
void th37();
void th38();
void th39();
void th40();
void th41();
void th42();
void th43();
void th44();
void th45();
void th46();
void th47();
SETGATE(idt[0], 0, GD_KT, th0, 0);
SETGATE(idt[1], 0, GD_KT, th1, 0);
//modify 0 to 3 to pass breakpoint test.
SETGATE(idt[3], 0, GD_KT, th3, 0);
SETGATE(idt[3], 0, GD_KT, th3, 3);
SETGATE(idt[4], 0, GD_KT, th4, 0);
SETGATE(idt[5], 0, GD_KT, th5, 0);
SETGATE(idt[6], 0, GD_KT, th6, 0);
SETGATE(idt[7], 0, GD_KT, th7, 0);
SETGATE(idt[8], 0, GD_KT, th8, 0);
SETGATE(idt[9], 0, GD_KT, th9, 0);
SETGATE(idt[10], 0, GD_KT, th10, 0);
SETGATE(idt[11], 0, GD_KT, th11, 0);
SETGATE(idt[12], 0, GD_KT, th12, 0);
SETGATE(idt[13], 0, GD_KT, th13, 0);
SETGATE(idt[14], 0, GD_KT, th14, 0);
SETGATE(idt[16], 0, GD_KT, th16, 0);
SETGATE(idt[48], 0, GD_KT, th48, 0);
SETGATE(idt[48], 0, GD_KT, th48, 3);
SETGATE(idt[32], 0, GD_KT, th32, 0);
SETGATE(idt[33], 0, GD_KT, th33, 0);
SETGATE(idt[34], 0, GD_KT, th34, 0);
SETGATE(idt[35], 0, GD_KT, th35, 0);
SETGATE(idt[36], 0, GD_KT, th36, 0);
SETGATE(idt[37], 0, GD_KT, th37, 0);
SETGATE(idt[38], 0, GD_KT, th38, 0);
SETGATE(idt[39], 0, GD_KT, th39, 0);
SETGATE(idt[40], 0, GD_KT, th40, 0);
SETGATE(idt[41], 0, GD_KT, th41, 0);
SETGATE(idt[42], 0, GD_KT, th42, 0);
SETGATE(idt[43], 0, GD_KT, th43, 0);
SETGATE(idt[44], 0, GD_KT, th44, 0);
SETGATE(idt[45], 0, GD_KT, th45, 0);
SETGATE(idt[46], 0, GD_KT, th46, 0);
SETGATE(idt[47], 0, GD_KT, th47, 0);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// Ashish
SETGATE(idt[T_DIVIDE], 0, GD_KT, divide_error_handler, 3);
SETGATE(idt[T_DEBUG], 0, GD_KT, debug_exception_handler, 3);
SETGATE(idt[T_NMI], 0, GD_KT, non_maskable_interrupt_handler, 3);
SETGATE(idt[T_BRKPT], 0, GD_KT, breakpoint_handler, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, overflow_handler, 3);
SETGATE(idt[T_BOUND], 0, GD_KT, bounds_check_handler, 3);
SETGATE(idt[T_ILLOP], 0, GD_KT, illegal_opcode_handler, 3);
SETGATE(idt[T_DEVICE], 0, GD_KT, device_no_available_handler, 3);
SETGATE(idt[T_DBLFLT], 0, GD_KT, double_fault_handler, 3);
SETGATE(idt[T_TSS], 0, GD_KT, invalid_tss_handler, 3);
SETGATE(idt[T_SEGNP], 0, GD_KT, segment_not_present_handler, 3);
SETGATE(idt[T_STACK], 0, GD_KT, stack_exception_handler, 3);
SETGATE(idt[T_GPFLT], 0, GD_KT, general_protection_fault_handler, 3);
SETGATE(idt[T_PGFLT], 0, GD_KT, page_fault_handler_1, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, floating_point_error_handler, 3);
SETGATE(idt[T_ALIGN], 0, GD_KT, allign_check_handler, 3);
SETGATE(idt[T_MCHK], 0, GD_KT, machine_check_handler, 3);
SETGATE(idt[T_SIMDERR], 0, GD_KT, SIMD_floating_point_error_handler, 3);
SETGATE(idt[T_SYSCALL], 0, GD_KT, system_call_handler, 3); //Diable interrupts if an env is in middle of a syscall.
SETGATE(idt[IRQ_TIMER+IRQ_OFFSET], 0, GD_KT, irq_timer_handler, 0);
SETGATE(idt[IRQ_KBD+IRQ_OFFSET], 0, GD_KT, irq_kbd_handler, 0);
SETGATE(idt[IRQ_SERIAL+IRQ_OFFSET], 0, GD_KT, irq_serial_handler, 0);
SETGATE(idt[IRQ_SPURIOUS+IRQ_OFFSET], 0, GD_KT, irq_spurious_handler, 0);
SETGATE(idt[IRQ_IDE+IRQ_OFFSET], 0, GD_KT, irq_ide_handler, 0);
idt_pd.pd_lim = sizeof(idt)-1;
idt_pd.pd_base = (uint64_t)idt;
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
// Handlers defined in trapentry.S
extern void handler_divide();
extern void handler_debug();
extern void handler_nmi();
extern void handler_brkpt();
extern void handler_oflow();
extern void handler_bound();
extern void handler_illop();
extern void handler_device();
extern void handler_dblflt();
//extern void handler_coproc();
extern void handler_tss();
extern void handler_segnp();
extern void handler_stack();
extern void handler_gpflt();
extern void handler_pgflt();
//extern void handler_res();
extern void handler_fperr();
extern void handler_align();
extern void handler_mchk();
extern void handler_simderr();
extern void handler_syscall();
extern void handler_irq0();
extern void handler_irq1();
extern void handler_irq2();
extern void handler_irq3();
extern void handler_irq4();
extern void handler_irq5();
extern void handler_irq6();
extern void handler_irq7();
extern void handler_irq8();
extern void handler_irq9();
extern void handler_irq10();
extern void handler_irq11();
extern void handler_irq12();
extern void handler_irq13();
extern void handler_irq14();
extern void handler_irq15();
// Initialize entries in idt
SETGATE(idt[T_DIVIDE], 0, GD_KT, handler_divide, DPL_KERN);
SETGATE(idt[T_DEBUG], 0, GD_KT, handler_debug, DPL_KERN); // Don't allow interrupts while in debug mode
SETGATE(idt[T_NMI], 0, GD_KT, handler_nmi, DPL_KERN);
SETGATE(idt[T_BRKPT], 0, GD_KT, handler_brkpt, DPL_USER);
SETGATE(idt[T_OFLOW], 0, GD_KT, handler_oflow, DPL_KERN);
SETGATE(idt[T_BOUND], 0, GD_KT, handler_bound, DPL_KERN);
SETGATE(idt[T_ILLOP], 0, GD_KT, handler_illop, DPL_KERN);
SETGATE(idt[T_DEVICE], 0, GD_KT, handler_device, DPL_KERN);
SETGATE(idt[T_DBLFLT], 0, GD_KT, handler_dblflt, DPL_KERN);
//SETGATE(idt[T_COPROC], 0, GD_KT, handler_coproc, 0);
SETGATE(idt[T_TSS], 0, GD_KT, handler_tss, DPL_KERN);
SETGATE(idt[T_SEGNP], 0, GD_KT, handler_segnp, DPL_KERN);
SETGATE(idt[T_STACK], 0, GD_KT, handler_stack, DPL_KERN);
SETGATE(idt[T_GPFLT], 0, GD_KT, handler_gpflt, DPL_KERN);
SETGATE(idt[T_PGFLT], 0, GD_KT, handler_pgflt, DPL_KERN);
//SETGATE(idt[T_RES], 0, GD_KT, handler_res, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, handler_fperr, DPL_KERN);
SETGATE(idt[T_ALIGN], 0, GD_KT, handler_align, DPL_KERN);
SETGATE(idt[T_MCHK], 0, GD_KT, handler_mchk, DPL_KERN);
SETGATE(idt[T_SIMDERR], 0, GD_KT, handler_simderr, DPL_KERN);
//Initial system call entry
SETGATE(idt[T_SYSCALL], 0, GD_KT, handler_syscall, DPL_USER);
// Initialize IRQ entries
SETGATE(idt[IRQ_OFFSET], 0, GD_KT, handler_irq0, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 1], 0, GD_KT, handler_irq1, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 2], 0, GD_KT, handler_irq2, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 3], 0, GD_KT, handler_irq3, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 4], 0, GD_KT, handler_irq4, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 5], 0, GD_KT, handler_irq5, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 6], 0, GD_KT, handler_irq6, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 7], 0, GD_KT, handler_irq7, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 8], 0, GD_KT, handler_irq8, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 9], 0, GD_KT, handler_irq9, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 10], 0, GD_KT, handler_irq10, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 11], 0, GD_KT, handler_irq11, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 12], 0, GD_KT, handler_irq12, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 13], 0, GD_KT, handler_irq13, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 14], 0, GD_KT, handler_irq14, DPL_KERN);
SETGATE(idt[IRQ_OFFSET + 15], 0, GD_KT, handler_irq15, DPL_KERN);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE], 0, GD_KT, xt_divide, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, xt_debug,0);
SETGATE(idt[T_DBLFLT], 0, GD_KT, xt_dblflt,0);
SETGATE(idt[T_SYSCALL], 0, GD_KT, xt_syscall, 3);
SETGATE(idt[T_NMI], 0, GD_KT, xt_nmi,0);
SETGATE(idt[T_BRKPT], 0, GD_KT, xt_brkpt,3);
SETGATE(idt[T_OFLOW], 0, GD_KT, xt_oflow,0);
SETGATE(idt[T_BOUND], 0, GD_KT, xt_bound,0);
SETGATE(idt[T_ILLOP], 0, GD_KT, xt_illop,0);
SETGATE(idt[T_DEVICE], 0, GD_KT, xt_device,0);
SETGATE(idt[T_TSS], 0, GD_KT, xt_tss,0);
SETGATE(idt[T_SEGNP], 0, GD_KT, xt_segnp,0);
SETGATE(idt[T_STACK], 0, GD_KT, xt_stack,0);
SETGATE(idt[T_GPFLT], 0, GD_KT, xt_gpflt,0);
SETGATE(idt[T_PGFLT], 0, GD_KT, xt_pgflt,0);
SETGATE(idt[T_FPERR], 0, GD_KT, xt_fperr,0);
SETGATE(idt[T_ALIGN], 0, GD_KT, xt_align,0);
SETGATE(idt[T_MCHK], 0, GD_KT, xt_mchk,0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, xt_simderr,0);
SETGATE(idt[32], 0, GD_KT, xi_timer_0,0);
SETGATE(idt[33], 0, GD_KT, xi_timer_1,0)
SETGATE(idt[34], 0, GD_KT, xi_timer_2,0)
SETGATE(idt[35], 0, GD_KT, xi_timer_3,0)
SETGATE(idt[36], 0, GD_KT, xi_timer_4,0)
SETGATE(idt[37], 0, GD_KT, xi_timer_5,0)
SETGATE(idt[38], 0, GD_KT, xi_timer_6,0)
SETGATE(idt[39], 0, GD_KT, xi_timer_7,0)
SETGATE(idt[40], 0, GD_KT, xi_timer_8,0)
SETGATE(idt[41], 0, GD_KT, xi_timer_9,0)
SETGATE(idt[42], 0, GD_KT, xi_timer_10,0)
SETGATE(idt[43], 0, GD_KT, xi_timer_11,0)
SETGATE(idt[44], 0, GD_KT, xi_timer_12,0)
SETGATE(idt[45], 0, GD_KT, xi_timer_13,0)
SETGATE(idt[46], 0, GD_KT, xi_timer_14,0)
SETGATE(idt[47], 0, GD_KT, xi_timer_15,0)
idt_pd.pd_lim = sizeof(idt)-1;
idt_pd.pd_base = (uint64_t)idt;
// Per-CPU setup
trap_init_percpu();
// cprintf("success trap_init");
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
SETGATE(idt[0],0,GD_KT,trapfun0,0);
SETGATE(idt[1],0,GD_KT,trapfun1,0);
SETGATE(idt[2],0,GD_KT,trapfun2,0);
SETGATE(idt[3],0,GD_KT,trapfun3,3);
SETGATE(idt[4],0,GD_KT,trapfun4,0);
SETGATE(idt[5],0,GD_KT,trapfun5,0);
SETGATE(idt[6],0,GD_KT,trapfun6,0);
SETGATE(idt[7],0,GD_KT,trapfun7,0);
SETGATE(idt[8],0,GD_KT,trapfun8,0);
SETGATE(idt[10],0,GD_KT,trapfun10,0);
SETGATE(idt[11],0,GD_KT,trapfun11,0);
SETGATE(idt[12],0,GD_KT,trapfun12,0);
SETGATE(idt[13],0,GD_KT,trapfun13,0);
SETGATE(idt[14],0,GD_KT,trapfun14,0);
SETGATE(idt[16],0,GD_KT,trapfun16,0);
SETGATE(idt[17],0,GD_KT,trapfun17,0);
SETGATE(idt[18],0,GD_KT,trapfun18,0);
SETGATE(idt[19],0,GD_KT,trapfun19,0);
SETGATE(idt[48],0,GD_KT,trapfun48,3);
SETGATE(idt[IRQ_OFFSET+0],0,GD_KT,irq0,0);
SETGATE(idt[IRQ_OFFSET+1],0,GD_KT,irq1,0);
SETGATE(idt[IRQ_OFFSET+2],0,GD_KT,irq2,0);
SETGATE(idt[IRQ_OFFSET+3],0,GD_KT,irq3,0);
SETGATE(idt[IRQ_OFFSET+4],0,GD_KT,irq4,0);
SETGATE(idt[IRQ_OFFSET+5],0,GD_KT,irq5,0);
SETGATE(idt[IRQ_OFFSET+6],0,GD_KT,irq6,0);
SETGATE(idt[IRQ_OFFSET+7],0,GD_KT,irq7,0);
SETGATE(idt[IRQ_OFFSET+8],0,GD_KT,irq8,0);
SETGATE(idt[IRQ_OFFSET+9],0,GD_KT,irq9,0);
SETGATE(idt[IRQ_OFFSET+10],0,GD_KT,irq10,0);
SETGATE(idt[IRQ_OFFSET+11],0,GD_KT,irq11,0);
SETGATE(idt[IRQ_OFFSET+12],0,GD_KT,irq12,0);
SETGATE(idt[IRQ_OFFSET+13],0,GD_KT,irq13,0);
SETGATE(idt[IRQ_OFFSET+14],0,GD_KT,irq14,0);
SETGATE(idt[IRQ_OFFSET+15],0,GD_KT,irq15,0);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
/*
void vec0();
void vec1();
void vec2();
void vec3();
void vec4();
void vec6();
void vec7();
void vec8();
void vec10();
void vec11();
void vec12();
void vec13();
void vec14();
void vec16();
void vec17();
void vec18();
void vec19();
void vec48();
SETGATE(idt[0], 0, GD_KT, vec0, 0);
SETGATE(idt[1], 0, GD_KT, vec1, 0);
SETGATE(idt[2], 0, GD_KT, vec2, 0);
SETGATE(idt[3], 0, GD_KT, vec3, 3); // software interrupt
SETGATE(idt[4], 0, GD_KT, vec4, 0);
SETGATE(idt[6], 0, GD_KT, vec6, 0);
SETGATE(idt[7], 0, GD_KT, vec7, 0);
SETGATE(idt[8], 0, GD_KT, vec8, 0);
SETGATE(idt[10], 0, GD_KT, vec10, 0);
SETGATE(idt[11], 0, GD_KT, vec11, 0);
SETGATE(idt[12], 0, GD_KT, vec12, 0);
SETGATE(idt[13], 0, GD_KT, vec13, 0);
SETGATE(idt[14], 0, GD_KT, vec14, 0);
SETGATE(idt[16], 0, GD_KT, vec16, 0);
SETGATE(idt[17], 0, GD_KT, vec17, 0);
SETGATE(idt[18], 0, GD_KT, vec18, 0);
SETGATE(idt[19], 0, GD_KT, vec19, 0);
SETGATE(idt[48], 0, GD_KT, vec48, 3);
*/
extern uint32_t vectors[];
extern void vec48();
int i;
for (i = 0; i != 20; i++) {
if (i == T_BRKPT) {
SETGATE(idt[i], 0, GD_KT, vectors[i], 3);
} else {
SETGATE(idt[i], 0, GD_KT, vectors[i], 0);
}
}
SETGATE(idt[48], 0, GD_KT, vec48, 3);
// Per-CPU setup
trap_init_percpu();
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
extern void divide_handler();
extern void debug_handler();
extern void nmi_handler();
extern void brkpt_handler();
extern void oflow_handler();
extern void bound_handler();
extern void illop_handler();
extern void device_handler();
extern void dblflt_handler();
extern void tss_handler();
extern void segnp_handler();
extern void stack_handler();
extern void gpflt_handler();
extern void pgflt_handler();
extern void fperr_handler();
extern void align_handler();
extern void mchk_handler();
extern void simderr_handler();
extern void irq0();
extern void irq1();
extern void irq2();
extern void irq3();
extern void irq4();
extern void irq5();
extern void irq6();
extern void irq7();
extern void irq8();
extern void irq9();
extern void irq10();
extern void irq11();
extern void irq12();
extern void irq13();
extern void irq14();
extern void irq15();
extern void sysint_handler();
SETGATE(idt[T_DIVIDE], 0, GD_KT, divide_handler, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, debug_handler, 0);
SETGATE(idt[T_NMI], 0, GD_KT, nmi_handler, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, brkpt_handler, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, oflow_handler, 0);
SETGATE(idt[T_BOUND], 0, GD_KT, bound_handler, 0);
SETGATE(idt[T_ILLOP], 0, GD_KT, illop_handler, 0);
SETGATE(idt[T_DEVICE], 0, GD_KT, device_handler, 0);
SETGATE(idt[T_DBLFLT], 0, GD_KT, dblflt_handler, 0);
SETGATE(idt[T_TSS], 0, GD_KT, tss_handler, 0);
SETGATE(idt[T_SEGNP], 0, GD_KT, segnp_handler, 0);
SETGATE(idt[T_STACK], 0, GD_KT, stack_handler, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, gpflt_handler, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, pgflt_handler, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, fperr_handler, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, align_handler, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, mchk_handler, 0);
SETGATE(idt[T_SIMDERR],0, GD_KT, simderr_handler, 0);
SETGATE(idt[IRQ_OFFSET+0], 0, GD_KT, irq0, 0);
SETGATE(idt[IRQ_OFFSET+1], 0, GD_KT, irq1, 0);
SETGATE(idt[IRQ_OFFSET+2], 0, GD_KT, irq2, 0);
SETGATE(idt[IRQ_OFFSET+3], 0, GD_KT, irq3, 0);
SETGATE(idt[IRQ_OFFSET+4], 0, GD_KT, irq4, 0);
SETGATE(idt[IRQ_OFFSET+5], 0, GD_KT, irq5, 0);
SETGATE(idt[IRQ_OFFSET+6], 0, GD_KT, irq6, 0);
SETGATE(idt[IRQ_OFFSET+7], 0, GD_KT, irq7, 0);
SETGATE(idt[IRQ_OFFSET+8], 0, GD_KT, irq8, 0);
SETGATE(idt[IRQ_OFFSET+9], 0, GD_KT, irq9, 0);
SETGATE(idt[IRQ_OFFSET+10], 0, GD_KT, irq10, 0);
SETGATE(idt[IRQ_OFFSET+11], 0, GD_KT, irq11, 0);
SETGATE(idt[IRQ_OFFSET+12], 0, GD_KT, irq12, 0);
SETGATE(idt[IRQ_OFFSET+13], 0, GD_KT, irq13, 0);
SETGATE(idt[IRQ_OFFSET+14], 0, GD_KT, irq14, 0);
SETGATE(idt[IRQ_OFFSET+15], 0, GD_KT, irq15, 0);
SETGATE(idt[T_SYSCALL], 0, GD_KT, sysint_handler, 3);
// Per-CPU setup
trap_init_percpu();
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE], 0, GD_KT, divide_error, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, debug, 0);
SETGATE(idt[T_NMI], 0, GD_KT, nmi, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, break_point, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, overflow, 0);
SETGATE(idt[T_BOUND], 0, GD_KT, bounds, 0);
SETGATE(idt[T_ILLOP], 0, GD_KT, invalid_op, 0);
SETGATE(idt[T_DEVICE], 0, GD_KT, device_not_available, 0);
SETGATE(idt[T_DBLFLT], 0, GD_KT, double_fault, 0);
SETGATE(idt[T_TSS], 0, GD_KT, invalid_TSS, 0);
SETGATE(idt[T_SEGNP], 0, GD_KT, segment_not_present, 0);
SETGATE(idt[T_STACK], 0, GD_KT, stack_segment, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, general_protection, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, page_fault, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, float_point_error, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, alignment_check, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, machine_check, 0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, SIMD_float_point_error, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_TIMER], 0, GD_KT, timer, 0);
SETGATE(idt[T_SYSCALL], 0, GD_KT, system_call, 3);
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
void
trap_init(void)
{
extern struct Segdesc gdt[];
extern void intr_irq0();
extern void intr_irq1();
extern void intr_irq2();
extern void intr_irq3();
extern void intr_irq4();
extern void intr_irq5();
extern void intr_irq6();
extern void intr_irq7();
extern void intr_irq8();
extern void intr_irq9();
extern void intr_irq10();
extern void intr_irq11();
extern void intr_irq12();
extern void intr_irq13();
extern void intr_irq14();
extern void intr_irq15();
SETGATE( idt[IRQ_OFFSET + 0], 0, GD_KT, intr_irq0, 0);
SETGATE( idt[IRQ_OFFSET + 1], 0, GD_KT, intr_irq1, 0);
SETGATE( idt[IRQ_OFFSET + 2], 0, GD_KT, intr_irq2, 0);
SETGATE( idt[IRQ_OFFSET + 3], 0, GD_KT, intr_irq3, 0);
SETGATE( idt[IRQ_OFFSET + 4], 0, GD_KT, intr_irq4, 0);
SETGATE( idt[IRQ_OFFSET + 5], 0, GD_KT, intr_irq5, 0);
SETGATE( idt[IRQ_OFFSET + 6], 0, GD_KT, intr_irq6, 0);
SETGATE( idt[IRQ_OFFSET + 7], 0, GD_KT, intr_irq7, 0);
SETGATE( idt[IRQ_OFFSET + 8], 0, GD_KT, intr_irq8, 0);
SETGATE( idt[IRQ_OFFSET + 9], 0, GD_KT, intr_irq9, 0);
SETGATE( idt[IRQ_OFFSET + 10], 0, GD_KT, intr_irq10, 0);
SETGATE( idt[IRQ_OFFSET + 11], 0, GD_KT, intr_irq11, 0);
SETGATE( idt[IRQ_OFFSET + 12], 0, GD_KT, intr_irq12, 0);
SETGATE( idt[IRQ_OFFSET + 13], 0, GD_KT, intr_irq13, 0);
SETGATE( idt[IRQ_OFFSET + 14], 0, GD_KT, intr_irq14, 0);
SETGATE( idt[IRQ_OFFSET + 15], 1, GD_KT, intr_irq15, 0);
// LAB 3: Your code here.
/* void routine_divde();
void routine_debug();
void routine_nmi();
void routine_brkpt();
void routine_oflow();
void routine_bound();
void routine_illop();
void routine_device();
void routine_dblft();
void routine_tss();
void routine_segnp();
void routine_stack();
void routine_gpflt();
void routine_pgflt();
void routine_fperr();
void routine_syscall();
SETGATE(idt[0], 0, GD_KT, routine_divde, 0);
SETGATE(idt[1], 0, GD_KT, routine_debug, 0);
SETGATE(idt[2], 0, GD_KT, routine_nmi, 0);
SETGATE(idt[3], 0, GD_KT, routine_brkpt, 3);
SETGATE(idt[4], 0, GD_KT, routine_oflow, 0);
SETGATE(idt[5], 0, GD_KT, routine_bound, 0);
SETGATE(idt[6], 0, GD_KT, routine_illop, 0);
SETGATE(idt[7], 0, GD_KT, routine_device, 0);
SETGATE(idt[8], 0, GD_KT, routine_dblft, 0);
SETGATE(idt[10], 0, GD_KT, routine_tss, 0);
SETGATE(idt[11], 0, GD_KT, routine_segnp, 0);
SETGATE(idt[12], 0, GD_KT, routine_stack, 0);
SETGATE(idt[13], 0, GD_KT, routine_gpflt, 0);
SETGATE(idt[14], 0, GD_KT, routine_pgflt, 0);
SETGATE(idt[16], 0, GD_KT, routine_fperr, 0);
SETGATE(idt[48], 0, GD_KT, routine_syscall, 3);
*/
//Challenge
extern void (*funs[])();
int i =0 ;
while (i <=16)
{
if (i==T_BRKPT)
SETGATE(idt[i], 0, GD_KT, funs[i], 3)
else if (i!=2 && i!=15) {
SETGATE(idt[i], 0, GD_KT, funs[i], 0);
}
++i;
}
SETGATE(idt[48], 0, GD_KT, funs[48], 3);
SETGATE(idt[48], 0, GD_KT, funs[48], 3);
// Per-CPU setup
trap_init_percpu();
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
extern void divide_entry();
extern void debug_entry();
extern void nmi_entry();
extern void brkpt_entry();
extern void oflow_entry();
extern void bound_entry();
extern void illop_entry();
extern void device_entry();
extern void dblflt_entry();
extern void tts_entry();
extern void segnp_entry();
extern void stack_entry();
extern void gpflt_entry();
extern void pgflt_entry();
extern void fperr_entry();
extern void align_entry();
extern void mchk_entry();
extern void simderr_entry();
extern void syscall_entry();
extern void irq_timer_entry();
extern void irq_kbd_entry();
extern void irq_serial_entry();
extern void irq_spurious_entry();
extern void irq_error_entry();
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE], 0, GD_KT, divide_entry, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, debug_entry, 0);
SETGATE(idt[T_NMI], 0, GD_KT, nmi_entry, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, brkpt_entry, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, oflow_entry, 3);
SETGATE(idt[T_BOUND], 0, GD_KT, bound_entry, 3);
SETGATE(idt[T_ILLOP], 0, GD_KT, illop_entry, 3);
SETGATE(idt[T_DEVICE], 0, GD_KT, device_entry, 3);
SETGATE(idt[T_DBLFLT], 0, GD_KT, dblflt_entry, 3);
SETGATE(idt[T_TSS], 0, GD_KT, tts_entry, 0);
SETGATE(idt[T_STACK], 0, GD_KT, stack_entry, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, gpflt_entry, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, pgflt_entry, 3);
SETGATE(idt[T_FPERR], 0, GD_KT, fperr_entry, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, align_entry, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, mchk_entry, 0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, simderr_entry, 0);
SETGATE(idt[T_SYSCALL],0, GD_KT, syscall_entry, 3);
/* lab4 irqs */
SETGATE(idt[IRQ_OFFSET + IRQ_TIMER], 0, GD_KT, irq_timer_entry, 0);
/* lab4 irqs */
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 2: Your code here.
extern uint32_t handler0;// divide error
extern uint32_t handler1;// debug exception
extern uint32_t handler2;// non-maskable interrupt
extern uint32_t handler3;// breakpoint
extern uint32_t handler4;// overflow
extern uint32_t handler5;// bounds check
extern uint32_t handler6;// illegal opcode
extern uint32_t handler7;// device not available
extern uint32_t handler8;// double fault
extern uint32_t handler9;// reserved (not generated by recent processors)
extern uint32_t handler10;// invalid task switch segment
extern uint32_t handler11;// segment not present
extern uint32_t handler12;// stack exception
extern uint32_t handler13;// general protection fault
extern uint32_t handler14;// page fault
extern uint32_t handler15;// reserved
extern uint32_t handler16;// floating point error
extern uint32_t handler17;// aligment check
extern uint32_t handler18;// machine check
extern uint32_t handler19;// SIMD floating point error
extern uint32_t handler48;// System Call
SETGATE(idt[1],1,GD_KT,&handler1,0);
SETGATE(idt[2],1,GD_KT,&handler2,0);
SETGATE(idt[3],1,GD_KT,&handler3,3);//intercept accessible from userlevel
SETGATE(idt[4],1,GD_KT,&handler4,0);
SETGATE(idt[5],1,GD_KT,&handler5,0);
SETGATE(idt[6],1,GD_KT,&handler6,0);
SETGATE(idt[7],1,GD_KT,&handler7,0);
SETGATE(idt[8],1,GD_KT,&handler8,0);
SETGATE(idt[9],1,GD_KT,&handler9,0);
SETGATE(idt[10],1,GD_KT,&handler10,0);
SETGATE(idt[11],1,GD_KT,&handler11,0);
SETGATE(idt[12],1,GD_KT,&handler12,0);
SETGATE(idt[13],1,GD_KT,&handler13,0);
SETGATE(idt[14],1,GD_KT,&handler14,0);
SETGATE(idt[15],1,GD_KT,&handler15,0);
SETGATE(idt[16],1,GD_KT,&handler16,0);
SETGATE(idt[17],1,GD_KT,&handler17,0);
SETGATE(idt[18],1,GD_KT,&handler18,0);
SETGATE(idt[19],1,GD_KT,&handler19,0);
// Set a gate for the system call interrupt.
// Hint: Must this gate be accessible from userlevel?
// LAB 3: Your code here.
SETGATE(idt[48],0,GD_KT,&handler48,3);
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
