/* Queue a division exception. */
enum frv_dtt
frvbf_division_exception (SIM_CPU *current_cpu, enum frv_dtt dtt,
int target_index, int non_excepting)
{
/* If there was an overflow and it is masked, then record it in
ISR.AEXC. */
USI isr = GET_ISR ();
if ((dtt & FRV_DTT_OVERFLOW) && GET_ISR_EDE (isr))
{
dtt &= ~FRV_DTT_OVERFLOW;
SET_ISR_AEXC (isr);
SET_ISR (isr);
}
if (dtt != FRV_DTT_NO_EXCEPTION)
{
if (non_excepting)
{
/* Non excepting instruction, simply set the NE flag for the target
register. */
SI NE_flags[2];
GET_NE_FLAGS (NE_flags, H_SPR_GNER0);
SET_NE_FLAG (NE_flags, target_index);
SET_NE_FLAGS (H_SPR_GNER0, NE_flags);
}
else
frv_queue_division_exception_interrupt (current_cpu, dtt);
}
return dtt;
}
/* Record the state of a division exception in the ISR. */
static void
set_isr_exception_fields (
SIM_CPU *current_cpu, struct frv_interrupt_queue_element *item
)
{
USI isr = GET_ISR ();
int dtt = GET_ISR_DTT (isr);
dtt |= item->u.dtt;
SET_ISR_DTT (isr, dtt);
SET_ISR (isr);
}
