/** * @brief Send data to slave(ESP8266 register of RD_STATUS or WR_STATUS). * */ void ICACHE_FLASH_ATTR SPIMasterSendStatus (SpiNum spiNum, uint8_t data) { if (spiNum > SpiNum_HSPI) { return; } while (READ_PERI_REG(SPI_CMD(spiNum)) & SPI_USR) ; // Enable MOSI SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO | SPI_USR_DUMMY | SPI_USR_ADDR); // 8bits cmd, 0x04 is eps8266 slave write cmd value WRITE_PERI_REG(SPI_USER2(spiNum), ((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | MASTER_WRITE_STATUS_TO_SLAVE_CMD); // Set data send buffer length. SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ( (sizeof (data) << 3) - 1), SPI_USR_MOSI_BITLEN_S); WRITE_PERI_REG(SPI_W0(spiNum), (uint32 ) (data)); // Start SPI SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); }
/** * @brief Receive status register from slave(ESP8266). * */ int ICACHE_FLASH_ATTR SPIMasterRecvStatus (SpiNum spiNum) { if (spiNum > SpiNum_HSPI) { return -1; } while (READ_PERI_REG(SPI_CMD(spiNum)) & SPI_USR) ; // Enable MISO SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI | SPI_USR_DUMMY | SPI_USR_ADDR); // 8bits cmd, 0x06 is eps8266 slave read status cmd value WRITE_PERI_REG(SPI_USER2(spiNum), ((7 & SPI_USR_COMMAND_BITLEN) << SPI_USR_COMMAND_BITLEN_S) | MASTER_READ_STATUS_FROM_SLAVE_CMD); // Set revcive buffer length. SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN, 7, SPI_USR_MISO_BITLEN_S); // start spi module. SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum)) & SPI_USR) ; uint8_t data = (uint8) (READ_PERI_REG(SPI_W0(spiNum)) & 0xff); return (uint8) (READ_PERI_REG(SPI_W0(spiNum)) & 0xff); }
/** * @brief Select SPI CS pin. * */ void ICACHE_FLASH_ATTR SPICsPinSelect(SpiNum spiNum, SpiPinCS pinCs) { if (spiNum > SpiNum_HSPI) { return; } // clear select SET_PERI_REG_BITS(SPI_PIN(spiNum), 3, 0, 0); SET_PERI_REG_MASK(SPI_PIN(spiNum), pinCs); }
void gpio_output_sigmadelta_enable(uint32 gpio_num, uint32 sigma_num, uint32 prescale) { if (sigma_num >= 8) { return; } SET_PERI_REG_BITS(SIGMADELTA0 + sigma_num * 4, SIGMADELTA_SD0_PRESCALE, prescale, SIGMADELTA_SD0_PRESCALE_S); gpio_matrix_out(gpio_num, GPIO_SD0_OUT_IDX + sigma_num); }
/** * @brief Set command value by master mode. * */ void ICACHE_FLASH_ATTR SPIMasterCfgCmd(SpiNum spiNum, uint32_t cmd) { if (spiNum > SpiNum_HSPI) { return; } // SPI_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1, // bit15-0 is cmd value. SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_VALUE, cmd, SPI_USR_COMMAND_VALUE_S); }
//only when USART_HardwareFlowControl_RTS is set , will the rx_thresh value be set. void UART_SetFlowCtrl(UART_Port uart_no, UART_HwFlowCtrl flow_ctrl, uint8 rx_thresh) { if (flow_ctrl & USART_HardwareFlowControl_RTS) { PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS); SET_PERI_REG_BITS(UART_CONF1(uart_no), UART_RX_FLOW_THRHD, rx_thresh, UART_RX_FLOW_THRHD_S); SET_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN); } else { CLEAR_PERI_REG_MASK(UART_CONF1(uart_no), UART_RX_FLOW_EN); } if (flow_ctrl & USART_HardwareFlowControl_CTS) { PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_UART0_CTS); SET_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN); } else { CLEAR_PERI_REG_MASK(UART_CONF0(uart_no), UART_TX_FLOW_EN); } }
/** * @brief Based on pAttr initialize SPI module. * */ void ICACHE_FLASH_ATTR SPIInit (SpiNum spiNum, SpiAttr* pAttr) { if ((spiNum > SpiNum_HSPI) || (NULL == pAttr)) { return; } // SPI_CPOL & SPI_CPHA switch (pAttr->subMode) { case SpiSubMode_1: CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE break; case SpiSubMode_2: SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // CHPA_FALLING_EDGE_SAMPLE break; case SpiSubMode_3: SET_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); break; case SpiSubMode_0: default: CLEAR_PERI_REG_MASK(SPI_PIN(spiNum), SPI_IDLE_EDGE); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_CK_OUT_EDGE); // To do nothing break; } // SPI bit order if (SpiBitOrder_MSBFirst == pAttr->bitOrder) { CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER); CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER); } else if (SpiBitOrder_LSBFirst == pAttr->bitOrder) { SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_WR_BIT_ORDER); SET_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_RD_BIT_ORDER); } else { // To do nothing } // Disable flash operation mode // As earlier as better, if not SPI_CTRL2 can not to be set delay cycles. CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_FLASH_MODE); // SPI mode type if (SpiMode_Master == pAttr->mode) { // SPI mode type CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE); // SPI Send buffer CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART);// By default slave send buffer C0-C7 // SPI Speed if (1 < (pAttr->speed)) { uint8 i, k; i = (pAttr->speed / 40) ? (pAttr->speed / 40) : 1; k = pAttr->speed / i; CLEAR_PERI_REG_MASK(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); WRITE_PERI_REG(SPI_CLOCK(spiNum), (((i - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) | (((k - 1) & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) | ((((k + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) | (((k - 1) & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div } else { WRITE_PERI_REG(SPI_CLOCK(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed } // By default format:CMD+ADDR+DATA SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI); //delay num SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MISO_DELAY_NUM) << SPI_MISO_DELAY_NUM_S)); } else if (SpiMode_Slave == pAttr->mode) { // BIT19 must do SET_PERI_REG_MASK(SPI_PIN(spiNum), BIT19); // SPI mode type SET_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_SLAVE_MODE); // SPI Send buffer SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO_HIGHPART);// By default slave send buffer C8-C15 SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); // If do not set delay cycles, slave not working,master cann't get the data. SET_PERI_REG_MASK(SPI_CTRL2(spiNum), ((0x1 & SPI_MOSI_DELAY_NUM) << SPI_MOSI_DELAY_NUM_S)); //delay num // SPI Speed WRITE_PERI_REG(SPI_CLOCK(spiNum), 0); // By default format::CMD(8bits)+ADDR(8bits)+DATA(32bytes). SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, 7, SPI_USR_COMMAND_BITLEN_S); SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_WR_ADDR_BITLEN, 7, SPI_SLV_WR_ADDR_BITLEN_S); SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_RD_ADDR_BITLEN, 7, SPI_SLV_RD_ADDR_BITLEN_S); SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_BUF_BITLEN, (32 * 8 - 1), SPI_SLV_BUF_BITLEN_S); // For 8266 work on slave mode. SET_PERI_REG_BITS(SPI_SLAVE1(spiNum), SPI_SLV_STATUS_BITLEN, 7, SPI_SLV_STATUS_BITLEN_S); } else { // To do nothing } //clear Daul or Quad lines transmission mode CLEAR_PERI_REG_MASK(SPI_CTRL(spiNum), SPI_QIO_MODE | SPI_DIO_MODE | SPI_DOUT_MODE | SPI_QOUT_MODE); // Clear the data buffer. uint8 i; uint32 regAddr = REG_SPI_BASE(spiNum) + 0x40; for (i = 0; i < 16; ++i) { WRITE_PERI_REG(regAddr, 0); regAddr += 4; } }
/** * @brief Receive data from slave. * */ int ICACHE_FLASH_ATTR SPIMasterRecvData (SpiNum spiNum, SpiData* pOutData) { char idx = 0; if ( (spiNum > SpiNum_HSPI) || (NULL == pOutData)) { return -1; } uint32_t *value = pOutData->data; while (READ_PERI_REG(SPI_CMD(spiNum)) & SPI_USR) ; // Set command by user. if (pOutData->cmdLen != 0) { // Max command length 16 bits. SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, ( (pOutData->cmdLen << 3) - 1), SPI_USR_COMMAND_BITLEN_S); // Enable command SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND); // Load command SPIMasterCfgCmd (spiNum, pOutData->cmd); } else { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND); SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S); } // Set Address by user. if (pOutData->addrLen == 0) { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, 0, SPI_USR_ADDR_BITLEN_S); } else { if (NULL == pOutData->addr) { return -1; } SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, ( (pOutData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S); // Enable address SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); // Load address SPIMasterCfgAddr (spiNum, *pOutData->addr); } // Set data by user. if (pOutData->dataLen != 0) { if (NULL == value) { return -1; } // Clear MOSI enable CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); // Enable MOSI SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); // Set data send buffer length.Max data length 64 bytes. SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN, ( (pOutData->dataLen << 3) - 1), SPI_USR_MISO_BITLEN_S); } else { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MISO_BITLEN, 0, SPI_USR_MISO_BITLEN_S); } // Start send data SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); while (READ_PERI_REG(SPI_CMD(spiNum)) & SPI_USR) ; // Read data out do { *pOutData->data++ = READ_PERI_REG(SPI_W0(spiNum) + (idx << 2)); } while ( ++idx < (pOutData->dataLen / 4)); return 0; }
/** * @brief Send data to slave. * */ int ICACHE_FLASH_ATTR SPIMasterSendData (SpiNum spiNum, SpiData* pInData) { char idx = 0; if ( (spiNum > SpiNum_HSPI) || (NULL == pInData) || (64 < pInData->dataLen)) { return -1; } uint32_t *value = pInData->data; while (READ_PERI_REG(SPI_CMD(spiNum)) & SPI_USR) ; // Set command by user. if (pInData->cmdLen != 0) { // Max command length 16 bits. SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, ( (pInData->cmdLen << 3) - 1), SPI_USR_COMMAND_BITLEN_S); // Enable command SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND); // Load command SPIMasterCfgCmd (spiNum, pInData->cmd); } else { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_COMMAND); SET_PERI_REG_BITS(SPI_USER2(spiNum), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S); } // Set Address by user. if (pInData->addrLen == 0) { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, 0, SPI_USR_ADDR_BITLEN_S); } else { if (NULL == pInData->addr) { return -1; } SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_ADDR_BITLEN, ( (pInData->addrLen << 3) - 1), SPI_USR_ADDR_BITLEN_S); // Enable address SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_ADDR); // Load address SPIMasterCfgAddr (spiNum, *pInData->addr); } // Set data by user. if (pInData->dataLen != 0) { if (NULL == value) { return -1; } // Enable MOSI SET_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MISO); // Load send buffer do { WRITE_PERI_REG((SPI_W0(spiNum) + (idx << 2)), *value++); } while ( ++idx < (pInData->dataLen / 4)); // Set data send buffer length.Max data length 64 bytes. SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, ( (pInData->dataLen << 3) - 1), SPI_USR_MOSI_BITLEN_S); } else { CLEAR_PERI_REG_MASK(SPI_USER(spiNum), SPI_USR_MOSI); SET_PERI_REG_BITS(SPI_USER1(spiNum), SPI_USR_MOSI_BITLEN, 0, SPI_USR_MOSI_BITLEN_S); } // Start send data SET_PERI_REG_MASK(SPI_CMD(spiNum), SPI_USR); // Wait for transmit done while ( ! (READ_PERI_REG(SPI_SLAVE(spiNum)) & SPI_TRANS_DONE)) ; CLEAR_PERI_REG_MASK(SPI_SLAVE(spiNum), SPI_TRANS_DONE); return 0; }
void rtc_clk_init(rtc_clk_config_t cfg) { rtc_cpu_freq_config_t old_config, new_config; /* If we get a TG WDT system reset while running at 240MHz, * DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz * APB and CPU frequencies after reset. This will cause issues with XTAL * frequency estimation, so we switch to XTAL frequency first. * * Ideally we would only do this if RTC_CNTL_SOC_CLK_SEL == PLL and * PLL is configured for 480M, but it takes less time to switch to 40M and * run the following code than querying the PLL does. */ if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) == RTC_CNTL_SOC_CLK_SEL_PLL) { /* We don't know actual XTAL frequency yet, assume 40MHz. * REF_TICK divider will be corrected below, once XTAL frequency is * determined. */ rtc_clk_cpu_freq_to_xtal(40, 1); } /* Set tuning parameters for 8M and 150k clocks. * Note: this doesn't attempt to set the clocks to precise frequencies. * Instead, we calibrate these clocks against XTAL frequency later, when necessary. * - SCK_DCAP value controls tuning of 150k clock. * The higher the value of DCAP is, the lower is the frequency. * - CK8M_DFREQ value controls tuning of 8M clock. * CLK_8M_DFREQ constant gives the best temperature characteristics. */ REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap); REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq); /* Configure 8M clock division */ REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, cfg.clk_8m_div); /* Enable the internal bus used to configure PLLs */ SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S); CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M); /* Estimate XTAL frequency */ rtc_xtal_freq_t xtal_freq = cfg.xtal_freq; if (xtal_freq == RTC_XTAL_FREQ_AUTO) { if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) { /* XTAL frequency has already been set, use existing value */ xtal_freq = rtc_clk_xtal_freq_get(); } else { /* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */ xtal_freq = rtc_clk_xtal_freq_estimate(); if (xtal_freq == RTC_XTAL_FREQ_AUTO) { SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz"); xtal_freq = RTC_XTAL_FREQ_26M; } } } else if (!clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) { /* Exact frequency was set in sdkconfig, but still warn if autodetected * frequency is different. If autodetection failed, worst case we get a * bit of garbage output. */ rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate(); if (est_xtal_freq != xtal_freq) { SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.", xtal_freq, est_xtal_freq); } } uart_tx_wait_idle(0); rtc_clk_xtal_freq_update(xtal_freq); rtc_clk_apb_freq_update(xtal_freq * MHZ); /* Set CPU frequency */ rtc_clk_cpu_freq_get_config(&old_config); uint32_t freq_before = old_config.freq_mhz; bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config); if (!res) { SOC_LOGE(TAG, "invalid CPU frequency value"); abort(); } rtc_clk_cpu_freq_set_config(&new_config); /* Configure REF_TICK */ REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, xtal_freq - 1); REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, APB_CLK_FREQ / MHZ - 1); /* Under PLL, APB frequency is always 80MHz */ /* Re-calculate the ccount to make time calculation correct. */ XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * cfg.cpu_freq_mhz / freq_before ); /* Slow & fast clocks setup */ if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) { rtc_clk_32k_enable(true); } if (cfg.fast_freq == RTC_FAST_FREQ_8M) { bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256; rtc_clk_8m_enable(true, need_8md256); } rtc_clk_fast_freq_set(cfg.fast_freq); rtc_clk_slow_freq_set(cfg.slow_freq); }
static void gpio_intr_init(uint32 intr_num, GPIO_INT_TYPE intr_type) { uint32 cfg0_addr = PCNT_U0_CONF0 + (intr_num * 12); uint32 cfg1_addr = PCNT_U0_CONF1 + (intr_num * 12); uint32 cfg2_addr = PCNT_U0_CONF2 + (intr_num * 12); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH1_LCTRL_MODE_U0, 0, PCNT_CH1_LCTRL_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH1_HCTRL_MODE_U0, 0, PCNT_CH1_HCTRL_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH1_POS_MODE_U0, 0, PCNT_CH1_POS_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH1_NEG_MODE_U0, 0, PCNT_CH1_NEG_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_LCTRL_MODE_U0, 0, PCNT_CH0_LCTRL_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_HCTRL_MODE_U0, 0, PCNT_CH0_HCTRL_MODE_U0_S); if (intr_type == GPIO_PIN_INTR_NEGEDGE) { SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_POS_MODE_U0, 0, PCNT_CH0_POS_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_NEG_MODE_U0, 1, PCNT_CH0_NEG_MODE_U0_S); } else if (intr_type == GPIO_PIN_INTR_POSEDGE) { SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_POS_MODE_U0, 1, PCNT_CH0_POS_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_NEG_MODE_U0, 0, PCNT_CH0_NEG_MODE_U0_S); } else if (intr_type == GPIO_PIN_INTR_ANYEDGE) { SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_POS_MODE_U0, 1, PCNT_CH0_POS_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_NEG_MODE_U0, 1, PCNT_CH0_NEG_MODE_U0_S); } else { SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_POS_MODE_U0, 0, PCNT_CH0_POS_MODE_U0_S); SET_PERI_REG_BITS(cfg0_addr, PCNT_CH0_NEG_MODE_U0, 0, PCNT_CH0_NEG_MODE_U0_S); } SET_PERI_REG_BITS(cfg1_addr, PCNT_CNT_THRES0_U0, 1, PCNT_CNT_THRES0_U0_S); SET_PERI_REG_BITS(cfg2_addr, PCNT_CNT_L_LIM_U0, 10, PCNT_CNT_L_LIM_U0_S); SET_PERI_REG_BITS(cfg2_addr, PCNT_CNT_H_LIM_U0, 10, PCNT_CNT_H_LIM_U0_S); CLEAR_PERI_REG_MASK(cfg0_addr, (PCNT_THR_THRES1_EN_U0 | PCNT_THR_L_LIM_EN_U0 | PCNT_THR_H_LIM_EN_U0 | PCNT_THR_ZERO_EN_U0 | PCNT_FILTER_EN_U0)); SET_PERI_REG_MASK(cfg0_addr, PCNT_THR_THRES0_EN_U0); SET_PERI_REG_MASK(PCNT_INT_ENA, BIT(intr_num)); }
void UART_SetStopBits(UART_Port uart_no, UART_StopBits bit_num) { SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_STOP_BIT_NUM, bit_num, UART_STOP_BIT_NUM_S); }
void UART_SetWordLength(UART_Port uart_no, UART_WordLength len) { SET_PERI_REG_BITS(UART_CONF0(uart_no), UART_BIT_NUM, len, UART_BIT_NUM_S); }