int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (is_serdes_configured(SGMII_TSEC3)) { puts("eTSEC3 is in sgmii mode."); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET struct tsec_info_struct tsec_info[2]; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } if (io_sel & 1) fsl_sgmii_riser_init(tsec_info, num); tsec_eth_init(bis, tsec_info, num); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[2]; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } /* Register 1G MDIO bus */ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
int board_eth_init(bd_t *bd) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[2]; struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; u32 rcwh = in_be32(&im->reset.rcwh); u32 tsec_mode; int num = 0; /* New line after Net: */ printf("\n"); #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); printf(CONFIG_TSEC1_NAME ": "); tsec_mode = rcwh & HRCWH_TSEC1M_MASK; if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) { printf("RGMII\n"); /* this is default, no need to fixup */ } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) { printf("SGMII\n"); tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII; tsec_info[num].flags = TSEC_GIGABIT; } else { printf("unsupported PHY type\n"); } num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); printf(CONFIG_TSEC2_NAME ": "); tsec_mode = rcwh & HRCWH_TSEC2M_MASK; if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) { printf("RGMII\n"); /* this is default, no need to fixup */ } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) { printf("SGMII\n"); tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII; tsec_info[num].flags = TSEC_GIGABIT; } else { printf("unsupported PHY type\n"); } num++; #endif mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bd, &mdio_info); return tsec_eth_init(bd, tsec_info, num); }
int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[3]; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); if (is_serdes_configured(SGMII_TSEC1)) { puts("eTSEC1 is in sgmii mode\n"); tsec_info[num].flags |= TSEC_SGMII; tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; } else { tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; } num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); if (is_serdes_configured(SGMII_TSEC2)) { puts("eTSEC2 is in sgmii mode\n"); tsec_info[num].flags |= TSEC_SGMII; tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; } else { tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_init(tsec_info, num); #endif mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); /* Register the virtual MDIO front-ends */ ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO"); ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO"); tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
void my_tsec_init() { int num = 0; char *tmp; unsigned int vscfw_addr; struct tsec_info_struct tsec_info[4]; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); //Здесь идет заполнение структуры для tsec определение расположения регистров и адресов !! //где находить трансивер физического уровня #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif if (!num) { //printf("No TSECs initialized\n"); //return 0; } //#ifdef CONFIG_VSC7385_ENET // If a VSC7385 microcode image is present, then upload it. // if ((tmp = getenv ("vscfw_addr")) != NULL) { // vscfw_addr = simple_strtoul (tmp, NULL, 16); // printf("uploading VSC7385 microcode from %x\n", vscfw_addr); // if (vsc7385_upload_firmware((void *) vscfw_addr, // CONFIG_VSC7385_IMAGE_SIZE)) // puts("Failure uploading VSC7385 microcode.\n"); // } else // puts("No address specified for VSC7385 microcode.\n"); //#endif tsec_eth_init(bis, tsec_info, num); }
int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; char *tmp; unsigned int vscfw_addr; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (is_serdes_configured(SGMII_TSEC3)) { puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_VSC7385_ENET /* If a VSC7385 microcode image is present, then upload it. */ if ((tmp = getenv ("vscfw_addr")) != NULL) { vscfw_addr = simple_strtoul (tmp, NULL, 16); printf("uploading VSC7385 microcode from %x\n", vscfw_addr); if (vsc7385_upload_firmware((void *) vscfw_addr, CONFIG_VSC7385_IMAGE_SIZE)) puts("Failure uploading VSC7385 microcode.\n"); } else puts("No address specified for VSC7385 microcode.\n"); #endif mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); num++; #endif #ifdef CONFIG_TSEC3 /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */ if (get_board_version() >= 0x13) { SET_STD_TSEC_INFO(tsec_info[num], 3); tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; num++; } #endif #ifdef CONFIG_TSEC4 /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */ if (get_board_version() >= 0x13) { SET_STD_TSEC_INFO(tsec_info[num], 4); tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; num++; } #endif if (!num) { printf("No TSECs initialized\n"); return 0; } mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); configure_rgmii(); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[2]; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); if (is_serdes_configured(SGMII_TSEC1)) { puts("eTSEC1 is in sgmii mode.\n"); tsec_info[num].phyaddr = 0; tsec_info[num].flags |= TSEC_SGMII; } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (is_serdes_configured(SGMII_TSEC3)) { puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].phyaddr = 1; tsec_info[num].flags |= TSEC_SGMII; } num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_FSL_SGMII_RISER if (is_serdes_configured(SGMII_TSEC1) || is_serdes_configured(SGMII_TSEC3)) { fsl_sgmii_riser_init(tsec_info, num); } #endif mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { struct tsec_info_struct tsec_info[4]; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif #ifdef CONFIG_TSEC4 SET_STD_TSEC_INFO(tsec_info[num], 4); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_init(tsec_info, num); #endif tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { struct tsec_info_struct tsec_info[4]; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; char *tmp; unsigned int vscfw_addr; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) tsec_info[num].flags |= TSEC_SGMII; num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_VSC7385_ENET /* If a VSC7385 microcode image is present, then upload it. */ if ((tmp = getenv ("vscfw_addr")) != NULL) { vscfw_addr = simple_strtoul (tmp, NULL, 16); printf("uploading VSC7385 microcode from %x\n", vscfw_addr); if (vsc7385_upload_firmware((void *) vscfw_addr, CONFIG_VSC7385_IMAGE_SIZE)) puts("Failure uploading VSC7385 microcode.\n"); } else puts("No address specified for VSC7385 microcode.\n"); #endif tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { #ifdef CONFIG_TSEC_ENET struct tsec_info_struct tsec_info[2]; volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; uint sdrs2_io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) { tsec_info[num].phyaddr = 0; tsec_info[num].flags |= TSEC_SGMII; } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (sdrs2_io_sel == 4) { tsec_info[num].phyaddr = 1; tsec_info[num].flags |= TSEC_SGMII; } num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_FSL_SGMII_RISER if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) fsl_sgmii_riser_init(tsec_info, num); #endif tsec_eth_init(bis, tsec_info, num); #endif return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; struct cpu_type *cpu; int num = 0; cpu = gd->arch.cpu; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); num++; #endif #ifdef CONFIG_TSEC3 /* P1014 and it's derivatives do not support eTSEC3 */ if (cpu->soc_ver != SVR_P1014) { SET_STD_TSEC_INFO(tsec_info[num], 3); num++; } #endif if (!num) { printf("No TSECs initialized\n"); return 0; } mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; ccsr_gur_t *gur __attribute__((unused)) = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; #ifdef CONFIG_VSC7385_ENET char *tmp; unsigned int vscfw_addr; #endif #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); if (is_serdes_configured(SGMII_TSEC2)) { printf("eTSEC2 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_VSC7385_ENET /* If a VSC7385 microcode image is present, then upload it. */ tmp = env_get("vscfw_addr"); if (tmp) { vscfw_addr = simple_strtoul(tmp, NULL, 16); printf("uploading VSC7385 microcode from %x\n", vscfw_addr); if (vsc7385_upload_firmware((void *) vscfw_addr, CONFIG_VSC7385_IMAGE_SIZE)) puts("Failure uploading VSC7385 microcode.\n"); } else puts("No address specified for VSC7385 microcode.\n"); #endif mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); #if defined(CONFIG_UEC_ETH) /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); uec_standard_init(bis); #endif return pci_eth_init(bis); }