static int32_t bsp_usb_dev_io_init ( int32_t i ) { if (i == USB_CONTROLLER_KHCI_0) { #if BSPCFG_USB_USE_IRC48M /* * Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0 */ SIM_CLKDIV2 = (uint32_t)0x0UL; /* Update USB clock prescalers */ /* Configure USB to be clocked from IRC 48MHz */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK; /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK; /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* Configure USB to be clocked from PLL0 */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBSRC_MASK; /* Configure USB divider to be 120MHz * 2 / 5 = 48 MHz */ SIM_CLKDIV2_REG(SIM_BASE_PTR) = SIM_CLKDIV2_USBDIV(4) | SIM_CLKDIV2_USBFRAC_MASK; /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBOTG_MASK; #endif } else { return -1; //unknow controller } return 0; }
static _mqx_int _bsp_usb_io_init ( _mqx_uint i ) { if (i == 0) { #if PE_LDD_VERSION /* USB clock is configured using CPU component */ /* Check if peripheral is not used by Processor Expert USB_LDD component */ if (PE_PeripheralUsed((uint_32)USB0_BASE_PTR) == TRUE) { /* IO Device used by PE Component*/ return IO_ERROR; } #endif /* Configure USB to be clocked from PLL0 */ SIM_SOPT2_REG(SIM_BASE_PTR) &= ~(SIM_SOPT2_USBFSRC_MASK); SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBFSRC(1); /* Configure USB to be clocked from clock divider */ SIM_SOPT2_REG(SIM_BASE_PTR) |= SIM_SOPT2_USBF_CLKSEL_MASK; /* Configure USB divider to be 120MHz * 2 / 5 = 48 MHz */ SIM_CLKDIV2_REG(SIM_BASE_PTR) &= ~(SIM_CLKDIV2_USBFSDIV_MASK | SIM_CLKDIV2_USBFSFRAC_MASK); SIM_CLKDIV2_REG(SIM_BASE_PTR) |= SIM_CLKDIV2_USBFSDIV(4) | SIM_CLKDIV2_USBFSFRAC_MASK; /* Enable USB-OTG IP clocking */ SIM_SCGC4_REG(SIM_BASE_PTR) |= SIM_SCGC4_USBFS_MASK; /* USB D+ and USB D- are standalone not multiplexed one-purpose pins */ /* VREFIN for device is standalone not multiplexed one-purpose pin */ #if BSP_USB_TWR_SER2 /* TWR-SER2 board has 2 connectors: on channel A, there is Micro-USB connector, ** which is not routed to TWRK60 board. On channel B, there is standard ** A-type host connector routed to the USB0 peripheral on TWRK60. To enable ** power to this connector, GPIO PB8 must be set as GPIO output */ PORT_PCR_REG(PORTB_BASE_PTR, 8) = PORT_PCR_MUX(0x01); GPIO_PDDR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 as output GPIO_PDOR_REG(PTB_BASE_PTR) |= 0x00000100; // PB8 in high level #endif } else if (i == 1) { //Disable MPU so the module can access RAM MPU_CESR &= ~MPU_CESR_VLD_MASK; //Enable clock to the module SIM_SCGC6 |= SIM_SCGC6_USBHS_MASK; // SIM_MCR &= (uint32_t)~0x40000000UL; /* Disconnect internal generated ULPI clock from pin */ // SIM_CLKDIV2 |= SIM_CLKDIV2_USBHSFRAC_MASK | SIM_CLKDIV2_USBHSDIV_MASK; // Divide reference clock to obtain 60MHz // SIM_SOPT2 |= SIM_SOPT2_USBHSRC(1); // MCGPLLCLK for the USB 60MHz CLKC source //Select external clock for USBH controller SIM_SOPT2 |= SIM_SOPT2_USBH_CLKSEL_MASK; PORTA_PCR7 = PORT_PCR_MUX(2); //ULPI DIR PORTA_PCR8 = PORT_PCR_MUX(2); //ULPI NXT PORTA_PCR10 = PORT_PCR_MUX(2); //ULPI DATA0 PORTA_PCR11 = PORT_PCR_MUX(2); //ULPI DATA1 PORTA_PCR24 = PORT_PCR_MUX(2); //ULPI DATA2 PORTA_PCR25 = PORT_PCR_MUX(2); //ULPI DATA3 PORTA_PCR26 = PORT_PCR_MUX(2); //ULPI DATA4 PORTA_PCR27 = PORT_PCR_MUX(2); //ULPI DATA5 PORTA_PCR28 = PORT_PCR_MUX(2); //ULPI DATA6 PORTA_PCR29 = PORT_PCR_MUX(2); //ULPI DATA7 PORTA_PCR6 = PORT_PCR_MUX(2); //ULPI CLK PORTA_PCR9 = PORT_PCR_MUX(2); //ULPI STP } else { return IO_ERROR; //unknow controller } return MQX_OK; }