static inline void set_fll_source(void) { /* Select FLL as source (as opposed to PLL) */ SIM->SOPT2 &= ~(SIM_SOPT2_PLLFLLSEL_MASK); /* Use external 32kHz RTC clock as source for OSC32K */ /* This is also done by hwtimer_arch, but we need it sooner than * hwtimer_init. */ #if K60_CPU_REV == 1 SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL_MASK; #elif K60_CPU_REV == 2 SIM->SOPT1 = (SIM->SOPT1 & ~(SIM_SOPT1_OSC32KSEL_MASK)) | SIM_SOPT1_OSC32KSEL(2); #else #error Unknown K60 CPU revision #endif /* Select RTC 32kHz clock as reference clock for the FLL */ #if K60_CPU_REV == 1 /* Rev 1 parts */ SIM->SOPT2 |= SIM_SOPT2_MCGCLKSEL_MASK; #elif K60_CPU_REV == 2 /* Rev 2 parts */ MCG->C7 = (MCG_C7_OSCSEL_MASK); #else #error Unknown K60 CPU revision #endif }
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */ void __init_hardware(void) { /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/ /*** ### MKL25Z128VLK4 "Cpu" init code ... ***/ /*** PE initialization code after reset ***/ SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */ /* Disable the WDOG module */ /* SIM_COPC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COPT=0,COPCLKS=0,COPW=0 */ SIM_COPC = SIM_COPC_COPT(0x00); /* System clock initialization */ /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescalers to safe value */ /* SIM_SCGC5: PORTD=1,PORTB=1,PORTA=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) { /* PMC_REGSC: ACKISO=1 */ PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */ } /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */ /* SIM_SOPT2: PLLFLLSEL=0 */ SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=3 */ SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ /* SIM_SOPT2: TPMSRC=1 */ SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)( SIM_SOPT2_TPMSRC(0x02) )) | (uint32_t)( SIM_SOPT2_TPMSRC(0x01) )); /* Set the TPM clock */ /* Switch to FEI Mode */ /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ MCG_C2 = MCG_C2_RANGE0(0x00); /* MCG_C4: DMX32=0,DRST_DRS=0 */ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0_CR = OSC_CR_ERCLKEN_MASK; /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ MCG_C5 = MCG_C5_PRDIV0(0x00); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG_C6 = MCG_C6_VDIV0(0x00); while((MCG_S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ } while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ } /*** End of PE initialization code after reset ***/ /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/ }
void rtc_init(void) { /*enable the clock to SRTC module register space*/ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; // Ensure PTC1 configured as RTC inpuit cloclk PORTC_PCR1 &= ~PORT_PCR_MUX_MASK ; PORTC_PCR1 = PORT_PCR_MUX(1) ; SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(2); // RTC clock in #ifdef CMSIS //enable_irq((IRQn_Type)(INT_RTC-16)); //enable_irq((IRQn_Type)(INT_RTC_Seconds-16)); NVIC_EnableIRQ(RTC_IRQn); NVIC_EnableIRQ(RTC_Seconds_IRQn); #else enable_irq(INT_RTC-16); enable_irq(INT_RTC_Seconds-16); #endif //Configure the TSR and TAR RTC_TSR = 0; //RTC Time Seconds Register RTC_TAR = RTC_TSR + ALARM_TIME; //RTC Time Alarm Register RTC_IER |= RTC_IER_TSIE_MASK | RTC_IER_TAIE_MASK; RTC_SR |= RTC_SR_TCE_MASK; //Enable RTC_SR_TCE }
static inline void set_fll_source(void) { /* Select FLL as source (as opposed to PLL) */ SIM->SOPT2 &= ~(SIM_SOPT2_PLLFLLSEL_MASK); /* Use external 32kHz RTC clock as source for OSC32K */ SIM->SOPT1 = (SIM->SOPT1 & ~(SIM_SOPT1_OSC32KSEL_MASK)) | SIM_SOPT1_OSC32KSEL(2); /* Select RTC 32kHz clock as reference clock for the FLL */ MCG->C7 = (MCG_C7_OSCSEL_MASK); }
void BoardConfig_vfnInit(void) { /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=3 */ SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ /* Switch to FBE Mode */ /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK); /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0_CR = OSC_CR_ERCLKEN_MASK; /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); /* MCG_C4: DMX32=0,DRST_DRS=0 */ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ MCG_C5 = MCG_C5_PRDIV0(0x03); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG_C6 = MCG_C6_VDIV0(0x00); while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to PBE Mode */ /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00)); while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ } SIM_SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK; GPIO_vfnPinMux(GPIO_PORT_C,10,GPIO_MUX_ALT_1); GPIO_vfnPinMux(GPIO_PORT_C,11,GPIO_MUX_ALT_1); GPIO_vfnPinMux(GPIO_PORT_C,12,GPIO_MUX_ALT_1); GPIO_vfnPinMux(GPIO_PORT_C,13,GPIO_MUX_ALT_1); GPIO_vfnPinMux(GPIO_PORT_D,7,GPIO_MUX_ALT_1); GPIO_vfnPinMux(GPIO_PORT_D,6,GPIO_MUX_ALT_1); GPIO_vfnPinMux(GPIO_PORT_B,19,GPIO_MUX_ALT_1); GPIOC_PDDR |= (1<<10) | (1<<11) | (1<<12) | (1<<13); GPIOD_PDDR |= (1<<7) | (1<<6); GPIOB_PDDR |= (1<<19); }
void Clock_init(void) { // Init system clock /* System clock initialization */ /* SIM_SCGC5: PORTA=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */ /* SIM_SOPT2: PLLFLLSEL=0 */ SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ /* SIM_SOPT2: TPMSRC=1 */ SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)( SIM_SOPT2_TPMSRC(0x02) )) | (uint32_t)( SIM_SOPT2_TPMSRC(0x01) )); /* Set the TPM clock */ /* PORTA_PCR18: ISF=0,MUX=0 */ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* PORTA_PCR19: ISF=0,MUX=0 */ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* MCG_SC: FCRDIV=1 */ MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)( MCG_SC_FCRDIV(0x06) )) | (uint8_t)( MCG_SC_FCRDIV(0x01) )); /* Switch to FEE Mode */ /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=1 */ MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK | MCG_C2_IRCS_MASK); /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0_CR = OSC_CR_ERCLKEN_MASK; /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); /* MCG_C4: DMX32=0,DRST_DRS=1 */ MCG_C4 = (uint8_t)((MCG_C4 & (uint8_t)~(uint8_t)( MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x02) )) | (uint8_t)( MCG_C4_DRST_DRS(0x01) )); /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ MCG_C5 = MCG_C5_PRDIV0(0x00); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG_C6 = MCG_C6_VDIV0(0x00); while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG_S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ } /*** End of PE initialization code after reset ***/ }
void Lptmr_Init(int count, int clock_source) { _mqx_uint mqx_ret; SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; SIM_SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK; SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(2); // ERCLK32 is RTC OSC CLOCK PORTC_PCR1 &= ~PORT_PCR_MUX_MASK; PORTC_PCR1 |= PORT_PCR_MUX(1);//enable ptc1 alt1 functions to select RTC_CLKIN function /********************************************************************************* * On L2K tower board, we use external 32kHz clock instead of 32kHz crystal, so please * don't enable the 32kHz crystal oscillator **********************************************************************************/ /* RTC_CR |= RTC_CR_OSCE_MASK | RTC_CR_CLKO_MASK | RTC_CR_SC8P_MASK ; */ LPTMR0_PSR &= ~LPTMR_PSR_PRESCALE_MASK; LPTMR0_PSR |= LPTMR_PSR_PRESCALE(0); // 0000 is div 2 LPTMR0_PSR |= LPTMR_PSR_PBYP_MASK; // LPO feeds directly to LPT LPTMR0_PSR &= ~LPTMR_PSR_PCS_MASK; LPTMR0_PSR |= LPTMR_PSR_PCS(clock_source); // use the choice of clock if (clock_source== 0) APP_TRACE("\n LPTMR Clock source is the MCGIRCLK \n\r"); if (clock_source== 1) APP_TRACE("\n LPTMR Clock source is the LPOCLK \n\r"); if (clock_source== 2) APP_TRACE("\n LPTMR Clock source is the ERCLK32 \n\r"); if (clock_source== 3) APP_TRACE("\n LPTMR Clock source is the OSCERCLK \n\r"); LPTMR0_CMR = LPTMR_CMR_COMPARE(count); //Set compare value LPTMR0_CSR |=( LPTMR_CSR_TCF_MASK // Clear any pending interrupt | LPTMR_CSR_TIE_MASK // LPT interrupt enabled |!LPTMR_CSR_TPP_MASK //TMR Pin polarity |!LPTMR_CSR_TFC_MASK // Timer Free running counter is reset whenever TMR counter equals compare |!LPTMR_CSR_TMS_MASK //LPTMR0 as Timer ); enable_irq(28) ; _int_install_isr(LDD_ivIndex_INT_LPTimer, lptmr_isr, NULL); mqx_ret = _lwsem_create(&g_lptmr_int_sem, 0); ASSERT_PARAM(MQX_OK == mqx_ret); // // ready for this interrupt. // set_irq_priority(28, 2); }
/** **=========================================================================== ** Reset handler **=========================================================================== */ void __init_hardware(void) { /* This is a cleaned up output of Processor Expert generated code */ /* Set the interrupt vector table position */ SCB_VTOR = (uint32_t)__vector_table; #if 0 /* Disable the WDOG module */ SIM_COPC = SIM_COPC_COPT(0x00); #endif /* System clock initialization */ /* Enable clock gate for ports to enable pin routing */ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Update system prescalers */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01); /* Select FLL as a clock source for various peripherals */ SIM_SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* Set the TPM clock */ SIM_SOPT2 &= ~SIM_SOPT2_TPMSRC(0x01); SIM_SOPT2 |= SIM_SOPT2_TPMSRC(0x02); /* Enable XTAL IO pins */ PORTA_PCR18 = PORT_PCR_MUX(0); PORTA_PCR19 = PORT_PCR_MUX(0); /* Switch to FBE Mode */ MCG_C2 = MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK; OSC0_CR = OSC_CR_ERCLKEN_MASK; MCG_C1 = MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK; MCG_C4 &= ~MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03); MCG_C5 = MCG_C5_PRDIV0(0x03); MCG_C6 = MCG_C6_VDIV0(0x00); /* Check that the source of the FLL reference clock is the external reference clock. */ while((MCG_S & MCG_S_IREFST_MASK) != 0x00U); /* Wait until external reference clock is selected as MCG output */ while((MCG_S & 0x0CU) != 0x08U); /* Switch to PBE Mode */ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00)); /* Wait until external reference clock is selected as MCG output */ while((MCG_S & 0x0CU) != 0x08U); /* Wait until locked */ while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U); /* Switch to PEE Mode */ MCG_C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK; /* Wait until output of the PLL is selected */ while((MCG_S & 0x0CU) != 0x0CU); }
void rtc_init(void) { rtc_hal_init_config_t hal_config = {0}; hal_config.disableClockOutToPeripheral = true; if (PinMap_RTC[0].pin == NC) { hal_config.enable32kOscillator = true; } clock_manager_set_gate(kClockModuleRTC, 0U, true); hal_config.startSecondsCounterAt = 1; /* TSR = 1 */ rtc_hal_init(&hal_config); // select RTC clock source SIM->SOPT1 &= ~SIM_SOPT1_OSC32KSEL_MASK; SIM->SOPT1 |= SIM_SOPT1_OSC32KSEL(PinMap_RTC[0].peripheral); rtc_hal_config_oscillator(true); rtc_hal_counter_enable(true); }
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */ void __init_hardware(void) { /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/ /*** ### MK22FX512VLQ12 "Cpu" init code ... ***/ /*** PE initialization code after reset ***/ SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */ /* Disable the WDOG module */ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ /* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK | WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U; /* System clock initialization */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x03) | SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */ /* SIM_SCGC5: PORTE=1,PORTD=1,PORTB=1,PORTA=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ /* SIM_SCGC5: LPTMR=1 */ SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) { /* PMC_REGSC: ACKISO=1 */ PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */ } /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=3 */ SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ /* PORTA_PCR18: ISF=0,MUX=0 */ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* PORTA_PCR19: ISF=0,MUX=0 */ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* Switch to FBE Mode */ /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK); /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC_CR = OSC_CR_ERCLKEN_MASK; /* MCG_C7: OSCSEL=0 */ MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); /* MCG_C4: DMX32=0,DRST_DRS=0 */ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */ MCG_C5 = MCG_C5_PRDIV0(0x01); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=6 */ MCG_C6 = MCG_C6_VDIV0(0x06); while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ } while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to PBE Mode */ /* MCG_C1: CLKS=2,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK); /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x06)); while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ } /* Switch to PEE Mode */ /* MCG_C1: CLKS=0,FRDIV=4,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x04) | MCG_C1_IRCLKEN_MASK); while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ } /*** End of PE initialization code after reset ***/ /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/ }
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */ void __init_hardware(void) { /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/ /*** ### MKL46Z256VMC4 "Cpu" init code ... ***/ /*** PE initialization code after reset ***/ SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */ /* Disable the WDOG module */ /* SIM_COPC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COPT=0,COPCLKS=0,COPW=0 */ SIM_COPC = SIM_COPC_COPT(0x00); /* System clock initialization */ /* SIM_SCGC5: PORTE=1,PORTC=1,PORTB=1,PORTA=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */ /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=2 */ SIM_SOPT1 = (uint32_t)((SIM_SOPT1 & (uint32_t)~(uint32_t)( SIM_SOPT1_OSC32KSEL(0x01) )) | (uint32_t)( SIM_SOPT1_OSC32KSEL(0x02) )); /* System oscillator drives 32 kHz clock for various peripherals */ /* SIM_SOPT2: TPMSRC=1 */ SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)( SIM_SOPT2_TPMSRC(0x02) )) | (uint32_t)( SIM_SOPT2_TPMSRC(0x01) )); /* Set the TPM clock */ /* PORTA_PCR18: ISF=0,MUX=0 */ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* PORTA_PCR19: ISF=0,MUX=0 */ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* Switch to FBE Mode */ /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)( MCG_C2_LOCRE0_MASK | MCG_C2_RANGE0(0x01) | MCG_C2_HGO0_MASK | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK )) | (uint8_t)( MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK )); /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0_CR = OSC_CR_ERCLKEN_MASK; /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); /* MCG_C4: DMX32=0,DRST_DRS=0 */ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ MCG_C5 = MCG_C5_PRDIV0(0x03); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG_C6 = MCG_C6_VDIV0(0x00); while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to PBE Mode */ /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00)); while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ } /* Switch to PEE Mode */ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ } /* Initialization of the RTC_CLKIN pin */ /* PORTC_PCR1: ISF=0,MUX=1 */ PORTC_PCR1 = (uint32_t)((PORTC_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x06) )) | (uint32_t)( PORT_PCR_MUX(0x01) )); /*** End of PE initialization code after reset ***/ /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/ }
void __pe_initialize_hardware(void) { /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/ /*** ### MK21FN1M0VMC12 "Cpu" init code ... ***/ /*** PE initialization code after reset ***/ /* Disable the WDOG module */ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */ /* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */ WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */ /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) | WDOG_STCTRLH_WAITEN_MASK | WDOG_STCTRLH_STOPEN_MASK | WDOG_STCTRLH_ALLOWUPDATE_MASK | WDOG_STCTRLH_CLKSRC_MASK | 0x0100U; #if MQX_ENABLE_LOW_POWER /* Reset from LLWU wake up source */ if (_lpm_get_reset_source() == MQX_RESET_SOURCE_LLWU) { PMC_REGSC |= PMC_REGSC_ACKISO_MASK; } #endif /* SIM_SCGC6: RTC=1 */ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */ /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ RTC_CR &= (uint32_t)~(uint32_t)( RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK ); /* RTC_CR: OSCE=1 */ RTC_CR |= RTC_CR_OSCE_MASK; /* RTC_CR: CLKO=0 */ RTC_CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK); } /* System clock initialization */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x03) | SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */ /* SIM_SCGC5: PORTD=1,PORTC=1,PORTA=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x02) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */ SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */ /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ /* PORTA_PCR18: ISF=0,MUX=0 */ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* PORTA_PCR19: ISF=0,MUX=0 */ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* Switch to FBE Mode */ /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK); /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=1,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC_CR = (OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK); /* MCG_C7: OSCSEL=0 */ MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK); /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03)); /* MCG_C4: DMX32=0,DRST_DRS=0 */ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */ MCG_C5 = MCG_C5_PRDIV0(0x01); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=6 */ MCG_C6 = MCG_C6_VDIV0(0x06); while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */ } while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to PBE Mode */ /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x06)); while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ } /* Switch to PEE Mode */ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03)); while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ } /*** End of PE initialization code after reset ***/ /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/ }
/* ===================================================================*/ LDD_TError Cpu_SetClockConfiguration(LDD_TClockConfiguration ModeID) { if (ModeID > 0x02U) { return ERR_RANGE; /* Undefined clock configuration requested requested */ } switch (ModeID) { case CPU_CLOCK_CONFIG_0: if (ClockConfigurationID == 2U) { /* Clock configuration 0 and clock configuration 2 use different clock configuration */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ Cpu_SetMCG(0U); /* Update clock source setting */ } /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x02) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */ SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */ /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; case CPU_CLOCK_CONFIG_1: if (ClockConfigurationID == 2U) { /* Clock configuration 1 and clock configuration 2 use different clock configuration */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ Cpu_SetMCG(0U); /* Update clock source setting */ } /* SIM_CLKDIV1: OUTDIV1=9,OUTDIV2=9,OUTDIV3=9,OUTDIV4=9,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x09) | SIM_CLKDIV1_OUTDIV2(0x09) | SIM_CLKDIV1_OUTDIV3(0x09) | SIM_CLKDIV1_OUTDIV4(0x09); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */ SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */ /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; case CPU_CLOCK_CONFIG_2: /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ if ((MCG_C2 & MCG_C2_IRCS_MASK) == 0x00U) { /* MCG_SC: FCRDIV=1 */ MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)( MCG_SC_FCRDIV(0x06) )) | (uint8_t)( MCG_SC_FCRDIV(0x01) )); } else { /* MCG_C2: IRCS=0 */ MCG_C2 &= (uint8_t)~(uint8_t)(MCG_C2_IRCS_MASK); while((MCG_S & MCG_S_IRCST_MASK) != 0x00U) { /* Check that the source internal reference clock is slow clock. */ } /* MCG_SC: FCRDIV=1 */ MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)( MCG_SC_FCRDIV(0x06) )) | (uint8_t)( MCG_SC_FCRDIV(0x01) )); /* MCG_C2: IRCS=1 */ MCG_C2 |= MCG_C2_IRCS_MASK; while((MCG_S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the source internal reference clock is fast clock. */ } } Cpu_SetMCG(1U); /* Update clock source setting */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x00) | SIM_CLKDIV1_OUTDIV3(0x00) | SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */ SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */ /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; default: break; } LDD_SetClockConfiguration(ModeID); /* Call all LDD components to update the clock configuration */ ClockConfigurationID = ModeID; /* Store clock configuration identifier */ return ERR_OK; }
/* ** =================================================================== ** Method : Cpu_SetClockConfiguration (component MK22FN512VDC12) ** ** Description : ** Calling of this method will cause the clock configuration ** change and reconfiguration of all components according to ** the requested clock configuration setting. ** Parameters : ** NAME - DESCRIPTION ** ModeID - Clock configuration identifier ** Returns : ** --- - ERR_OK - OK. ** ERR_RANGE - Mode parameter out of range ** =================================================================== */ LDD_TError Cpu_SetClockConfiguration(LDD_TClockConfiguration ModeID) { if (ModeID > 0x03U) { return ERR_RANGE; /* Undefined clock configuration requested requested */ } if (0x03U == ClockConfigurationID) { if ((CPU_CLOCK_CONFIG_1 == ModeID) || ( CPU_CLOCK_CONFIG_2 == ModeID)) return ERR_FAILED; Cpu_SetMCGClockInModePEE(ModeID); } if (0x03U == ModeID) { if ((CPU_CLOCK_CONFIG_1 == ClockConfigurationID) || ( CPU_CLOCK_CONFIG_2 == ClockConfigurationID)) return ERR_FAILED; Cpu_SetMCGClockInModePEE(ModeID); } switch (ModeID) { case CPU_CLOCK_CONFIG_0: if (ClockConfigurationID == 2U) { /* Clock configuration 0 and clock configuration 2 use different clock configuration */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,*/ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ Cpu_SetMCG(0U); /* Update clock source setting */ } /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x03) | SIM_CLKDIV1_OUTDIV4(0x02); /* Update system prescalers */ #if (BSPCFG_USB_CLK_FROM_IRC48M) SIM_CLKDIV2 = 0; SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x03); SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK); /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* Update USB clock prescalers */ /* SIM_SOPT2: PLLFLLSEL=0x01 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ #endif SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; case CPU_CLOCK_CONFIG_1: if (ClockConfigurationID == 2U) { /* Clock configuration 1 and clock configuration 2 use different clock configuration */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ Cpu_SetMCG(0U); /* Update clock source setting */ } /* SIM_CLKDIV1: OUTDIV1=9,OUTDIV2=9,OUTDIV3=9,OUTDIV4=9,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x09) | SIM_CLKDIV1_OUTDIV2(0x09) | SIM_CLKDIV1_OUTDIV3(0x09) | SIM_CLKDIV1_OUTDIV4(0x09); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* SIM_SOPT2: PLLFLLSEL=0x01 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; case CPU_CLOCK_CONFIG_2: /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??*/ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Set the system prescalers to safe value */ if ((MCG_C2 & MCG_C2_IRCS_MASK) == 0x00U) { /* MCG_SC: FCRDIV=1 */ MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)( MCG_SC_FCRDIV(0x06) )) | (uint8_t)( MCG_SC_FCRDIV(0x01) )); } else { /* MCG_C2: IRCS=0 */ MCG_C2 &= (uint8_t)~(uint8_t)(MCG_C2_IRCS_MASK); while((MCG_S & MCG_S_IRCST_MASK) != 0x00U) { /* Check that the source internal reference clock is slow clock. */ } /* MCG_SC: FCRDIV=1 */ MCG_SC = (uint8_t)((MCG_SC & (uint8_t)~(uint8_t)( MCG_SC_FCRDIV(0x06) )) | (uint8_t)( MCG_SC_FCRDIV(0x01) )); /* MCG_C2: IRCS=1 */ MCG_C2 |= MCG_C2_IRCS_MASK; while((MCG_S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the source internal reference clock is fast clock. */ } } Cpu_SetMCG(1U); /* Update clock source setting */ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x00) | SIM_CLKDIV1_OUTDIV3(0x00) | SIM_CLKDIV1_OUTDIV4(0x03); /* Update system prescalers */ /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; case CPU_CLOCK_CONFIG_3: /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=4,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV2(0x01) | SIM_CLKDIV1_OUTDIV3(0x04) | SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */ #if (BSPCFG_USB_CLK_FROM_IRC48M) SIM_CLKDIV2 = 0; SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x03); SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK); /* Enable IRC 48MHz for USB module */ USB_CLK_RECOVER_IRC_EN = 0x03; #else /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */ SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0x4) | SIM_CLKDIV2_USBFRAC_MASK; /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL(0x01); /* Select PLL as a clock source for various peripherals */ #endif /* SIM_SOPT1: OSC32KSEL=0 */ SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */ break; default: break; } LDD_SetClockConfiguration(ModeID); /* Call all LDD components to update the clock configuration */ ClockConfigurationID = ModeID; /* Store clock configuration identifier */ return ERR_OK; }
void Boot_Init_Clock(void){ /* System clock initialization */ /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescalers to safe value */ /* SIM_SCGC5: PORTA=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) { /* PMC_REGSC: ACKISO=1 */ PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */ } /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */ /* SIM_SOPT2: PLLFLLSEL=1 */ SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */ /* SIM_SOPT1: OSC32KSEL=3 */ SIM_SOPT1 |= SIM_SOPT1_OSC32KSEL(0x03); /* LPO 1kHz oscillator drives 32 kHz clock for various peripherals */ /* SIM_SOPT2: TPMSRC=1 */ SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)( SIM_SOPT2_TPMSRC(0x02) )) | (uint32_t)( SIM_SOPT2_TPMSRC(0x01) )); /* Set the TPM clock */ /* PORTA_PCR18: ISF=0,MUX=0 */ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* PORTA_PCR19: ISF=0,MUX=0 */ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); /* Switch to FBE Mode */ /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)( MCG_C2_LOCRE0_MASK | MCG_C2_RANGE0(0x01) | MCG_C2_HGO0_MASK | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK )) | (uint8_t)( MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK )); /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0_CR = OSC_CR_ERCLKEN_MASK; /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); /* MCG_C4: DMX32=0,DRST_DRS=0 */ MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03))); /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */ MCG_C5 = MCG_C5_PRDIV0(0x03); /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ MCG_C6 = MCG_C6_VDIV0(0x00); while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ } while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } /* Switch to PBE Mode */ /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x00)); while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ } while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ } /* Switch to PEE Mode */ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03) | MCG_C1_IRCLKEN_MASK); while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ } /* MCG_C6: CME0=1 */ MCG_C6 |= MCG_C6_CME0_MASK; /* Enable the clock monitor */ /*** End of PE initialization code after reset ***/ }
void rtc_init(uint32 seconds, uint32 alarm, uint8 c_interval, uint8 c_value, uint8 interrupt) { int i; /*enable the clock to SRTC module register space*/ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK; SIM_SOPT1 = SIM_SOPT1_OSC32KSEL(0); /*Only VBAT_POR has an effect on the SRTC, RESET to the part does not, so you must manually reset the SRTC to make sure everything is in a known state*/ /*clear the software reset bit*/ // printf("Generating SoftWare reset to SRTC\n"); disable_irq(interrupt); disable_irq(interrupt+1); RTC_CR = RTC_CR_SWR_MASK; RTC_CR &= ~RTC_CR_SWR_MASK; if (RTC_SR & RTC_SR_TIF_MASK) { RTC_TSR = 0x00000000; // this action clears the TIF // printf("RTC Invalid flag was set - Write to TSR done to clears RTC_SR = %#02X \n", (RTC_SR) ) ; } /*Set time compensation parameters*/ RTC_TCR = RTC_TCR_CIR(c_interval) | RTC_TCR_TCR(c_value); /*Enable the counter*/ if (seconds >0) { /*Enable the interrupt*/ if(interrupt >1) { enable_irq(interrupt+1); } RTC_IER |= RTC_IER_TSIE_MASK; RTC_SR |= RTC_SR_TCE_MASK; /*Configure the timer seconds and alarm registers*/ RTC_TSR = seconds; } else { RTC_IER &= ~RTC_IER_TSIE_MASK; } if (alarm >0) { RTC_IER |= RTC_IER_TAIE_MASK; RTC_SR |= RTC_SR_TCE_MASK; /*Configure the timer seconds and alarm registers*/ RTC_TAR = alarm; /*Enable the interrupt*/ if(interrupt >1) { enable_irq(interrupt); } } else { RTC_IER &= ~RTC_IER_TAIE_MASK; } /*Enable the oscillator*/ RTC_CR |= RTC_CR_OSCE_MASK|RTC_CR_SC16P_MASK; /*Wait to all the 32 kHz to stabilize, refer to the crystal startup time in the crystal datasheet*/ for(i=0;i<0x600000;i++); RTC_SR |= RTC_SR_TCE_MASK; //rtc_reg_report(); }