void Uart0_init(uint32_t baud) // confirm uart0
{
uint32_t clk =48000000; //CLock source
uint16_t temp = 0; //Save SBR
uint8_t BDL; //save UART0_BDL
uint8_t BDH; //save UART0_BDH
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; // Set clock PORTA
SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; // MCGFLLCLK is selected for UART0 clock source
SIM->SOPT2 |= SIM_SOPT2_UART0SRC(1);
/* Enable the UART_TXD function on PTA1 */
PORTA->PCR[1] = PORT_PCR_MUX(0x2);
/* Enable the UART_TXD function on PTA2 */
PORTA->PCR[2] = PORT_PCR_MUX(0x2);
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; // enable UART0 Clock
UART0->C4 = 0x0F; // UART0_C4[OSR]= 0x0F => ratio 16x
temp = clk/(baud*16); // SBR
BDH = temp>>8; //5 bit High SBR
BDL = temp & 0x00ff; //8 bit LOW SBR
UART0->BDH = BDH;
UART0->BDL = BDL;
UART0->C1 = 0x00; //Default control uart
UART0->C5|= UART0_C5_BOTHEDGE_MASK; //Both Edge Sampling
/* enable UART Transmitter and Receiver */
UART0->C2 |= UART0_C2_RIE_MASK;
UART0->C2 |= (UART0_C2_TE_MASK | UART0_C2_RE_MASK );
NVIC_EnableIRQ(UART0_IRQn);
}
static void SetSIMRegisters()
{
// TODO
SIM->COPC = SIM_COPC_COPT(0);//disable watchdog immediately
//do the rest in order listed in data sheet
SIM->SOPT2 = SIM_SOPT2_UART0SRC(0)|SIM_SOPT2_TPMSRC(0);//no clocks enabled for
// uart0 or TPM counterClock
SIM->SOPT4 = ((0 << SIM_SOPT4_TPM1CLKSEL_SHIFT)&SIM_SOPT4_TPM1CLKSEL_MASK)|((0 << SIM_SOPT4_TPM0CLKSEL_SHIFT)&SIM_SOPT4_TPM0CLKSEL_MASK)|((0<<SIM_SOPT4_TPM1CH0SRC_SHIFT)&SIM_SOPT4_TPM1CH0SRC_MASK);//don't care settings
SIM->SOPT5 = ((0<<SIM_SOPT5_UART0ODE_SHIFT)&SIM_SOPT5_UART0ODE_MASK)|((0<<SIM_SOPT5_UART0RXSRC_SHIFT)&SIM_SOPT5_UART0RXSRC_MASK)|((0<<SIM_SOPT5_UART0TXSRC_SHIFT)&SIM_SOPT5_UART0TXSRC_MASK);//don't cares
SIM->SOPT7 = ((0<<SIM_SOPT7_ADC0ALTTRGEN_SHIFT)&SIM_SOPT7_ADC0ALTTRGEN_MASK)|((0<<SIM_SOPT7_ADC0PRETRGSEL_SHIFT)&SIM_SOPT7_ADC0PRETRGSEL_MASK)|((0<<SIM_SOPT7_ADC0TRGSEL_SHIFT)&SIM_SOPT7_ADC0TRGSEL_MASK);//don't cares
SIM->SCGC4 = ((1<<SIM_SCGC4_SPI0_SHIFT)&SIM_SCGC4_SPI0_MASK)|((0<<SIM_SCGC4_CMP_SHIFT)&SIM_SCGC4_CMP_MASK)|((0<<SIM_SCGC4_UART0_SHIFT)&SIM_SCGC4_UART0_MASK)|((1<<SIM_SCGC4_I2C1_SHIFT)&SIM_SCGC4_I2C1_MASK)|((1<<SIM_SCGC4_I2C0_SHIFT)&SIM_SCGC4_I2C0_MASK);//enable the I2C module
SIM->SCGC5 = ((1<<SIM_SCGC5_PORTB_SHIFT)&SIM_SCGC5_PORTB_MASK)|((1<<SIM_SCGC5_PORTA_SHIFT)&SIM_SCGC5_PORTA_MASK)|((0<<SIM_SCGC5_LPTMR_SHIFT)&SIM_SCGC5_LPTMR_MASK);//enable both ports
SIM->SCGC6 = ((0<<SIM_SCGC6_ADC0_SHIFT)&SIM_SCGC6_ADC0_MASK)|((0<<SIM_SCGC6_TPM1_SHIFT)&SIM_SCGC6_TPM1_MASK)|((0<<SIM_SCGC6_TPM0_SHIFT)&SIM_SCGC6_TPM0_MASK)|((0<<SIM_SCGC6_FTF_SHIFT)&SIM_SCGC6_FTF_MASK);//don't cares
SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0)|SIM_CLKDIV1_OUTDIV4(4);//clk configured for 4MHz core, .8 MHz Bus Clk (fastest allowable in BLPI mode)
//this is unchanged from default, do not alter. If we need to save power we can turn off flash, but this has caused hard faults. we need to move the interrupt vectors out of flash to do this SIM_FCFG1 = ((0<<SIM_FCFG1_FLASHDOZE_SHIFT)&SIM_FCFG1_FLASHDOZE_MASK)|((0<<SIM_FCFG1_FLASHDIS_SHIFT)&SIM_FCFG1_FLASHDIS_MASK);//flash disabled to conserve power, other settings are don't cares, TODO:verify flash size setting is unimportant
//SIM_FCFG2 = SIM_FCFG2 only has maxaddr0, which is read only.
//SIM_SRVCOP, we do not need to reset timer, it is disabled already.
return;
}
void Configure_UART()
{
SIM->SOPT2 |= SIM_SOPT2_UART0SRC(UART_OSC_CLOCK); // UART use OSC Clock (24 MHz? - using SystemInit to give us this)
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; // Enable clock gate for UART0
//This is 38400 Baud - Works! :)
//UART0->C4 = 12; // Over sample rate (OSC)
//UART0->BDL = 16; // Modulo - 24MHz / (115200 * (OSC + 1)) where OSC = 12
//C4 = 14 and BDL = 5 displayed 'A' on the terminal! :)
//WORKS WITH 115200!!
//UART0->BDL = 5;
//UART0->C4 = 14;
UART0->BDL = UART_115200_MOD;
UART0->C4 = UART_115200_OSC;
UART0->C2 = UART_C2_TE_MASK | UART_C2_RE_MASK; //Enable TX and RX
//Need to configure PTA1 & PTA2 as alt2 (UART0_RX, UART0_TX)
PORTA->PCR[1] |= PORT_PCR_MUX(2);
PORTA->PCR[2] |= PORT_PCR_MUX(2);
}
void vfnUART_Config(void)
{
SIM_SOPT2 |= SIM_SOPT2_UART0SRC(1);
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
UART0_BDL = UART0_BDL_SBR(137);
UART0_C2 = UART0_C2_TE_MASK;
PORTA_PCR1= PORT_PCR_MUX(2) | PORT_PCR_PE_MASK;
PORTA_PCR2= PORT_PCR_MUX(2) | PORT_PCR_PE_MASK;
}
void uart_init(void) {
/* Supply the clock for UART0 and PORTA */
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK;
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* Set PORTA1 as Rx and PORTA2 as Tx */
PORTA->PCR[1] &= ~PORT_PCR_MUX_MASK; // Make sure that MUX is clear
PORTA->PCR[1] |= PORT_PCR_MUX(2);
PORTA->PCR[2] &= ~PORT_PCR_MUX_MASK; // Make sure that MUX is clear
PORTA->PCR[2] |= PORT_PCR_MUX(2);
/* Choose external 8MHz crystal as a reference clock for UART0 */
/* Asynch Module Clock = 8 MHz */
SIM->SOPT2 |= SIM_SOPT2_UART0SRC(2);
/* Disable the reciever and transmitter of UART0 */
UART0->C2 &= ~(UART0_C2_TE_MASK | UART0_C2_RE_MASK); // turn off the Tx and Rx
/* Set the oversampling ratio to 4 */
UART0->C4 = UART0_C4_OSR(3);
/* Set SBr to 139 in order to achieve Baud Rate euqal to 14400 */
UART0->BDH |= UART0_BDH_SBR(0);
UART0->BDL &= ~UART0_BDL_SBR_MASK; // clear BDL first
UART0->BDL |= UART0_BDL_SBR(139);
/* Set 1 Stop Bit */
UART0->BDH &= ~UART0_BDH_SBNS_MASK;
/* Choose 8-bits long data */
UART0->C1 &= ~UART0_C1_M_MASK;
/* Disable hardware parity check */
UART0->C1 &= ~UART0_C1_PE_MASK;
/* Initialize the queues for the interrupts-driven serial communication */
q_init(&TxQ);
q_init(&RxQ);
/* Configure the interrupts from the UART0 */
NVIC_ClearPendingIRQ(UART0_IRQn);
NVIC_EnableIRQ(UART0_IRQn);
/* Enable the interrupt when receiver buffer gets full */
UART0->C2 |= UART0_C2_RIE_MASK;
/* Turn on the receiver and transmitter */
UART0->C2 |= UART0_C2_TE_MASK | UART0_C2_RE_MASK; // turn on the Tx and Rx
}
void UARTinit()
{
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;
/* PORTA_PCR1: ISF=0,MUX=2 */
PORTA_PCR1 |= (PORT_PCR_MUX(2));
/* PORTA_PCR2: ISF=0,MUX=2 */
PORTA_PCR2 |= (PORT_PCR_MUX(2));
/* Disable TX & RX while we configure settings */
UART0_C2 &= ~(UART0_C2_TE_MASK); //disable transmitter
UART0_C2 &= ~(UART0_C2_RE_MASK); //disable receiver
/* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
UART0_C1 = 0x00U; /* Set the C1 register */
/* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
UART0_C3 = 0x00U; /* Set the C3 register */
/* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
UART0_S2 = 0x00U; /* Set the S2 register */
SIM_SOPT2 |= SIM_SOPT2_UART0SRC(1); //set clock source to be from PLL/FLL
SIM_SOPT2 |= SIM_SOPT2_CLKOUTSEL(0b100);
unsigned SBR = 546;//137; //Set the baud rate register, SBR = 137
UART0_BDH |= (~UART0_BDH_SBR_MASK) | SBR >> 8;
UART0_BDL |= (~UART0_BDL_SBR_MASK) | SBR;
char OSR = 3; //set the oversampling ratio to option #3 = 4x
UART0_C4 &= (~UART0_C4_OSR_MASK) | OSR;
/*
* Target Baud rate = 38400 9600
*
* Baud rate = baud clock / ((OSR+1) * SBR)
* baud clock = FLL/PLL = 20.97152MHz 32kHZ
* OSR = 3
* SBR = 137 //546
* Resulting Baud rate = 20.97152MHz / ((3 + 1) * 546) = 9600
*/
UART0_C5 |= UART0_C5_BOTHEDGE_MASK; //enable sampling on both edges of the clock
UART0_C2 |= UART0_C2_TE_MASK; //enable transmitter
UART0_C2 |= UART0_C2_RE_MASK; //enable receiver
}
uint8_t UART_QuickInit(uint32_t MAP, uint32_t baudrate)
{
uint8_t i;
uint32_t clock;
UART_InitTypeDef UART_InitStruct1;
QuickInit_Type * pq = (QuickInit_Type*)&(MAP);
UART_InitStruct1.baudrate = baudrate;
UART_InitStruct1.instance = pq->ip_instance;
/* clock source */
if(pq->ip_instance == HW_UART0)
{
CLOCK_GetClockFrequency(kMCGOutClock, &clock);
/* use PLL/2 or FLL */
SIM->SOPT2 &= ~SIM_SOPT2_UART0SRC_MASK;
SIM->SOPT2 |= SIM_SOPT2_UART0SRC(1);
if(MCG->C6 & MCG_C6_PLLS_MASK) /* PLL */
{
SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;
clock /= 2;
}
else /* FLL */
{
SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
}
}
else
{
CLOCK_GetClockFrequency(kBusClock, &clock);
}
UART_InitStruct1.srcClock = clock;
/* init pinmux */
for(i = 0; i < pq->io_offset; i++)
{
PORT_PinMuxConfig(pq->io_instance, pq->io_base + i, (PORT_PinMux_Type) pq->mux);
}
/* init UART */
UART_Init(&UART_InitStruct1);
return pq->ip_instance;
}
/**
*****************************************************************************
* \fn UART_init
* \brief Configure a UART to the specific baud rate and 8n1.
*
* \param [in] UARTx The UART port which will be used. Possible values are
* UART0, UART1 and UART2.
* \param [in] Baud Selected baud rate in Hz.
* \return None
*****************************************************************************
*/
void UART_init(void *UARTx, uint32_t Baud) {
uint16_t tmp;
if ((UARTLP_Type *) UARTx == UART0) {
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable GPIOA clock */
SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; /* Enable UART0 clock */
/* Configure the GPIOs */
UART_Port_Pin[0].PORTx->PCR[UART_Port_Pin[0].Bit] =
UART_Port_Pin[0].Alt;
UART_Port_Pin[1].PORTx->PCR[UART_Port_Pin[1].Bit] =
UART_Port_Pin[1].Alt;
/**
* Configuration register C1:
* - Nothing
* Configuration register C2:
* - Enable transmitter
* - Enable receiver
* Configuration register C3:
* - Nothing
* Configuration register C4:
* - Nothing
* Configuration register C5:
* - Nothing
* Clock source for UART0:
* - MCGFLLCLK
*/
((UARTLP_Type *) UARTx)->C1 = 0x00;
((UARTLP_Type *) UARTx)->C2 = UARTLP_C2_RE_MASK | UARTLP_C2_TE_MASK;
((UARTLP_Type *) UARTx)->C3 = 0x00;
((UARTLP_Type *) UARTx)->C4 = 0x00;
((UARTLP_Type *) UARTx)->C5 = 0x00;
SIM->SOPT2 &= ~(SIM_SOPT2_PLLFLLSEL_MASK); /* MCGFLLCLK */
SIM->SOPT2 |= SIM_SOPT2_UART0SRC(1); /* Using MCGFLLPLL */
tmp = SystemCoreClock / Baud;
((UARTLP_Type *) UARTx)->BDH &= ~UARTLP_BDH_SBR_MASK;
((UARTLP_Type *) UARTx)->BDH |= UARTLP_BDH_SBR(tmp);
((UARTLP_Type *) UARTx)->BDL &= ~UARTLP_BDL_SBR_MASK;
((UARTLP_Type *) UARTx)->BDL |= UARTLP_BDL_SBR(tmp);
}
}
void DrvUART0_Config(void)
{
uint32_t divisor;
// enable clock
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_SHIFT ;
SIM->SOPT2 |= SIM_SOPT2_UART0SRC(0x01);
PORTA->PCR[1] = PORT_PCR_MUX(0x2);
PORTA->PCR[2] = PORT_PCR_MUX(0x2);
SIM->SCGC4 |= 1UL<<10;
//disabled tx and rx before configuration
UART0->C2 &= ~UART0_C2_TE_MASK ;
UART0->C2 &= ~UART0_C2_RE_MASK ;
// Data bit: 8; Parity: None; Stop bits: 1; Flow Control: None
UART0->C1 = 00U;
UART0->C3 = 00U;
UART0->C4 = UART0_C4_OSR(15);
UART0->S2 = 00U;
UART0->S1 = 00U;
// Set baud rate 115200
divisor = 23;
UART0->BDH = UART0_BDH_SBR(divisor>>8);
UART0->BDL = (uint8_t)(divisor);
// Tx & Rx are enable
UART0->C2 |= UART0_C2_TE_MASK ;
UART0->C2 |= UART0_C2_RE_MASK ;
UART0->C2 |= UART0_C2_RIE_MASK ;
NVIC_EnableIRQ(UART0_IRQn);
NVIC_ClearPendingIRQ(UART0_IRQn);
}
PUBLIC_FCT void UART0_Init (T_ULONG bd_value)
{
const T_ULONG cul_mcg_clk_hz = 24000000; //PLL/2 Source Clock for UART
T_ULONG lul_baud_rate = 0; //Variable to store baud rate
T_ULONG lul_br_value = 0; //Variable to store BD dividers
float lf_br_float = 0; //Auxiliary variable to save the result of division
float lf_residue = 0; //Variable to store the minimum residue
T_UBYTE lub_temp = 4; //Auxiliary Variable
T_UWORD luw_osr_value = 4; //Variable to store OSR dividers
register T_UBYTE lub_i = 0; //Auxiliary Variable
PORTA_PCR1 = PORT_PCR_MUX(2); //Enable the UART_TXD function on PTA1
PORTA_PCR2 = PORT_PCR_MUX(2); //Enable the UART_TXD function on PTA2
SIM_SOPT2 |= SIM_SOPT2_UART0SRC(1); //Select the PLLFLLCLK as UART0 clock source
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; //Enable Clock signal for UART0
UART0_Stop(); //Disable UART0 before changing registers
lul_baud_rate = bd_value; //Store Baud rate desired
/*
* Calculate BR registers depends on Baud Rate = Baud Clock / (BR * (OSR + 1)) according to datasheet
*/
lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (luw_osr_value + 1));
lf_br_float = (float)cul_mcg_clk_hz / ((float)lul_baud_rate * ((float)luw_osr_value + 1));
lf_residue = lf_br_float - (float)lul_br_value;
/*
* Calculate it for all OSR possible values to find the minimum error
*/
for(lub_i = 5; lub_i <= 32; lub_i++)
{
lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (lub_i + 1));
lf_br_float = (float)cul_mcg_clk_hz / ((float)lul_baud_rate * ((float)lub_i + 1));
lf_br_float -= (float)lul_br_value;
if(lf_br_float <= lf_residue) //If a new "minimum error" is found
{
lf_residue = lf_br_float; //Store new minimum error
lub_temp = lub_i; //Store OSR value for this minimum error
}
}
luw_osr_value = lub_temp; //Assign the found OSR value to calculate the minimum error
lul_br_value = cul_mcg_clk_hz / (lul_baud_rate * (luw_osr_value + 1)); //Calculate BR value
UART0_BDH |= UART0_BDH_SBR(((lul_br_value & 0x1F00) >> 8)); //Setting BD dividers
UART0_BDL = (T_UBYTE)(lul_br_value & UART0_BDL_SBR_MASK); //Setting BD dividers
UART0_C4 = UART0_C4_OSR(luw_osr_value); //Setting OSR for Sampling Ratio
if(luw_osr_value < 8) //If Sampling Ratio is less than 8
{
UART0_C5|= UART0_C5_BOTHEDGE_MASK; //Enable both edges of baud clock for receiving data
}
else
{
}
UART0_C1 &=~(UART0_C1_M_MASK | UART0_C1_PE_MASK); //8 Bit for data, No parity Selected
UART0_BDH &= ~(UART0_BDH_SBNS_MASK); //Configure One Stop Bit: 0 One stop bit.
UART0_Start(); //Enable receiver and transmitter
}
/*********************************************************************************************************
** Function name: uart0Init
** Descriptions: UART0µÄ³õʼ»¯
** input parameters: ucBaudRate:²¨ÌØÂÊ£»ucParityEnable:УÑéλѡÔñ£»
** ucParityType:УÑéÀàÐÍ£»ucDataLength:Êý¾Ý³¤¶È£»ucStopBit:ֹͣλ£»
** output parameters: none
** Returned value: none
** Created by:
** Created date:
**--------------------------------------------------------------------------------------------------------
** Modified by:
** Modified date:
*********************************************************************************************************/
void uart0Init (INT32U ulBaudRate,
INT8U ucParityEnable,
INT8U ucParityType,
INT8U ucDataLength,
INT8U ucStopBit)
{
UART0_MemMapPtr uartPtr = UART0_BASE_PTR;
register INT16U usBaudRate = 0;
#if UART_PARAM_DEBUG
UART_CHECK_PARAM(UART_PARAM_LENGTH(ucDataLength));
UART_CHECK_PARAM(UART_PARAM_STOP(ucStopBit));
UART_CHECK_PARAM(UART_PARAM_LOGIC(ucParityEnable));
UART_CHECK_PARAM(UART_PARAM_PARITY(ucParityType));
#endif
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;
SIM_SOPT2 |= SIM_SOPT2_UART0SRC(1); /* Ñ¡ÔñPLLʱÖÓ */
SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; /* ÔÊÐíÍâÉèʱÖÓ */
uart0TranControl(UART_TX_DISABLE, UART_RX_DISABLE); /* Ê×ÏȽûֹͨÐÅ */
#if 1
PORTA_PCR1 = PORT_PCR_MUX(0x2); /* UART0_TXD */
PORTA_PCR2 = PORT_PCR_MUX(0x2); /* UART0_RXD */
#endif
#if 0
PORTA_PCR14 = PORT_PCR_MUX(0x3); /* UART0_TXD */
PORTA_PCR15 = PORT_PCR_MUX(0x3); /* UART0_RXD */
#endif
#if 0
PORTD_PCR7 = PORT_PCR_MUX(0x3); /* UART0_TXD */
PORTD_PCR6 = PORT_PCR_MUX(0x3); /* UART0_RXD */
#endif
#if 0
PORTE_PCR20 = PORT_PCR_MUX(0x4); /* UART0_TXD */
PORTE_PCR21 = PORT_PCR_MUX(0x4); /* UART0_RXD */
#endif
#if 0
PORTE_PCR17 = PORT_PCR_MUX(0x3); /* UART0_TXD */
PORTE_PCR16 = PORT_PCR_MUX(0x3); /* UART0_RXD */
#endif
UART0_C1_REG(uartPtr) &= ~(UART0_C1_M_MASK | /* Êý¾Ý³¤¶È */
UART0_C1_PT_MASK | /* УÑéλÀàÐÍ */
UART0_C1_PE_MASK); /* УÑéλ */
UART0_C4_REG(uartPtr) &= ~UART0_C4_M10_MASK;
if (ucDataLength == 10) {
UART0_C1_REG(uartPtr) |= (ucParityEnable << UART0_C1_PE_SHIFT)|
(ucParityType << UART0_C1_PT_SHIFT);
UART0_C4_REG(uartPtr) |= UART0_C4_M10_MASK;
} else {
UART0_C1_REG(uartPtr) |= ((ucDataLength - 8UL) << UART0_C1_M_SHIFT)|
(ucParityEnable << UART0_C1_PE_SHIFT)|
(ucParityType << UART0_C1_PT_SHIFT);
}
usBaudRate = SystemBusClock/(ulBaudRate * 16);
UART0_BDH_REG(uartPtr) = (usBaudRate & 0x1F00) >> 8; /* ²¨ÌØÂÊ */
UART0_BDL_REG(uartPtr) = (INT8U)(usBaudRate & UART0_BDL_SBR_MASK);
UART0_BDH_REG(uartPtr) &= ~UART0_BDH_SBNS_MASK; /* ֹͣλ */
UART0_BDH_REG(uartPtr) |= (ucStopBit - 1) << UART0_BDH_SBNS_SHIFT;
UART0_C2_REG(uartPtr) &= ~(UART0_C2_TIE_MASK | UART0_C2_TCIE_MASK |
UART0_C2_RIE_MASK | UART0_C2_ILIE_MASK); /* Çå³ýÖжÏÉèÖà */
while ((UART0_S1_REG(uartPtr) & UART0_S1_RDRF_MASK) &&
(UART0_D_REG(uartPtr))); /* Çå½ÓÊÕ»º³åÇø */
#if UART0_DEFAULT_OPEN
uart0TranControl(UART_TX_ENABLE, UART_RX_ENABLE); /* ÅäÖÃÍê³ÉÔÊÐíͨÐÅ */
#endif
#if UART0_IRQ_ENABLE
#if UART0_SEND_IRQ
UART0_C2_REG(uartPtr) |= UART0_C2_TCIE_MASK;
#endif
#if UART0_RECEIVE_IRQ
UART0_C2_REG(uartPtr) |= UART0_C2_RIE_MASK;
#endif
NVIC_EnableIRQ(UART0_IRQn);
NVIC_SetPriority(UART0_IRQn,3); /* Óû§×Ô¼º¶¨Òå */
#endif
}
/*! Sets up the clock for USB operation (out of RESET)
*!
*! MCGOUTCLK = 48MHz
*! core/platform/system clock = PLL (48MHz),
*! bus clock = PLL (48MHz),
*! flash clock = PLL/2 (24MHz)
*!
*! Assumes 8 MHz external crystal
*!
*! Modes: FEI [FLL engaged internal] ->
*! FBE [FLL bypassed external] ->
*! PBE [PLL bypassed external] ->
*! PEE [PLL engaged external]
*!
*! Refer 24.5.3.1 of K20 Family reference
*/
void initClock(void) {
MCG_C7 = 0; // OSCSEL = 0 => Crystal Osc
// Out of reset MCG is in FEI mode
// Configure the Crystal Oscillator
OSC0_CR = OSC_CR_SC16P_MASK;
// 1. Switch from FEI (FLL engaged internal) to FBE (FLL bypassed external)
// 1 a) Set up crystal
MCG_C2 = // oscillator in low power mode (w/o Rf)
MCG_C2_EREFS0_MASK | // because crystal is being used
MCG_C2_RANGE0(1) | // 4 or 8 MHz is in high frequency range
MCG_C2_IRCS_MASK;
// 1 b) Select clock mode
MCG_C1 = MCG_C1_CLKS(2) | // CLKS = 10 -> External reference clock
MCG_C1_FRDIV(FRDIV_VALUE) | // FRDIV = 2,3 -> 8MHz,4MHz/256 = 31.25 kHz
MCG_C1_IRCLKEN_MASK; // IRCLKEN = 1 -> MCGIRCLK active
// Make sure - reset default
MCG_C4 &= ~(MCG_C4_DMX32_MASK|MCG_C4_DRST_DRS_MASK);
// 1 c) Wait for crystal to start up
while ((MCG_S & MCG_S_OSCINIT0_MASK) == 0) {
}
// 1 d) Wait for mode change
while ((MCG_S & MCG_S_IREFST_MASK) != 0) {
}
// 1 e) Wait for MCGOUT indicating that the external reference to be fed to MCGOUT
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) {
}
// 2. Configure PLL Ref. Freq.
// 2 a) Set PRDIV for correct range
MCG_C5 = MCG_C5_PLLCLKEN0_MASK |
MCG_C5_PRDIV0(PRDIV_VALUE); // PRDIV=3,1, PLL Ref Freq. = 8MHz,4MHz/4 => 2 MHz
MCG_C6 = 0;
// 3. FBE => BLPE => PBE
// 3 a) BLPE
MCG_C2 = // oscillator in low power mode (w/o external Rf)
MCG_C2_EREFS0_MASK | // because crystal is being used
MCG_C2_RANGE0(1) | // 4 or 8 MHz is in high frequency range
MCG_C2_IRCS_MASK ;
// 3 b) BLPE/PBE
MCG_C6 = MCG_C6_PLLS_MASK|MCG_C6_VDIV0(0); // 2MHz x 24 = 96MHz
// 3 c) BPE
MCG_C2 = // oscillator in low power mode (w/o Rf)
MCG_C2_EREFS0_MASK | // because crystal is being used
MCG_C2_RANGE0(1) | // 4 or 8 MHz is in high frequency range
MCG_C2_IRCS_MASK;
// 3 d) Wait until PLLS clock source changes to the PLL
while((MCG_S & MCG_S_PLLST_MASK) == 0) {
}
// 3 e) Wait for PLL to acquired lock
while((MCG_S & MCG_S_LOCK0_MASK) == 0) {
}
// Set up the SIM clock dividers BEFORE switching to the PLL to ensure the
// system clock speeds are in spec.
#if 1 || (CPU == MK20D5)
{
// Disable Flash pre-fetch while changing flash divider
uint32_t temp = FMC_PFAPR;
FMC_PFAPR |= FMC_PFAPR_M3AP_MASK|FMC_PFAPR_M2AP_MASK|FMC_PFAPR_M1AP_MASK|FMC_PFAPR_M0AP_MASK;
// core/platform/system clock = PLL (48MHz), bus clock = PLL (48MHz), flash clock = PLL/2 (24MHz)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(1);
FMC_PFAPR = temp;
}
#elif CPU == MKL25Z4
{
// Disable Flash pre-fetch while changing flash divider
uint32_t temp = FMC_PFAPR;
FMC_PFAPR |= FMC_PFAPR_M3AP_MASK|FMC_PFAPR_M2AP_MASK|FMC_PFAPR_M1AP_MASK|FMC_PFAPR_M0AP_MASK;
// core/platform/system clock = PLL/2 (48MHz), bus clock/flash clock = PLL/2/2 (24MHz)
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV4(1);
FMC_PFAPR = temp;
}
#endif
// 4. PBE mode transitions into PEE mode:
// 4 a) Select clock mode
MCG_C1 = MCG_C1_CLKS(0) | // CLKS = 0 -> FLL or PLL is selected
MCG_C1_FRDIV(FRDIV_VALUE) | // FRDIV = 2,3 -> 8MHz,4MHz/256 = 31.25 kHz
MCG_C1_IRCLKEN_MASK;
// 4 b) Wait for clock stable
while ((MCG_S & MCG_S_CLKST_MASK) != (3<<MCG_S_CLKST_SHIFT)) {
}
// Now MCGOUTCLK=MCGPLLCLK=[(2 MHz / 1) * 24] = 48 MHz
// Basic clock selection
#if 1 || (CPU == MK20D5)
// Peripheral clock choice (incl. USB), USBCLK = MCGCLK
SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | // PLL rather than FLL for peripheral clock
SIM_SOPT2_USBSRC_MASK; // MCGPLLCLK Source as USB clock (48MHz req.)
// USB Clock = Divider input clock x [(USBFRAC+1)/(USBDIV+1)]
// USBDIV 0-7, USBFRAC 0-1
// SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1);
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
#elif CPU == MKL25Z4
SIM_SOPT2 = SIM_SOPT2_UART0SRC(1) | // MCGPLLCLK/2 as UART0 clock
SIM_SOPT2_TPMSRC(1) | // MCGPLLCLK/2 as TPM clock
SIM_SOPT2_PLLFLLSEL_MASK | // PLL rather than FLL for peripheral clock
SIM_SOPT2_USBSRC_MASK; // MCGPLLCLK/2 Source as USB clock (48MHz req.)
#else
#error "CPU not set"
#endif
}