static exception_type_t
operation(conf_object_t *obj, generic_transaction_t *mop, map_info_t info)
{
byte_dump_device_t *bdd = (byte_dump_device_t *)obj;
int offset = mop->physical_address + info.start - info.base;
if (SIM_mem_op_is_read(mop)) {
if (mop->inquiry)
return Sim_PE_Inquiry_Unhandled;
SIM_log_error(&bdd->log, 0,"Only write accesses allowed.");
SIM_set_mem_op_value_le(mop, 0);
} else {
uint8 value = SIM_get_mem_op_value_le(mop);
if (mop->size != 1) {
SIM_log_error(&bdd->log, 0,
"Only byte accesses allowed.");
}
SIM_log_info(2, &bdd->log, 0,
"Write to offset %d, value 0x%x: '%c'",
offset, value,
isprint(value) ? value : ' ');
if (bdd->fd >= 0)
write(bdd->fd, &value, 1);
}
return Sim_PE_No_Exception;
}
static exception_type_t
sample_operation(conf_object_t *obj, generic_transaction_t *mop,
map_info_t info)
{
sample_device_t *sample = (sample_device_t *)obj;
int offset = (int)(mop->physical_address + info.start - info.base);
if (SIM_mem_op_is_read(mop)) {
SIM_log_info(1, &sample->log, 0,
"Read from offset %d.", offset);
SIM_set_mem_op_value_le(mop, 0);
} else {
SIM_log_info(1, &sample->log, 0,
"Write to offset %d.", offset);
}
return Sim_PE_No_Exception;
}
static cycles_t
operate(conf_object_t *self,
conf_object_t *mem_space,
map_list_t *map_list,
generic_transaction_t *mem_op)
{
uart_sampler_t *s = (uart_sampler_t *)self;
uart_sampler_conf_t *c = (uart_sampler_conf_t *)s->conf;
usf_access_t ref;
if (!s->active)
return 0;
if (SIM_mem_op_is_prefetch(mem_op)) {
SIM_log_info(4, &s->log, 0, "Ignoring prefetch");
return 0;
}
if (SIM_mem_op_is_control(mem_op)) {
SIM_log_info(4, &s->log, 0, "Ignoring control");
return 0;
}
assert(SIM_mem_op_is_data(mem_op));
assert(SIM_mem_op_is_from_cpu(mem_op));
ref.pc = eip((mem_op)->ini_ptr);
ref.addr = mem_op->physical_address;
ref.time = s->time;
ref.tid = cpuid((mem_op)->ini_ptr);
ref.len = mem_op->size;
ref.type = SIM_mem_op_is_read(mem_op) ? USF_ATYPE_RD : USF_ATYPE_WR;
if (c->master)
operate_master(s, c, &ref);
else
operate_slave(s, c, &ref);
s->time++;
return 0;
}
