void spi1_init ()
{
//Setting pin CS as digital out
//spi_pin.setOutPin(CS);
//
//spi_pin.setPin(CS);
//Settings pins SCK, MOSI, MISO as ALT2
spi_pin.setOutPort((1 << CS|1 << SCK|1 << MOSI|1 << MISO), Gpio::Alt2);
//Turn on tacting SPI0
SIM->SCGC6 |= SIM_SCGC6_SPI1_MASK;
//Settings SPI1
SPI1->MCR = SPI_MCR_DCONF (0);
SPI1->MCR |= SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS(1 << 1) |SPI_MCR_DIS_TXF_MASK|SPI_MCR_DIS_RXF_MASK;
//SPI1_MCR = SPI_MCR_MSTR_MASK | SPI_MCR_ROOE_MASK | SPI_MCR_PCSIS(2) | SPI_MCR_DIS_TXF_MASK | SPI_MCR_DIS_RXF_MASK | SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK | SPI_MCR_HALT_MASK; //Set Configuration register
SPI1->CTAR[0] = SPI_CTAR_FMSZ(7) | SPI_CTAR_PASC(1) | SPI_CTAR_PBR(1)| SPI_CTAR_BR(0x0E)
//|SPI_CTAR_PCSSCK(2)|SPI_CTAR_CSSCK(2)
;
//SPI0->CTAR[1] &= ~ (SPI_CTAR_CPHA_MASK|SPI_CTAR_CPOL_MASK|SPI_CTAR_LSBFE_MASK);
//SPI1->CTAR[0] = SPI_CTAR_FMSZ(7) | SPI_CTAR_BR(0x0E);
SPI1->SR = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TXCTR(0) | SPI_SR_TXNXTPTR(0) | SPI_SR_RXCTR(0) | SPI_SR_POPNXTPTR(0); //Clear flags
SPI1->MCR &= ~SPI_MCR_HALT_MASK;
}
//! Initialise SPI
//!
//! @param default ctar0 value for SPI.CTAR0 register
//! @param default ctar1 value for SPI.CTAR1 register
//!
//! @note a default frequency is used.
//!
void spi_init(uint32_t ctar0, uint32_t ctar1) {
ctar0Value = ctar0;
ctar1Value = ctar1;
// Configure SPI
(void)spi_setSpeed(0);
SPI0->MCR = SPI_MCR_CLR_RXF_MASK|SPI_MCR_ROOE_MASK|SPI_MCR_CLR_TXF_MASK|SPI_MCR_PCSIS((1<<0)|(1<<1))|
SPI_MCR_MSTR_MASK|SPI_MCR_FRZ_MASK|SPI_MCR_DCONF(0)|SPI_MCR_SMPL_PT(0);
}
/* ===================================================================*/
void SM1_Deinit(LDD_TDeviceData *DeviceDataPtr)
{
(void)DeviceDataPtr; /* Parameter is not used, suppress unused argument warning */
/* SPI1_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=0,??=0,??=0,PCSIS=0,DOZE=0,MDIS=1,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI1_MCR = SPI_MCR_DCONF(0x00) |
SPI_MCR_PCSIS(0x00) |
SPI_MCR_MDIS_MASK |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Disable device */
/* Restoring the interrupt vector */
/* {Default RTOS Adapter} Restore interrupt vector: IVT is static, no code is generated */
/* Unregistration of the device structure */
PE_LDD_UnregisterDeviceStructure(PE_LDD_COMPONENT_SM1_ID);
/* Deallocation of the device structure */
/* {Default RTOS Adapter} Driver memory deallocation: Dynamic allocation is simulated, no deallocation code is generated */
/* SIM_SCGC6: SPI1=0 */
SIM_SCGC6 &= (uint32_t)~(uint32_t)(SIM_SCGC6_SPI1_MASK);
}
/* ===================================================================*/
LDD_TDeviceData* SPI_SD_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
SPI_SD_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_SPI1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
DeviceDataPrv->TxCommand = 0x80000000U; /* Initialization of current Tx command */
DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
DeviceDataPrv->CurrentAttributeSet = 0U; /* Init current attribute set */
DeviceDataPrv->SerFlag = 0x00U; /* Reset flags */
/* SIM_SCGC6: SPI1=1 */
SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
/* Interrupt vector(s) priority setting */
/* NVICIP27: PRI27=0x70 */
NVICIP27 = NVIC_IP_PRI27(0x70);
/* NVICISER0: SETENA|=0x08000000 */
NVICISER0 |= NVIC_ISER_SETENA(0x08000000);
/* SIM_SCGC5: PORTD=1 */
SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;
/* PORTD_PCR7: ISF=0,MUX=7 */
PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK
)) | (uint32_t)(
PORT_PCR_MUX(0x07)
));
/* PORTD_PCR6: ISF=0,MUX=7 */
PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK
)) | (uint32_t)(
PORT_PCR_MUX(0x07)
));
/* PORTD_PCR5: ISF=0,MUX=7 */
PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK
)) | (uint32_t)(
PORT_PCR_MUX(0x07)
));
/* SPI1_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI1_MCR = SPI_MCR_DCONF(0x00) |
SPI_MCR_ROOE_MASK |
SPI_MCR_PCSIS(0x00) |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Set Configuration register */
/* SPI1_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,PCSSE=0,ROOE=1,??=0,??=0,PCSIS=0,DOZE=0,MDIS=0,DIS_TXF=1,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI1_MCR = SPI_MCR_MSTR_MASK |
SPI_MCR_DCONF(0x00) |
SPI_MCR_ROOE_MASK |
SPI_MCR_PCSIS(0x00) |
SPI_MCR_DIS_TXF_MASK |
SPI_MCR_DIS_RXF_MASK |
SPI_MCR_CLR_TXF_MASK |
SPI_MCR_CLR_RXF_MASK |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Set Configuration register */
/* SPI1_CTAR0: DBR=1,FMSZ=7,CPOL=0,CPHA=0,LSBFE=0,PCSSCK=0,PASC=0,PDT=0,PBR=0,CSSCK=0,ASC=0,DT=0,BR=0 */
SPI1_CTAR0 = SPI_CTAR_DBR_MASK |
SPI_CTAR_FMSZ(0x07) |
SPI_CTAR_PCSSCK(0x00) |
SPI_CTAR_PASC(0x00) |
SPI_CTAR_PDT(0x00) |
SPI_CTAR_PBR(0x00) |
SPI_CTAR_CSSCK(0x00) |
SPI_CTAR_ASC(0x00) |
SPI_CTAR_DT(0x00) |
SPI_CTAR_BR(0x00); /* Set Clock and Transfer Attributes register */
/* SPI1_SR: TCF=1,TXRXS=0,??=0,EOQF=1,TFUF=1,??=0,TFFF=1,??=0,??=0,??=0,??=1,??=0,RFOF=1,??=0,RFDF=1,??=0,TXCTR=0,TXNXTPTR=0,RXCTR=0,POPNXTPTR=0 */
SPI1_SR = SPI_SR_TCF_MASK |
SPI_SR_EOQF_MASK |
SPI_SR_TFUF_MASK |
SPI_SR_TFFF_MASK |
SPI_SR_RFOF_MASK |
SPI_SR_RFDF_MASK |
SPI_SR_TXCTR(0x00) |
SPI_SR_TXNXTPTR(0x00) |
SPI_SR_RXCTR(0x00) |
SPI_SR_POPNXTPTR(0x00) |
0x00200000U; /* Clear flags */
/* SPI1_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SPI1_RSER = SPI_RSER_RFDF_RE_MASK; /* Set DMA Interrupt Request Select and Enable register */
SPI_SD_SetClockConfiguration(DeviceDataPrv, Cpu_GetClockConfiguration()); /* Set Initial according speed CPU mode */
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SPI_SD_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/* ===================================================================*/
LDD_TDeviceData* SM1_Init(LDD_TUserData *UserDataPtr)
{
/* Allocate LDD device structure */
SM1_TDeviceDataPtr DeviceDataPrv;
/* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
/* Interrupt vector(s) allocation */
/* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
INT_SPI0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
DeviceDataPrv->TxCommand = 0x80040000U; /* Initialization of current Tx command */
DeviceDataPrv->ErrFlag = 0x00U; /* Clear error flags */
/* Clear the receive counters and pointer */
DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
DeviceDataPrv->InpDataPtr = NULL; /* Clear the buffer pointer for received characters */
/* Clear the transmit counters and pointer */
DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
DeviceDataPrv->OutDataPtr = NULL; /* Clear the buffer pointer for data to be transmitted */
/* SIM_SCGC6: SPI0=1 */
SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK;
/* Interrupt vector(s) priority setting */
/* NVIC_IPR2: PRI_10=1 */
NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)(
NVIC_IP_PRI_10(0x02)
)) | (uint32_t)(
NVIC_IP_PRI_10(0x01)
));
/* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=0,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=1,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */
NVIC_ISER = NVIC_ISER_SETENA10_MASK;
/* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */
NVIC_ICER = 0x00U;
/* SIM_SCGC5: PORTE=1,PORTC=1 */
SIM_SCGC5 |= (SIM_SCGC5_PORTE_MASK | SIM_SCGC5_PORTC_MASK);
/* PORTE_PCR18: ISF=0,MUX=6 */
PORTE_PCR18 = (uint32_t)((PORTE_PCR18 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x01)
)) | (uint32_t)(
PORT_PCR_MUX(0x06)
));
/* PORTE_PCR19: ISF=0,MUX=6 */
PORTE_PCR19 = (uint32_t)((PORTE_PCR19 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x01)
)) | (uint32_t)(
PORT_PCR_MUX(0x06)
));
/* PORTC_PCR5: ISF=0,MUX=2 */
PORTC_PCR5 = (uint32_t)((PORTC_PCR5 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* PORTC_PCR2: ISF=0,MUX=2 */
PORTC_PCR2 = (uint32_t)((PORTC_PCR2 & (uint32_t)~(uint32_t)(
PORT_PCR_ISF_MASK |
PORT_PCR_MUX(0x05)
)) | (uint32_t)(
PORT_PCR_MUX(0x02)
));
/* SPI0_MCR: MSTR=0,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,??=0,ROOE=1,??=0,??=0,??=0,PCSIS=4,DOZE=0,MDIS=0,DIS_TXF=0,DIS_RXF=0,CLR_TXF=0,CLR_RXF=0,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI0_MCR = SPI_MCR_DCONF(0x00) |
SPI_MCR_ROOE_MASK |
SPI_MCR_PCSIS(0x04) |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Set Configuration register */
/* SPI0_MCR: MSTR=1,CONT_SCKE=0,DCONF=0,FRZ=0,MTFE=0,??=0,ROOE=1,??=0,??=0,??=0,PCSIS=4,DOZE=0,MDIS=0,DIS_TXF=1,DIS_RXF=1,CLR_TXF=1,CLR_RXF=1,SMPL_PT=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HALT=1 */
SPI0_MCR = SPI_MCR_MSTR_MASK |
SPI_MCR_DCONF(0x00) |
SPI_MCR_ROOE_MASK |
SPI_MCR_PCSIS(0x04) |
SPI_MCR_DIS_TXF_MASK |
SPI_MCR_DIS_RXF_MASK |
SPI_MCR_CLR_TXF_MASK |
SPI_MCR_CLR_RXF_MASK |
SPI_MCR_SMPL_PT(0x00) |
SPI_MCR_HALT_MASK; /* Set Configuration register */
/* SPI0_CTAR0: DBR=1,FMSZ=7,CPOL=0,CPHA=0,LSBFE=0,PCSSCK=0,PASC=0,PDT=0,PBR=2,CSSCK=0,ASC=0,DT=0,BR=1 */
SPI0_CTAR0 = SPI_CTAR_DBR_MASK |
SPI_CTAR_FMSZ(0x07) |
SPI_CTAR_PCSSCK(0x00) |
SPI_CTAR_PASC(0x00) |
SPI_CTAR_PDT(0x00) |
SPI_CTAR_PBR(0x02) |
SPI_CTAR_CSSCK(0x00) |
SPI_CTAR_ASC(0x00) |
SPI_CTAR_DT(0x00) |
SPI_CTAR_BR(0x01); /* Set Clock and Transfer Attributes register */
/* SPI0_SR: TCF=1,TXRXS=0,??=0,EOQF=1,TFUF=1,??=0,TFFF=1,??=0,??=0,??=0,??=1,??=0,RFOF=1,??=0,RFDF=1,??=0,TXCTR=0,TXNXTPTR=0,RXCTR=0,POPNXTPTR=0 */
SPI0_SR = SPI_SR_TCF_MASK |
SPI_SR_EOQF_MASK |
SPI_SR_TFUF_MASK |
SPI_SR_TFFF_MASK |
SPI_SR_RFOF_MASK |
SPI_SR_RFDF_MASK |
SPI_SR_TXCTR(0x00) |
SPI_SR_TXNXTPTR(0x00) |
SPI_SR_RXCTR(0x00) |
SPI_SR_POPNXTPTR(0x00) |
0x00200000U; /* Clear flags */
/* SPI0_RSER: TCF_RE=0,??=0,??=0,EOQF_RE=0,TFUF_RE=0,??=0,TFFF_RE=0,TFFF_DIRS=0,??=0,??=0,??=0,??=0,RFOF_RE=0,??=0,RFDF_RE=1,RFDF_DIRS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SPI0_RSER = SPI_RSER_RFDF_RE_MASK; /* Set DMA Interrupt Request Select and Enable register */
/* SPI0_MCR: HALT=0 */
SPI0_MCR &= (uint32_t)~(uint32_t)(SPI_MCR_HALT_MASK);
/* Registration of the device structure */
PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SM1_ID,DeviceDataPrv);
return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
OSStatus spi_init( spi_driver_t* spi_driver, SPI_MemMapPtr spi_peripheral, uint32_t baud_rate_bps, uint8_t chip_select, bool polarity, bool phase, bool use_dma )
{
uint8_t br = get_baud_rate_scaler_register_value( baud_rate_bps );
spi_driver->spi_peripheral = spi_peripheral;
spi_driver->baud_rate_bps = baud_rate_bps;
spi_driver->chip_select = chip_select;
spi_driver->polarity = polarity;
spi_driver->phase = phase;
spi_driver->use_dma = use_dma;
/* Enable SPI peripheral clock */
set_spi_peripheral_clock( spi_peripheral, true );
/* Enable SPI peripheral and clean up (stop) any previous transfer
* MDIS = 0 to enable
* HALT = 1 to stop transfer
* MSTR = 1 for master mode
* DCONF = 0 for SPI
* PCSIS[x] = 1 for CS active low
*/
SPI_MCR_REG( spi_peripheral ) &= ~(uint32_t) ( SPI_MCR_MDIS_MASK | SPI_MCR_DCONF(0) );
SPI_MCR_REG( spi_peripheral ) |= (uint32_t) ( (0x1<<24)|SPI_MCR_HALT_MASK | SPI_MCR_MSTR_MASK | SPI_MCR_PCSIS( 1 << chip_select ) );
/* Select Clock and Transfer Attributes Register (CTAR). Always use CTAR0 */
SPI_PUSHR_REG( spi_peripheral ) &= ~(uint32_t) SPI_PUSHR_CTAS(CTAR_REG_USED);
/* Reset Clock and Transfer Attributes (CTAR) register */
SPI_CTAR_REG( spi_peripheral, CTAR_REG_USED ) = 0;
/* Set SPI configuration
* FMSZ = 7. Set frame size to 8-bit. frame size = FMSZ + 1
* CPOL = phase
* CPHA = polarity
* DBR = 00
* PBR = 2
* BR = calculate based on baud_rate_Mbps
* PCSSCK = 0
* PASC = 0
* PDT = 0
* CSSCK = BR - 1
* ASC = BR - 1
* DT = 0
*/
SPI_CTAR_REG( spi_peripheral, CTAR_REG_USED ) |= (uint32_t) ( SPI_CTAR_CPOL_MASK & (uint32_t)( polarity << SPI_CTAR_CPOL_SHIFT ) ) |
(uint32_t) ( SPI_CTAR_CPHA_MASK & (uint32_t)( phase << SPI_CTAR_CPHA_SHIFT ) ) |
(uint32_t) ( SPI_CTAR_FMSZ( 8 - 1 ) ) |
(uint32_t) ( SPI_CTAR_DBR_MASK & ( DOUBLE_BAUD_RATE << SPI_CTAR_DBR_SHIFT ) ) |
(uint32_t) ( SPI_CTAR_PBR( CTAR_PBR ) ) |
(uint32_t) ( SPI_CTAR_BR( br ) ) |
(uint32_t) ( SPI_CTAR_CSSCK( br - 1 ) ) |
(uint32_t) ( SPI_CTAR_ASC( br - 1 ) );
clear_spi_fifos( spi_peripheral );
/* Enable the start transfer bit */
SPI_MCR_REG( spi_peripheral ) &= ~(uint32_t) ( SPI_MCR_HALT_MASK );
if(use_dma)
{
SPI_RSER_REG( spi_peripheral ) |= (0x3<<24)|(0x3<<16);
DMA_init();
}
spi_status_print(spi_peripheral);
return kNoErr;
}
