void fdct16x8_1d_row(int16_t *input, int16_t *output) {
v8i16 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7;
v8i16 in0, in1, in2, in3, in4, in5, in6, in7;
v8i16 in8, in9, in10, in11, in12, in13, in14, in15;
LD_SH8(input, 16, in0, in1, in2, in3, in4, in5, in6, in7);
LD_SH8((input + 8), 16, in8, in9, in10, in11, in12, in13, in14, in15);
TRANSPOSE8x8_SH_SH(in0, in1, in2, in3, in4, in5, in6, in7, in0, in1, in2, in3,
in4, in5, in6, in7);
TRANSPOSE8x8_SH_SH(in8, in9, in10, in11, in12, in13, in14, in15, in8, in9,
in10, in11, in12, in13, in14, in15);
ADD4(in0, 1, in1, 1, in2, 1, in3, 1, in0, in1, in2, in3);
ADD4(in4, 1, in5, 1, in6, 1, in7, 1, in4, in5, in6, in7);
ADD4(in8, 1, in9, 1, in10, 1, in11, 1, in8, in9, in10, in11);
ADD4(in12, 1, in13, 1, in14, 1, in15, 1, in12, in13, in14, in15);
SRA_4V(in0, in1, in2, in3, 2);
SRA_4V(in4, in5, in6, in7, 2);
SRA_4V(in8, in9, in10, in11, 2);
SRA_4V(in12, in13, in14, in15, 2);
BUTTERFLY_16(in0, in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11,
in12, in13, in14, in15, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6,
tmp7, in8, in9, in10, in11, in12, in13, in14, in15);
ST_SH8(in8, in9, in10, in11, in12, in13, in14, in15, input, 16);
FDCT8x16_EVEN(tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp0, tmp1,
tmp2, tmp3, tmp4, tmp5, tmp6, tmp7);
LD_SH8(input, 16, in8, in9, in10, in11, in12, in13, in14, in15);
FDCT8x16_ODD(in8, in9, in10, in11, in12, in13, in14, in15, in0, in1, in2, in3,
in4, in5, in6, in7);
TRANSPOSE8x8_SH_SH(tmp0, in0, tmp1, in1, tmp2, in2, tmp3, in3, tmp0, in0,
tmp1, in1, tmp2, in2, tmp3, in3);
ST_SH8(tmp0, in0, tmp1, in1, tmp2, in2, tmp3, in3, output, 16);
TRANSPOSE8x8_SH_SH(tmp4, in4, tmp5, in5, tmp6, in6, tmp7, in7, tmp4, in4,
tmp5, in5, tmp6, in6, tmp7, in7);
ST_SH8(tmp4, in4, tmp5, in5, tmp6, in6, tmp7, in7, output + 8, 16);
}
void vp8_short_fdct8x4_msa(int16_t *input, int16_t *output, int32_t pitch) {
v8i16 in0, in1, in2, in3;
v8i16 temp0, temp1, tmp0, tmp1;
v8i16 const0, const1, const2;
v8i16 coeff = { 2217, 5352, -5352, 14500, 7500, 12000, 25000, 26000 };
v8i16 zero = { 0 };
v4i32 vec0_w, vec1_w, vec2_w, vec3_w;
LD_SH4(input, pitch / 2, in0, in1, in2, in3);
TRANSPOSE4x4_H(in0, in1, in2, in3, in0, in1, in2, in3);
BUTTERFLY_4(in0, in1, in2, in3, temp0, temp1, in1, in3);
SLLI_4V(temp0, temp1, in1, in3, 3);
in0 = temp0 + temp1;
in2 = temp0 - temp1;
SET_DOTP_VALUES(coeff, 0, 1, 2, const1, const2);
temp0 = __msa_splati_h(coeff, 3);
vec1_w = (v4i32)__msa_ilvev_h(zero, temp0);
coeff = __msa_ilvl_h(zero, coeff);
vec3_w = __msa_splati_w((v4i32)coeff, 0);
ILVRL_H2_SH(in3, in1, tmp1, tmp0);
vec0_w = vec1_w;
vec2_w = vec3_w;
DPADD_SH4_SW(tmp1, tmp0, tmp1, tmp0, const1, const1, const2, const2, vec0_w,
vec1_w, vec2_w, vec3_w);
SRA_4V(vec1_w, vec0_w, vec3_w, vec2_w, 12);
PCKEV_H2_SH(vec1_w, vec0_w, vec3_w, vec2_w, in1, in3);
TRANSPOSE4x4_H(in0, in1, in2, in3, in0, in1, in2, in3);
BUTTERFLY_4(in0, in1, in2, in3, temp0, temp1, in1, in3);
in0 = temp0 + temp1 + 7;
in2 = temp0 - temp1 + 7;
in0 >>= 4;
in2 >>= 4;
SPLATI_W2_SW(coeff, 2, vec3_w, vec1_w);
vec3_w += vec1_w;
vec1_w = __msa_splati_w((v4i32)coeff, 1);
const0 = RET_1_IF_NZERO_H(in3);
ILVRL_H2_SH(in3, in1, tmp1, tmp0);
vec0_w = vec1_w;
vec2_w = vec3_w;
DPADD_SH4_SW(tmp1, tmp0, tmp1, tmp0, const1, const1, const2, const2, vec0_w,
vec1_w, vec2_w, vec3_w);
SRA_4V(vec1_w, vec0_w, vec3_w, vec2_w, 16);
PCKEV_H2_SH(vec1_w, vec0_w, vec3_w, vec2_w, in1, in3);
in1 += const0;
PCKEV_D2_SH(in1, in0, in3, in2, temp0, temp1);
ST_SH2(temp0, temp1, output, 8);
PCKOD_D2_SH(in1, in0, in3, in2, in0, in2);
ST_SH2(in0, in2, output + 16, 8);
}
void vpx_fdct4x4_msa(const int16_t *input, int16_t *output,
int32_t src_stride) {
v8i16 in0, in1, in2, in3;
LD_SH4(input, src_stride, in0, in1, in2, in3);
/* fdct4 pre-process */
{
v8i16 vec, mask;
v16i8 zero = { 0 };
v16i8 one = __msa_ldi_b(1);
mask = (v8i16)__msa_sldi_b(zero, one, 15);
SLLI_4V(in0, in1, in2, in3, 4);
vec = __msa_ceqi_h(in0, 0);
vec = vec ^ 255;
vec = mask & vec;
in0 += vec;
}
VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
ADD4(in0, 1, in1, 1, in2, 1, in3, 1, in0, in1, in2, in3);
SRA_4V(in0, in1, in2, in3, 2);
PCKEV_D2_SH(in1, in0, in3, in2, in0, in2);
ST_SH2(in0, in2, output, 8);
}
void vp8_short_walsh4x4_msa(int16_t *input, int16_t *output, int32_t pitch) {
v8i16 in0_h, in1_h, in2_h, in3_h;
v4i32 in0_w, in1_w, in2_w, in3_w, temp0, temp1, temp2, temp3;
LD_SH4(input, pitch / 2, in0_h, in1_h, in2_h, in3_h);
TRANSPOSE4x4_SH_SH(in0_h, in1_h, in2_h, in3_h, in0_h, in1_h, in2_h, in3_h);
UNPCK_R_SH_SW(in0_h, in0_w);
UNPCK_R_SH_SW(in1_h, in1_w);
UNPCK_R_SH_SW(in2_h, in2_w);
UNPCK_R_SH_SW(in3_h, in3_w);
BUTTERFLY_4(in0_w, in1_w, in3_w, in2_w, temp0, temp3, temp2, temp1);
SLLI_4V(temp0, temp1, temp2, temp3, 2);
BUTTERFLY_4(temp0, temp1, temp2, temp3, in0_w, in1_w, in2_w, in3_w);
temp0 = RET_1_IF_NZERO_W(temp0);
in0_w += temp0;
TRANSPOSE4x4_SW_SW(in0_w, in1_w, in2_w, in3_w, in0_w, in1_w, in2_w, in3_w);
BUTTERFLY_4(in0_w, in1_w, in3_w, in2_w, temp0, temp3, temp2, temp1);
BUTTERFLY_4(temp0, temp1, temp2, temp3, in0_w, in1_w, in2_w, in3_w);
in0_w += RET_1_IF_NEG_W(in0_w);
in1_w += RET_1_IF_NEG_W(in1_w);
in2_w += RET_1_IF_NEG_W(in2_w);
in3_w += RET_1_IF_NEG_W(in3_w);
ADD4(in0_w, 3, in1_w, 3, in2_w, 3, in3_w, 3, in0_w, in1_w, in2_w, in3_w);
SRA_4V(in0_w, in1_w, in2_w, in3_w, 3);
PCKEV_H2_SH(in1_w, in0_w, in3_w, in2_w, in0_h, in1_h);
ST_SH2(in0_h, in1_h, output, 8);
}
static void avc_dequant_4x4_msa( int16_t *p_dct, int32_t pi_dequant_mf[6][16],
int32_t i_qp )
{
const int32_t i_mf = i_qp % 6;
const int32_t q_bits = i_qp / 6 - 4;
v8i16 dct0, dct1;
v4i32 dequant_m_f0, dequant_m_f1, dequant_m_f2, dequant_m_f3;
LD_SH2( p_dct, 8, dct0, dct1 );
LD_SW2( pi_dequant_mf[i_mf], 4, dequant_m_f0, dequant_m_f1 );
LD_SW2( pi_dequant_mf[i_mf] + 8, 4, dequant_m_f2, dequant_m_f3 );
if( q_bits >= 0 )
{
v8i16 dequant_mf_h0, dequant_mf_h1, q_bits_vec;
q_bits_vec = __msa_fill_h( q_bits );
PCKEV_H2_SH( dequant_m_f1, dequant_m_f0, dequant_m_f3, dequant_m_f2,
dequant_mf_h0, dequant_mf_h1 );
dct0 *= dequant_mf_h0;
dct1 *= dequant_mf_h1;
dct0 <<= q_bits_vec;
dct1 <<= q_bits_vec;
ST_SH2( dct0, dct1, p_dct, 8 );
}
else
{
const int32_t q_bits_add = 1 << ( -q_bits - 1 );
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
v4i32 q_bits_vec, q_bits_vec_add;
q_bits_vec_add = __msa_fill_w( q_bits_add );
q_bits_vec = __msa_fill_w( -q_bits );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
dct_signed_w0 *= dequant_m_f0;
dct_signed_w1 *= dequant_m_f1;
dct_signed_w2 *= dequant_m_f2;
dct_signed_w3 *= dequant_m_f3;
dct_signed_w0 += q_bits_vec_add;
dct_signed_w1 += q_bits_vec_add;
dct_signed_w2 += q_bits_vec_add;
dct_signed_w3 += q_bits_vec_add;
SRA_4V( dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3,
q_bits_vec );
PCKEV_H2_SH( dct_signed_w1, dct_signed_w0, dct_signed_w3, dct_signed_w2,
dct0, dct1 );
ST_SH2( dct0, dct1, p_dct, 8 );
}
}
void vp9_fht4x4_msa(const int16_t *input, int16_t *output, int32_t stride,
int32_t tx_type) {
v8i16 in0, in1, in2, in3;
LD_SH4(input, stride, in0, in1, in2, in3);
/* fdct4 pre-process */
{
v8i16 temp, mask;
v16i8 zero = { 0 };
v16i8 one = __msa_ldi_b(1);
mask = (v8i16)__msa_sldi_b(zero, one, 15);
SLLI_4V(in0, in1, in2, in3, 4);
temp = __msa_ceqi_h(in0, 0);
temp = (v8i16)__msa_xori_b((v16u8)temp, 255);
temp = mask & temp;
in0 += temp;
}
switch (tx_type) {
case DCT_DCT:
VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
break;
case ADST_DCT:
VP9_FADST4(in0, in1, in2, in3, in0, in1, in2, in3);
TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
break;
case DCT_ADST:
VP9_FDCT4(in0, in1, in2, in3, in0, in1, in2, in3);
TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
VP9_FADST4(in0, in1, in2, in3, in0, in1, in2, in3);
break;
case ADST_ADST:
VP9_FADST4(in0, in1, in2, in3, in0, in1, in2, in3);
TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
VP9_FADST4(in0, in1, in2, in3, in0, in1, in2, in3);
break;
default:
assert(0);
break;
}
TRANSPOSE4x4_SH_SH(in0, in1, in2, in3, in0, in1, in2, in3);
ADD4(in0, 1, in1, 1, in2, 1, in3, 1, in0, in1, in2, in3);
SRA_4V(in0, in1, in2, in3, 2);
PCKEV_D2_SH(in1, in0, in3, in2, in0, in2);
ST_SH2(in0, in2, output, 8);
}
static int32_t avc_quant_4x4_msa( int16_t *p_dct, uint16_t *p_mf,
uint16_t *p_bias )
{
int32_t non_zero = 0;
v8i16 dct0, dct1;
v8i16 zero = { 0 };
v8i16 dct0_mask, dct1_mask;
v8i16 dct_h0, dct_h1, mf_h0, mf_h1, bias_h0, bias_h1;
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
v4i32 dct_w0, dct_w1, dct_w2, dct_w3;
v4i32 mf_vec0, mf_vec1, mf_vec2, mf_vec3;
v4i32 bias0, bias1, bias2, bias3;
LD_SH2( p_dct, 8, dct0, dct1 );
LD_SH2( p_bias, 8, bias_h0, bias_h1 );
LD_SH2( p_mf, 8, mf_h0, mf_h1 );
dct0_mask = __msa_clei_s_h( dct0, 0 );
dct1_mask = __msa_clei_s_h( dct1, 0 );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
ILVR_H2_SW( zero, bias_h0, zero, bias_h1, bias0, bias2 );
ILVL_H2_SW( zero, bias_h0, zero, bias_h1, bias1, bias3 );
ILVR_H2_SW( zero, mf_h0, zero, mf_h1, mf_vec0, mf_vec2 );
ILVL_H2_SW( zero, mf_h0, zero, mf_h1, mf_vec1, mf_vec3 );
dct_w1 = __msa_add_a_w( dct_signed_w1, bias1 );
dct_w0 = __msa_add_a_w( dct_signed_w0, bias0 );
dct_w2 = __msa_add_a_w( dct_signed_w2, bias2 );
dct_w3 = __msa_add_a_w( dct_signed_w3, bias3 );
dct_w0 *= mf_vec0;
dct_w1 *= mf_vec1;
dct_w2 *= mf_vec2;
dct_w3 *= mf_vec3;
SRA_4V( dct_w0, dct_w1, dct_w2, dct_w3, 16 );
PCKEV_H2_SH( dct_w1, dct_w0, dct_w3, dct_w2, dct_h0, dct_h1 );
dct0 = zero - dct_h0;
dct1 = zero - dct_h1;
dct0 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h0, ( v16u8 ) dct0,
( v16u8 ) dct0_mask );
dct1 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h1, ( v16u8 ) dct1,
( v16u8 ) dct1_mask );
non_zero = HADD_SW_S32( ( v4u32 ) ( dct_h0 + dct_h1 ) );
ST_SH2( dct0, dct1, p_dct, 8 );
return !!non_zero;
}
static void avc_dequant_4x4_dc_msa( int16_t *p_dct,
int32_t pi_dequant_mf[6][16],
int32_t i_qp )
{
const int32_t q_bits = i_qp / 6 - 6;
int32_t i_dmf = pi_dequant_mf[i_qp % 6][0];
v8i16 dct0, dct1, dequant_mf_h;
LD_SH2( p_dct, 8, dct0, dct1 );
if( q_bits >= 0 )
{
i_dmf <<= q_bits;
dequant_mf_h = __msa_fill_h( i_dmf );
dct0 = dct0 * dequant_mf_h;
dct1 = dct1 * dequant_mf_h;
ST_SH2( dct0, dct1, p_dct, 8 );
}
else
{
const int32_t q_bits_add = 1 << ( -q_bits - 1 );
v4i32 dequant_m_f, q_bits_vec, q_bits_vec_add;
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
q_bits_vec_add = __msa_fill_w( q_bits_add );
q_bits_vec = __msa_fill_w( -q_bits );
dequant_m_f = __msa_fill_w( i_dmf );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
dct_signed_w0 *= dequant_m_f;
dct_signed_w1 *= dequant_m_f;
dct_signed_w2 *= dequant_m_f;
dct_signed_w3 *= dequant_m_f;
dct_signed_w0 += q_bits_vec_add;
dct_signed_w1 += q_bits_vec_add;
dct_signed_w2 += q_bits_vec_add;
dct_signed_w3 += q_bits_vec_add;
SRA_4V( dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3,
q_bits_vec );
PCKEV_H2_SH( dct_signed_w1, dct_signed_w0, dct_signed_w3, dct_signed_w2,
dct0, dct1 );
ST_SH2( dct0, dct1, p_dct, 8 );
}
}
static int32_t avc_quant_4x4_dc_msa( int16_t *p_dct, int32_t i_mf,
int32_t i_bias )
{
int32_t non_zero = 0;
v8i16 dct0, dct1, dct0_mask, dct1_mask;
v8i16 zero = { 0 };
v8i16 dct_h0, dct_h1;
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
v4i32 dct_w0, dct_w1, dct_w2, dct_w3;
v4i32 mf_vec, bias_vec;
LD_SH2( p_dct, 8, dct0, dct1 );
dct0_mask = __msa_clei_s_h( dct0, 0 );
dct1_mask = __msa_clei_s_h( dct1, 0 );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
bias_vec = __msa_fill_w( i_bias );
mf_vec = __msa_fill_w( i_mf );
dct_w0 = __msa_add_a_w( dct_signed_w0, bias_vec );
dct_w1 = __msa_add_a_w( dct_signed_w1, bias_vec );
dct_w2 = __msa_add_a_w( dct_signed_w2, bias_vec );
dct_w3 = __msa_add_a_w( dct_signed_w3, bias_vec );
dct_w0 *= mf_vec;
dct_w1 *= mf_vec;
dct_w2 *= mf_vec;
dct_w3 *= mf_vec;
SRA_4V( dct_w0, dct_w1, dct_w2, dct_w3, 16 );
PCKEV_H2_SH( dct_w1, dct_w0, dct_w3, dct_w2, dct_h0, dct_h1 );
dct0 = zero - dct_h0;
dct1 = zero - dct_h1;
dct0 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h0,
( v16u8 ) dct0, ( v16u8 ) dct0_mask );
dct1 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h1,
( v16u8 ) dct1, ( v16u8 ) dct1_mask );
non_zero = HADD_SW_S32( ( v4u32 ) ( dct_h0 + dct_h1 ) );
ST_SH2( dct0, dct1, p_dct, 8 );
return !!non_zero;
}
void aom_iwht4x4_16_add_msa(const int16_t *input, uint8_t *dst,
int32_t dst_stride) {
v8i16 in0, in1, in2, in3;
v4i32 in0_r, in1_r, in2_r, in3_r, in4_r;
/* load vector elements of 4x4 block */
LD4x4_SH(input, in0, in2, in3, in1);
TRANSPOSE4x4_SH_SH(in0, in2, in3, in1, in0, in2, in3, in1);
UNPCK_R_SH_SW(in0, in0_r);
UNPCK_R_SH_SW(in2, in2_r);
UNPCK_R_SH_SW(in3, in3_r);
UNPCK_R_SH_SW(in1, in1_r);
SRA_4V(in0_r, in1_r, in2_r, in3_r, UNIT_QUANT_SHIFT);
in0_r += in2_r;
in3_r -= in1_r;
in4_r = (in0_r - in3_r) >> 1;
in1_r = in4_r - in1_r;
in2_r = in4_r - in2_r;
in0_r -= in1_r;
in3_r += in2_r;
TRANSPOSE4x4_SW_SW(in0_r, in1_r, in2_r, in3_r, in0_r, in1_r, in2_r, in3_r);
in0_r += in1_r;
in2_r -= in3_r;
in4_r = (in0_r - in2_r) >> 1;
in3_r = in4_r - in3_r;
in1_r = in4_r - in1_r;
in0_r -= in3_r;
in2_r += in1_r;
PCKEV_H4_SH(in0_r, in0_r, in1_r, in1_r, in2_r, in2_r, in3_r, in3_r, in0, in1,
in2, in3);
ADDBLK_ST4x4_UB(in0, in3, in1, in2, dst, dst_stride);
}
static void avc_idct8_addblk_msa( uint8_t *p_dst, int16_t *p_src,
int32_t i_dst_stride )
{
v8i16 src0, src1, src2, src3, src4, src5, src6, src7;
v8i16 vec0, vec1, vec2, vec3;
v8i16 tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7;
v8i16 res0, res1, res2, res3, res4, res5, res6, res7;
v4i32 tmp0_r, tmp1_r, tmp2_r, tmp3_r, tmp4_r, tmp5_r, tmp6_r, tmp7_r;
v4i32 tmp0_l, tmp1_l, tmp2_l, tmp3_l, tmp4_l, tmp5_l, tmp6_l, tmp7_l;
v4i32 vec0_r, vec1_r, vec2_r, vec3_r, vec0_l, vec1_l, vec2_l, vec3_l;
v4i32 res0_r, res1_r, res2_r, res3_r, res4_r, res5_r, res6_r, res7_r;
v4i32 res0_l, res1_l, res2_l, res3_l, res4_l, res5_l, res6_l, res7_l;
v16i8 dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7;
v16i8 zeros = { 0 };
p_src[ 0 ] += 32;
LD_SH8( p_src, 8, src0, src1, src2, src3, src4, src5, src6, src7 );
vec0 = src0 + src4;
vec1 = src0 - src4;
vec2 = src2 >> 1;
vec2 = vec2 - src6;
vec3 = src6 >> 1;
vec3 = src2 + vec3;
BUTTERFLY_4( vec0, vec1, vec2, vec3, tmp0, tmp1, tmp2, tmp3 );
vec0 = src7 >> 1;
vec0 = src5 - vec0 - src3 - src7;
vec1 = src3 >> 1;
vec1 = src1 - vec1 + src7 - src3;
vec2 = src5 >> 1;
vec2 = vec2 - src1 + src7 + src5;
vec3 = src1 >> 1;
vec3 = vec3 + src3 + src5 + src1;
tmp4 = vec3 >> 2;
tmp4 += vec0;
tmp5 = vec2 >> 2;
tmp5 += vec1;
tmp6 = vec1 >> 2;
tmp6 -= vec2;
tmp7 = vec0 >> 2;
tmp7 = vec3 - tmp7;
BUTTERFLY_8( tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7,
res0, res1, res2, res3, res4, res5, res6, res7 );
TRANSPOSE8x8_SH_SH( res0, res1, res2, res3, res4, res5, res6, res7,
res0, res1, res2, res3, res4, res5, res6, res7 );
UNPCK_SH_SW( res0, tmp0_r, tmp0_l );
UNPCK_SH_SW( res1, tmp1_r, tmp1_l );
UNPCK_SH_SW( res2, tmp2_r, tmp2_l );
UNPCK_SH_SW( res3, tmp3_r, tmp3_l );
UNPCK_SH_SW( res4, tmp4_r, tmp4_l );
UNPCK_SH_SW( res5, tmp5_r, tmp5_l );
UNPCK_SH_SW( res6, tmp6_r, tmp6_l );
UNPCK_SH_SW( res7, tmp7_r, tmp7_l );
BUTTERFLY_4( tmp0_r, tmp0_l, tmp4_l, tmp4_r,
vec0_r, vec0_l, vec1_l, vec1_r );
vec2_r = tmp2_r >> 1;
vec2_l = tmp2_l >> 1;
vec2_r -= tmp6_r;
vec2_l -= tmp6_l;
vec3_r = tmp6_r >> 1;
vec3_l = tmp6_l >> 1;
vec3_r += tmp2_r;
vec3_l += tmp2_l;
BUTTERFLY_4( vec0_r, vec1_r, vec2_r, vec3_r,
tmp0_r, tmp2_r, tmp4_r, tmp6_r );
BUTTERFLY_4( vec0_l, vec1_l, vec2_l, vec3_l,
tmp0_l, tmp2_l, tmp4_l, tmp6_l );
vec0_r = tmp7_r >> 1;
vec0_l = tmp7_l >> 1;
vec0_r = tmp5_r - vec0_r - tmp3_r - tmp7_r;
vec0_l = tmp5_l - vec0_l - tmp3_l - tmp7_l;
vec1_r = tmp3_r >> 1;
vec1_l = tmp3_l >> 1;
vec1_r = tmp1_r - vec1_r + tmp7_r - tmp3_r;
vec1_l = tmp1_l - vec1_l + tmp7_l - tmp3_l;
vec2_r = tmp5_r >> 1;
vec2_l = tmp5_l >> 1;
vec2_r = vec2_r - tmp1_r + tmp7_r + tmp5_r;
vec2_l = vec2_l - tmp1_l + tmp7_l + tmp5_l;
vec3_r = tmp1_r >> 1;
vec3_l = tmp1_l >> 1;
vec3_r = vec3_r + tmp3_r + tmp5_r + tmp1_r;
vec3_l = vec3_l + tmp3_l + tmp5_l + tmp1_l;
tmp1_r = vec3_r >> 2;
tmp1_l = vec3_l >> 2;
tmp1_r += vec0_r;
tmp1_l += vec0_l;
tmp3_r = vec2_r >> 2;
tmp3_l = vec2_l >> 2;
tmp3_r += vec1_r;
tmp3_l += vec1_l;
tmp5_r = vec1_r >> 2;
tmp5_l = vec1_l >> 2;
tmp5_r -= vec2_r;
tmp5_l -= vec2_l;
tmp7_r = vec0_r >> 2;
tmp7_l = vec0_l >> 2;
tmp7_r = vec3_r - tmp7_r;
tmp7_l = vec3_l - tmp7_l;
BUTTERFLY_4( tmp0_r, tmp0_l, tmp7_l, tmp7_r,
res0_r, res0_l, res7_l, res7_r );
BUTTERFLY_4( tmp2_r, tmp2_l, tmp5_l, tmp5_r,
res1_r, res1_l, res6_l, res6_r );
BUTTERFLY_4( tmp4_r, tmp4_l, tmp3_l, tmp3_r,
res2_r, res2_l, res5_l, res5_r );
BUTTERFLY_4( tmp6_r, tmp6_l, tmp1_l, tmp1_r,
res3_r, res3_l, res4_l, res4_r );
SRA_4V( res0_r, res0_l, res1_r, res1_l, 6 );
SRA_4V( res2_r, res2_l, res3_r, res3_l, 6 );
SRA_4V( res4_r, res4_l, res5_r, res5_l, 6 );
SRA_4V( res6_r, res6_l, res7_r, res7_l, 6 );
PCKEV_H4_SH( res0_l, res0_r, res1_l, res1_r, res2_l, res2_r, res3_l, res3_r,
res0, res1, res2, res3 );
PCKEV_H4_SH( res4_l, res4_r, res5_l, res5_r, res6_l, res6_r, res7_l, res7_r,
res4, res5, res6, res7 );
LD_SB8( p_dst, i_dst_stride,
dst0, dst1, dst2, dst3,
dst4, dst5, dst6, dst7 );
ILVR_B4_SH( zeros, dst0, zeros, dst1, zeros, dst2, zeros, dst3,
tmp0, tmp1, tmp2, tmp3 );
ILVR_B4_SH( zeros, dst4, zeros, dst5, zeros, dst6, zeros, dst7,
tmp4, tmp5, tmp6, tmp7 );
ADD4( res0, tmp0, res1, tmp1, res2, tmp2, res3, tmp3,
res0, res1, res2, res3 );
ADD4( res4, tmp4, res5, tmp5, res6, tmp6, res7, tmp7,
res4, res5, res6, res7 );
CLIP_SH4_0_255( res0, res1, res2, res3 );
CLIP_SH4_0_255( res4, res5, res6, res7 );
PCKEV_B4_SB( res1, res0, res3, res2, res5, res4, res7, res6,
dst0, dst1, dst2, dst3 );
ST8x4_UB( dst0, dst1, p_dst, i_dst_stride );
p_dst += ( 4 * i_dst_stride );
ST8x4_UB( dst2, dst3, p_dst, i_dst_stride );
}
static void avc_dequant_8x8_msa( int16_t *p_dct, int32_t pi_dequant_mf[6][64],
int32_t i_qp )
{
const int32_t i_mf = i_qp % 6;
const int32_t q_bits = i_qp / 6 - 6;
v8i16 dct0, dct1, dct2, dct3, dct4, dct5, dct6, dct7;
v4i32 dequant_m_f0, dequant_m_f1, dequant_m_f2, dequant_m_f3;
v4i32 dequant_m_f4, dequant_m_f5, dequant_m_f6, dequant_m_f7;
v4i32 dequant_m_f8, dequant_m_f9, dequant_m_f10, dequant_m_f11;
v4i32 dequant_m_f12, dequant_m_f13, dequant_m_f14, dequant_m_f15;
LD_SH8( p_dct, 8, dct0, dct1, dct2, dct3, dct4, dct5, dct6, dct7 );
LD_SW2( pi_dequant_mf[i_mf], 4, dequant_m_f0, dequant_m_f1 );
LD_SW2( pi_dequant_mf[i_mf] + 8, 4, dequant_m_f2, dequant_m_f3 );
LD_SW2( pi_dequant_mf[i_mf] + 16, 4, dequant_m_f4, dequant_m_f5 );
LD_SW2( pi_dequant_mf[i_mf] + 24, 4, dequant_m_f6, dequant_m_f7 );
LD_SW2( pi_dequant_mf[i_mf] + 32, 4, dequant_m_f8, dequant_m_f9 );
LD_SW2( pi_dequant_mf[i_mf] + 40, 4, dequant_m_f10, dequant_m_f11 );
LD_SW2( pi_dequant_mf[i_mf] + 48, 4, dequant_m_f12, dequant_m_f13 );
LD_SW2( pi_dequant_mf[i_mf] + 56, 4, dequant_m_f14, dequant_m_f15 );
if( q_bits >= 0 )
{
v8i16 q_bits_vec;
v8i16 dequant_mf_h0, dequant_mf_h1, dequant_mf_h2, dequant_mf_h3;
v8i16 dequant_mf_h4, dequant_mf_h5, dequant_mf_h6, dequant_mf_h7;
q_bits_vec = __msa_fill_h( q_bits );
PCKEV_H4_SH( dequant_m_f1, dequant_m_f0, dequant_m_f3, dequant_m_f2,
dequant_m_f5, dequant_m_f4, dequant_m_f7, dequant_m_f6,
dequant_mf_h0, dequant_mf_h1,
dequant_mf_h2, dequant_mf_h3 );
PCKEV_H4_SH( dequant_m_f9, dequant_m_f8, dequant_m_f11, dequant_m_f10,
dequant_m_f13, dequant_m_f12, dequant_m_f15, dequant_m_f14,
dequant_mf_h4, dequant_mf_h5,
dequant_mf_h6, dequant_mf_h7 );
dct0 *= dequant_mf_h0;
dct1 *= dequant_mf_h1;
dct2 *= dequant_mf_h2;
dct3 *= dequant_mf_h3;
dct4 *= dequant_mf_h4;
dct5 *= dequant_mf_h5;
dct6 *= dequant_mf_h6;
dct7 *= dequant_mf_h7;
SLLI_4V( dct0, dct1, dct2, dct3, q_bits_vec );
SLLI_4V( dct4, dct5, dct6, dct7, q_bits_vec );
ST_SH8( dct0, dct1, dct2, dct3, dct4, dct5, dct6, dct7, p_dct, 8 );
}
else
{
const int32_t q_bits_add = 1 << ( -q_bits - 1 );
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
v4i32 dct_signed_w4, dct_signed_w5, dct_signed_w6, dct_signed_w7;
v4i32 dct_signed_w8, dct_signed_w9, dct_signed_w10, dct_signed_w11;
v4i32 dct_signed_w12, dct_signed_w13, dct_signed_w14, dct_signed_w15;
v4i32 q_bits_vec, q_bits_vec_add;
q_bits_vec_add = __msa_fill_w( q_bits_add );
q_bits_vec = __msa_fill_w( -q_bits );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
UNPCK_SH_SW( dct2, dct_signed_w4, dct_signed_w5 );
UNPCK_SH_SW( dct3, dct_signed_w6, dct_signed_w7 );
UNPCK_SH_SW( dct4, dct_signed_w8, dct_signed_w9 );
UNPCK_SH_SW( dct5, dct_signed_w10, dct_signed_w11 );
UNPCK_SH_SW( dct6, dct_signed_w12, dct_signed_w13 );
UNPCK_SH_SW( dct7, dct_signed_w14, dct_signed_w15 );
dct_signed_w0 *= dequant_m_f0;
dct_signed_w1 *= dequant_m_f1;
dct_signed_w2 *= dequant_m_f2;
dct_signed_w3 *= dequant_m_f3;
dct_signed_w4 *= dequant_m_f4;
dct_signed_w5 *= dequant_m_f5;
dct_signed_w6 *= dequant_m_f6;
dct_signed_w7 *= dequant_m_f7;
dct_signed_w8 *= dequant_m_f8;
dct_signed_w9 *= dequant_m_f9;
dct_signed_w10 *= dequant_m_f10;
dct_signed_w11 *= dequant_m_f11;
dct_signed_w12 *= dequant_m_f12;
dct_signed_w13 *= dequant_m_f13;
dct_signed_w14 *= dequant_m_f14;
dct_signed_w15 *= dequant_m_f15;
dct_signed_w0 += q_bits_vec_add;
dct_signed_w1 += q_bits_vec_add;
dct_signed_w2 += q_bits_vec_add;
dct_signed_w3 += q_bits_vec_add;
dct_signed_w4 += q_bits_vec_add;
dct_signed_w5 += q_bits_vec_add;
dct_signed_w6 += q_bits_vec_add;
dct_signed_w7 += q_bits_vec_add;
dct_signed_w8 += q_bits_vec_add;
dct_signed_w9 += q_bits_vec_add;
dct_signed_w10 += q_bits_vec_add;
dct_signed_w11 += q_bits_vec_add;
dct_signed_w12 += q_bits_vec_add;
dct_signed_w13 += q_bits_vec_add;
dct_signed_w14 += q_bits_vec_add;
dct_signed_w15 += q_bits_vec_add;
SRA_4V( dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3,
q_bits_vec );
SRA_4V( dct_signed_w4, dct_signed_w5, dct_signed_w6, dct_signed_w7,
q_bits_vec );
SRA_4V( dct_signed_w8, dct_signed_w9, dct_signed_w10, dct_signed_w11,
q_bits_vec );
SRA_4V( dct_signed_w12, dct_signed_w13, dct_signed_w14, dct_signed_w15,
q_bits_vec );
PCKEV_H4_SH( dct_signed_w1, dct_signed_w0, dct_signed_w3, dct_signed_w2,
dct_signed_w5, dct_signed_w4, dct_signed_w7, dct_signed_w6,
dct0, dct1, dct2, dct3 );
PCKEV_H4_SH( dct_signed_w9, dct_signed_w8, dct_signed_w11,
dct_signed_w10, dct_signed_w13, dct_signed_w12,
dct_signed_w15, dct_signed_w14, dct4, dct5, dct6, dct7 );
ST_SH8( dct0, dct1, dct2, dct3, dct4, dct5, dct6, dct7, p_dct, 8 );
}
}
static int32_t avc_quant_8x8_msa( int16_t *p_dct, uint16_t *p_mf,
uint16_t *p_bias )
{
int32_t non_zero = 0;
v8i16 dct0, dct1, dct2, dct3;
v8i16 zero = { 0 };
v8i16 dct0_mask, dct1_mask, dct2_mask, dct3_mask;
v8i16 dct_h0, dct_h1, dct_h2, dct_h3, mf_h0, mf_h1, mf_h2, mf_h3;
v8i16 bias_h0, bias_h1, bias_h2, bias_h3;
v4i32 dct_w0, dct_w1, dct_w2, dct_w3, dct_w4, dct_w5, dct_w6, dct_w7;
v4i32 dct_signed_w0, dct_signed_w1, dct_signed_w2, dct_signed_w3;
v4i32 dct_signed_w4, dct_signed_w5, dct_signed_w6, dct_signed_w7;
v4i32 mf_vec0, mf_vec1, mf_vec2, mf_vec3;
v4i32 mf_vec4, mf_vec5, mf_vec6, mf_vec7;
v4i32 bias0, bias1, bias2, bias3, bias4, bias5, bias6, bias7;
LD_SH4( p_dct, 8, dct0, dct1, dct2, dct3 );
dct0_mask = __msa_clei_s_h( dct0, 0 );
dct1_mask = __msa_clei_s_h( dct1, 0 );
dct2_mask = __msa_clei_s_h( dct2, 0 );
dct3_mask = __msa_clei_s_h( dct3, 0 );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
UNPCK_SH_SW( dct2, dct_signed_w4, dct_signed_w5 );
UNPCK_SH_SW( dct3, dct_signed_w6, dct_signed_w7 );
LD_SH4( p_bias, 8, bias_h0, bias_h1, bias_h2, bias_h3 );
ILVR_H4_SW( zero, bias_h0, zero, bias_h1, zero, bias_h2, zero, bias_h3,
bias0, bias2, bias4, bias6 );
ILVL_H4_SW( zero, bias_h0, zero, bias_h1, zero, bias_h2, zero, bias_h3,
bias1, bias3, bias5, bias7 );
LD_SH4( p_mf, 8, mf_h0, mf_h1, mf_h2, mf_h3 );
ILVR_H4_SW( zero, mf_h0, zero, mf_h1, zero, mf_h2, zero, mf_h3,
mf_vec0, mf_vec2, mf_vec4, mf_vec6 );
ILVL_H4_SW( zero, mf_h0, zero, mf_h1, zero, mf_h2, zero, mf_h3,
mf_vec1, mf_vec3, mf_vec5, mf_vec7 );
dct_w0 = __msa_add_a_w( dct_signed_w0, bias0 );
dct_w1 = __msa_add_a_w( dct_signed_w1, bias1 );
dct_w2 = __msa_add_a_w( dct_signed_w2, bias2 );
dct_w3 = __msa_add_a_w( dct_signed_w3, bias3 );
dct_w4 = __msa_add_a_w( dct_signed_w4, bias4 );
dct_w5 = __msa_add_a_w( dct_signed_w5, bias5 );
dct_w6 = __msa_add_a_w( dct_signed_w6, bias6 );
dct_w7 = __msa_add_a_w( dct_signed_w7, bias7 );
dct_w0 *= mf_vec0;
dct_w1 *= mf_vec1;
dct_w2 *= mf_vec2;
dct_w3 *= mf_vec3;
dct_w4 *= mf_vec4;
dct_w5 *= mf_vec5;
dct_w6 *= mf_vec6;
dct_w7 *= mf_vec7;
SRA_4V( dct_w0, dct_w1, dct_w2, dct_w3, 16 );
SRA_4V( dct_w4, dct_w5, dct_w6, dct_w7, 16 );
PCKEV_H4_SH( dct_w1, dct_w0, dct_w3, dct_w2, dct_w5, dct_w4, dct_w7, dct_w6,
dct_h0, dct_h1, dct_h2, dct_h3 );
SUB4( zero, dct_h0, zero, dct_h1, zero, dct_h2, zero, dct_h3,
dct0, dct1, dct2, dct3 );
dct0 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h0,
( v16u8 ) dct0, ( v16u8 ) dct0_mask );
dct1 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h1,
( v16u8 ) dct1, ( v16u8 ) dct1_mask );
dct2 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h2,
( v16u8 ) dct2, ( v16u8 ) dct2_mask );
dct3 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h3,
( v16u8 ) dct3, ( v16u8 ) dct3_mask );
non_zero = HADD_SW_S32( ( v4u32 )( dct_h0 + dct_h1 + dct_h2 + dct_h3 ) );
ST_SH4( dct0, dct1, dct2, dct3, p_dct, 8 );
LD_SH4( p_dct + 32, 8, dct0, dct1, dct2, dct3 );
dct0_mask = __msa_clei_s_h( dct0, 0 );
dct1_mask = __msa_clei_s_h( dct1, 0 );
dct2_mask = __msa_clei_s_h( dct2, 0 );
dct3_mask = __msa_clei_s_h( dct3, 0 );
UNPCK_SH_SW( dct0, dct_signed_w0, dct_signed_w1 );
UNPCK_SH_SW( dct1, dct_signed_w2, dct_signed_w3 );
UNPCK_SH_SW( dct2, dct_signed_w4, dct_signed_w5 );
UNPCK_SH_SW( dct3, dct_signed_w6, dct_signed_w7 );
LD_SH4( p_bias + 32, 8, bias_h0, bias_h1, bias_h2, bias_h3 );
ILVR_H4_SW( zero, bias_h0, zero, bias_h1, zero, bias_h2, zero, bias_h3,
bias0, bias2, bias4, bias6 );
ILVL_H4_SW( zero, bias_h0, zero, bias_h1, zero, bias_h2, zero, bias_h3,
bias1, bias3, bias5, bias7 );
LD_SH4( p_mf + 32, 8, mf_h0, mf_h1, mf_h2, mf_h3 );
ILVR_H4_SW( zero, mf_h0, zero, mf_h1, zero, mf_h2, zero, mf_h3,
mf_vec0, mf_vec2, mf_vec4, mf_vec6 );
ILVL_H4_SW( zero, mf_h0, zero, mf_h1, zero, mf_h2, zero, mf_h3,
mf_vec1, mf_vec3, mf_vec5, mf_vec7 );
dct_w0 = __msa_add_a_w( dct_signed_w0, bias0 );
dct_w1 = __msa_add_a_w( dct_signed_w1, bias1 );
dct_w2 = __msa_add_a_w( dct_signed_w2, bias2 );
dct_w3 = __msa_add_a_w( dct_signed_w3, bias3 );
dct_w4 = __msa_add_a_w( dct_signed_w4, bias4 );
dct_w5 = __msa_add_a_w( dct_signed_w5, bias5 );
dct_w6 = __msa_add_a_w( dct_signed_w6, bias6 );
dct_w7 = __msa_add_a_w( dct_signed_w7, bias7 );
dct_w0 *= mf_vec0;
dct_w1 *= mf_vec1;
dct_w2 *= mf_vec2;
dct_w3 *= mf_vec3;
dct_w4 *= mf_vec4;
dct_w5 *= mf_vec5;
dct_w6 *= mf_vec6;
dct_w7 *= mf_vec7;
SRA_4V( dct_w0, dct_w1, dct_w2, dct_w3, 16 );
SRA_4V( dct_w4, dct_w5, dct_w6, dct_w7, 16 );
PCKEV_H2_SH( dct_w1, dct_w0, dct_w3, dct_w2, dct_h0, dct_h1 );
PCKEV_H2_SH( dct_w5, dct_w4, dct_w7, dct_w6, dct_h2, dct_h3 );
SUB4( zero, dct_h0, zero, dct_h1, zero, dct_h2, zero, dct_h3,
dct0, dct1, dct2, dct3 );
dct0 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h0,
( v16u8 ) dct0, ( v16u8 ) dct0_mask );
dct1 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h1,
( v16u8 ) dct1, ( v16u8 ) dct1_mask );
dct2 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h2,
( v16u8 ) dct2, ( v16u8 ) dct2_mask );
dct3 = ( v8i16 ) __msa_bmnz_v( ( v16u8 ) dct_h3,
( v16u8 ) dct3, ( v16u8 ) dct3_mask );
non_zero += HADD_SW_S32( ( v4u32 ) ( dct_h0 + dct_h1 + dct_h2 + dct_h3 ) );
ST_SH4( dct0, dct1, dct2, dct3, p_dct + 32, 8 );
return !!non_zero;
}
