/**
Sends a Module Synchronous Request (SREQ) message and retrieves the response. A SREQ is a message to
the Module that is immediately followed by a Synchronous Response (SRSP) message from the Module. As
opposed to an Asynchronous Request (AREQ) message, which does not have a SRSP. This is a private
method that gets wrapped by sendMessage() and spiPoll().
@pre Module has been initialized
@pre zmBuf contains a properly formatted message. No validation is done.
@post received data is written to zmBuf
@return if FAST_PROCESSOR is defined then MODULE_SUCCESS, else an error code. If FAST_PROCESSOR is not defined, then MODULE_SUCCESS.
*/
moduleResult_t sendSreq()
{
#ifdef FAST_PROCESSOR //NOTE: only enable if using a processor with sufficient speed (25MHz+)
uint32_t timeLeft1 = CHIP_SELECT_TO_SRDY_LOW_TIMEOUT;
uint32_t timeLeft2 = WAIT_FOR_SRSP_TIMEOUT;
SPI_SS_SET(); // Assert SS
while (SRDY_IS_HIGH() && (timeLeft1 != 0)) //wait until SRDY goes low
timeLeft1--;
if (timeLeft1 == 0) //SRDY did not go low in time, so return an error
return ZM_PHY_CHIP_SELECT_TIMEOUT;
timeFromChipSelectToSrdyLow = (CHIP_SELECT_TO_SRDY_LOW_TIMEOUT - timeLeft1);
spiWrite(zmBuf, (*zmBuf + 3)); // *bytes (first byte) is length after the first 3 bytes, all frames have at least the first 3 bytes
*zmBuf = 0; *(zmBuf+1) = 0; *(zmBuf+2) = 0; //poll message is 0,0,0
//NOTE: MRDY must remain asserted here, but can de-assert SS if the two signals are separate
/* Now: Data was sent, so we wait for Synchronous Response (SRSP) to be received.
This will be indicated by SRDY transitioning to high */
while (SRDY_IS_LOW() && (timeLeft2 != 0)) //wait for data
timeLeft2--;
if (timeLeft2 == 0)
return ZM_PHY_SRSP_TIMEOUT;
timeWaitingForSrsp = (WAIT_FOR_SRSP_TIMEOUT - timeLeft2);
//NOTE: if SS & MRDY are separate signals then can re-assert SS here.
spiWrite(zmBuf, 3);
if (*zmBuf > 0) // *bytes (first byte) contains number of bytes to receive
spiWrite(zmBuf+3, *zmBuf); //write-to-read: read data into buffer
SPI_SS_CLEAR();
return 0;
#else // In a slow processor there's not enough time to set up the timeout so there will be errors
SPI_SS_SET();
while (SRDY_IS_HIGH()) ; //wait until SRDY goes low
spiWrite(zmBuf, (*zmBuf + 3)); // *bytes (first byte) is length after the first 3 bytes, all frames have at least the first 3 bytes
*zmBuf = 0; *(zmBuf+1) = 0; *(zmBuf+2) = 0; //poll message is 0,0,0
//NOTE: MRDY must remain asserted here, but can de-assert SS if the two signals are separate
//Now: Data was sent, wait for Synchronous Response (SRSP)
while (SRDY_IS_LOW()) ; //wait for data
//NOTE: if SS & MRDY are separate signals then can re-assert SS here.
spiWrite(zmBuf, 3);
if (*zmBuf > 0) // *bytes (first byte) contains number of bytes to receive
spiWrite(zmBuf+3, *zmBuf); //write-to-read: read data into buffer
SPI_SS_CLEAR(); // re-assert MRDY and SS
return MODULE_SUCCESS;
#endif
}
/** Use this to verify that the SPI port is configured correctly and writing bytes
Use a logic analyzer or scope and view the bytes being written.
The ZNP won't do anything but you'll be able to determine whether the SPI port is working.
Configure logic analyzer to trigger on a 1->0 transition on CS.
Verify that you're seeing the bytes written out the SPI port.
*/
int main( void )
{
halInit(); //Initialize hardware
halSpiInitZnp();
halInit();
printf("Test ZNP Reset\r\n");
RADIO_OFF();
delayMs(1);
RADIO_ON();
#define TEST_SRDY_INTERVAL_MS 1 //check SRDY every 100 mSec
#define TEST_SRDY_TIMEOUT_MS 1000
unsigned int elapsedTime = 0; //now, poll for SRDY going low...
do
{
delayMs(TEST_SRDY_INTERVAL_MS);
elapsedTime += TEST_SRDY_INTERVAL_MS;
}
while ((elapsedTime < TEST_SRDY_TIMEOUT_MS) && (SRDY_IS_HIGH()));
if (SRDY_IS_LOW())
{
printf("Test PASSED - SRDY went low after approximately %umS\r\n", elapsedTime);
}
else
{
printf("ERROR - SRDY never went low\r\n");
}
printf("SPI Write Test\r\n");
#define TEST_DATA {0x05, 0x04, 0x03, 0x02, 0x01, 0x00}
#define TEST_DATA_LENGTH 6
unsigned char test[] = TEST_DATA;
spiWrite(test, TEST_DATA_LENGTH);
printf("Done!\r\n");
}
/** This utility will toggle the reset line of the ZNP and determine whether the ZNP firmware is loaded.
When using SPI, toggling the reset line should cause SRDY to go high after approx. 400mSec to indicate a SYS_RESET_IND message.
This utility doesn't read the SPI bytes, just checks the SRDY line.
Verify that the pin connected to the hardware reset of the ZNP is pulled down for 1mSec.
Configure logic analyzer to trigger on a 1->0 transition on ZNP reset line*/
int main( void )
{
halInit();
printf("Test ZNP Reset\r\n");
RADIO_OFF();
delayMs(1);
RADIO_ON();
#define TEST_SRDY_INTERVAL_MS 1 //check SRDY every 100 mSec
#define TEST_SRDY_TIMEOUT_MS 1000
unsigned int elapsedTime = 0; //now, poll for SRDY going low...
do
{
delayMs(TEST_SRDY_INTERVAL_MS);
elapsedTime += TEST_SRDY_INTERVAL_MS;
}
while ((elapsedTime < TEST_SRDY_TIMEOUT_MS) && (SRDY_IS_HIGH()));
if (SRDY_IS_LOW())
{
printf("Test PASSED - SRDY went low after approximately %umS\r\n", elapsedTime);
}
else
{
printf("ERROR - SRDY never went low\r\n");
}
}
/** From znp_interface_spi.c, implemented here to avoid pesky dependencies */
signed int sendSreq()
{
SPI_SS_SET();
while (SRDY_IS_HIGH()) ; //wait until SRDY goes low
spiWrite(znpBuf, (*znpBuf + 3)); // *bytes (first byte) is length after the first 3 bytes, all frames have at least the first 3 bytes
*znpBuf = 0; *(znpBuf+1) = 0; *(znpBuf+2) = 0; //poll message is 0,0,0
//SPI_SS_CLEAR(); //NOTE: MRDY must remain asserted here, but can de-assert SS if the two signals are separate
while (SRDY_IS_LOW()) ; //wait for data
//SPI_SS_SET(); //NOTE: if SS & MRDY are separate signals then can re-assert SS here.
spiWrite(znpBuf, 3);
if (*znpBuf > 0) // *bytes (first byte) contains number of bytes to receive
spiWrite(znpBuf+3, *znpBuf); //write-to-read: read data into buffer
SPI_SS_CLEAR();
return 0;
}
/** Whether the module has a message waiting to be retrieved.
@return true (1) if there is a complete message ready for processing, or 0 otherwise.
*/
uint8_t moduleHasMessageWaiting()
{
return (SRDY_IS_LOW());
}
