/*#####################################################*/ void _mcspi_close(new_mcspi *McspiStruct) { SSIDisable(McspiStruct->BaseAddr); switch(McspiStruct->McspiNr) { case 0: IOCPortConfigureSet(McspiStruct->SckPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->SckPin); IOCPortConfigureSet(McspiStruct->MisoPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MisoPin); IOCPortConfigureSet(McspiStruct->MosiPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MosiPin); IOCPortConfigureSet(McspiStruct->CsPin[0], IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->CsPin[0]); SSIConfigSetExpClk(SSI0_BASE, CoreFreq, SSI_FRF_MOTO_MODE_0, McspiStruct->Mode, McspiStruct->ClkDiv[McspiStruct->McspiNr], McspiStruct->WordSize); McspiStruct->BaseAddr = 0; break; case 1: IOCPortConfigureSet(McspiStruct->SckPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->SckPin); IOCPortConfigureSet(McspiStruct->MisoPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MisoPin); IOCPortConfigureSet(McspiStruct->MosiPin, IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MosiPin); IOCPortConfigureSet(McspiStruct->CsPin[0], IOC_PORT_GPIO, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->CsPin[0]); SSIConfigSetExpClk(SSI1_BASE, CoreFreq, SSI_FRF_MOTO_MODE_0, McspiStruct->Mode, McspiStruct->ClkDiv[McspiStruct->McspiNr], McspiStruct->WordSize); McspiStruct->BaseAddr = 0; break; } }
void init_periph() { //initialize SSI0 - SD card SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlPeripheralReset(SYSCTL_PERIPH_SSI0); SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SysCtlClockGet()/4, 8); SSIEnable(SSI0_BASE); SSIDataPut(SSI0_BASE, 0xff); SSIDataPut(SSI0_BASE, 0xff); SSIDataPut(SSI0_BASE, 0xff); //Initialize SSI1 - VS Decoders SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1); SysCtlPeripheralReset(SYSCTL_PERIPH_SSI1); SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, SysCtlClockGet()/4, 8); SSIEnable(SSI1_BASE); SSIDataPut(SSI1_BASE, 0xff); SSIDataPut(SSI1_BASE, 0xff); SSIDataPut(SSI1_BASE, 0xff); //Initialize I2C0 - RTC SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C0); SysCtlPeripheralReset(SYSCTL_PERIPH_I2C0); return; }
int main() { SysCtlClockSet(SYSCTL_SYSDIV_2_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_MAIN); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); GPIOPinConfigure(GPIO_PB4_SSI2CLK); GPIOPinConfigure(GPIO_PB7_SSI2TX); GPIOPinTypeSSI(GPIO_PORTB_BASE,GPIO_PIN_4|GPIO_PIN_7); SSIConfigSetExpClk(SSI2_BASE,SysCtlClockGet(),SSI_FRF_MOTO_MODE_0,SSI_MODE_MASTER,2000000,8); SSIEnable(SSI2_BASE); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_2|GPIO_PIN_3); GPIOPinWrite(GPIO_PORTA_BASE,GPIO_PIN_2,0); GPIOPinWrite(GPIO_PORTA_BASE,GPIO_PIN_3,0); GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_6); GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_6,0); while(1) { SSIDataPut(SSI2_BASE,0xAA); latch(); SysCtlDelay(SysCtlClockGet()/10); SSIDataPut(SSI2_BASE,0x55); latch(); SysCtlDelay(SysCtlClockGet()/10); } }
/** * Initializes the QSSI_COMM port to transmit or receive a data transmission * * \param RXmode - true - initialize QSSI_COMM to read as a slave * false - initialize QSSI_COMM to write as a master **/ void twe_initQSSI(uint32_t SysClkFreq, bool RXmode) { // Enable Peripherals MAP_SysCtlPeripheralEnable(twe_QSSI_COMM_PERIPH); MAP_SysCtlPeripheralEnable(twe_QSSI_COMM_CLK_FSS_GPIO_PERIPH); MAP_SysCtlPeripheralEnable(twe_QSSI_COMM_XDAT01_GPIO_PERIPH); MAP_SysCtlPeripheralEnable(twe_QSSI_COMM_XDAT23_GPIO_PERIPH); // Set the pin muxing MAP_GPIOPinConfigure(twe_QSSI_COMM_CLK_PIN_CONFIG); MAP_GPIOPinConfigure(twe_QSSI_COMM_FSS_PIN_CONFIG); MAP_GPIOPinConfigure(twe_QSSI_COMM_DAT0_PIN_CONFIG); MAP_GPIOPinConfigure(twe_QSSI_COMM_DAT1_PIN_CONFIG); MAP_GPIOPinConfigure(twe_QSSI_COMM_DAT2_PIN_CONFIG); MAP_GPIOPinConfigure(twe_QSSI_COMM_DAT3_PIN_CONFIG); MAP_GPIOPinTypeSSI(twe_QSSI_COMM_CLK_FSS_GPIO_BASE, twe_QSSI_COMM_CLK_PIN | twe_QSSI_COMM_FSS_PIN); MAP_GPIOPinTypeSSI(twe_QSSI_COMM_XDAT01_GPIO_BASE, twe_QSSI_COMM_DAT0_PIN | twe_QSSI_COMM_DAT1_PIN); MAP_GPIOPinTypeSSI(twe_QSSI_COMM_XDAT23_GPIO_BASE, twe_QSSI_COMM_DAT2_PIN | twe_QSSI_COMM_DAT3_PIN); // Must be in SPI Mode0 for QSSI (Advanced) mode if(RXmode) { MAP_SSIConfigSetExpClk(twe_QSSI_COMM_BASE, SysClkFreq, SSI_FRF_MOTO_MODE_0, SSI_MODE_SLAVE, twe_QSSI_COMM_BAUD, 8); SSIAdvModeSet(twe_QSSI_COMM_BASE, SSI_ADV_MODE_QUAD_READ); SSIDataPut(twe_QSSI_COMM_BASE,0x00); } else { SSIConfigSetExpClk(twe_QSSI_COMM_BASE, SysClkFreq, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, twe_QSSI_COMM_BAUD, 8); SSIAdvModeSet(twe_QSSI_COMM_BASE, SSI_ADV_MODE_QUAD_WRITE); } // Enable SSI MAP_SSIEnable(twe_QSSI_COMM_BASE); //SSIDMAEnable(ADC_SSI_BASE, SSI_DMA_RX); // Enable SSI uDMA }
/** Initializes the Serial Peripheral Interface (SPI) interface to the Zigbee Module (ZM). @note Maximum module SPI clock speed is 4MHz. SPI port configured for clock polarity of 0, clock phase of 0, and MSB first. @note The Stellaris LaunchPad uses SSI2 to communicate with module @pre SPI pins configured correctly: - Clock, MOSI, MISO configured as SPI function - Chip Select configured as an output - SRDY configured as an input. @post SPI port is configured for communications with the module. */ void halSpiInitModule() { // Disable the SSI Port //SSIDisable(SSI2_BASE); // Reconfigure the SSI Port for Module operation. // Clock polarity = inactive is LOW (CPOL=0); Clock Phase = 0; MSB first; Master Mode, 2MHz, data is 8bits wide; SSIConfigSetExpClk(SSI2_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); // Enable the SSI Port SSIEnable(SSI2_BASE); // // Read any residual data from the SSI port. This makes sure the receive // FIFOs are empty, so we don't read any unwanted junk. This is done here // because the SPI SSI mode is full-duplex, which allows you to send and // receive at the same time. The SSIDataGetNonBlocking function returns // "true" when data was returned, and "false" when no data was returned. // The "non-blocking" function checks if there is any data in the receive // FIFO and does not "hang" if there isn't. // uint32_t ulDataRx[5]; while(SSIDataGetNonBlocking(SSI2_BASE, &ulDataRx[0])) { } // Don't select the module SPI_SS_CLEAR(); }
void EEPROM_Init() { SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); GPIOPinConfigure(GPIO_PD0_SSI1CLK); GPIOPinConfigure(GPIO_PD1_SSI1FSS); GPIOPinConfigure(GPIO_PD2_SSI1RX); GPIOPinConfigure(GPIO_PD3_SSI1TX); GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE,GPIO_PIN_CS); GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2|GPIO_PIN_3); SSIConfigSetExpClk(SSI1_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000, 8); SSIEnable(SSI1_BASE); memset(_eepromcachestr,0,EEPROMADDRSTRLEN+1); _iseepromenabled = EEPROM_Test(); }
/* ------------------------------------------------------------------------------------------------------ * ssi0_Init() * * Description : SPI sysctl init function. * * Argument(s) : none. * */ void BSP_SSI0_Init(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); SSIDisable(SSI0_BASE); /* Disable SSI0.*/ GPIOPinTypeSSI(GPIO_PORTA_BASE, /* Configure the SPI port*/ GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5); GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5, GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU); GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6); /* Configure the CS port*/ GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_6, GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU); SELECT(); DESELECT(); /* Deassert the SSI0 chip select */ SSIConfigSetExpClk(SSI0_BASE, /* Configure the SSI0 port */ SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 400000, 8); SSIEnable(SSI0_BASE); /* Enable SSI0.*/ }
int main(void) { uint32_t ui32Index; uint32_t ui32Data; SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); GPIOPinConfigure(GPIO_PA2_SSI0CLK); GPIOPinConfigure(GPIO_PA3_SSI0FSS); GPIOPinConfigure(GPIO_PA5_SSI0TX); GPIOPinTypeSSI(GPIO_PORTA_BASE,GPIO_PIN_5|GPIO_PIN_3|GPIO_PIN_2); SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 10000, 16); SSIEnable(SSI0_BASE); while(1) { for(ui32Index = 0; ui32Index < NUM_SSI_DATA; ui32Index++) { ui32Data = (Reverse(pui8DataTx[ui32Index]) << 8) + (1 << ui32Index); SSIDataPut(SSI0_BASE, ui32Data); while(SSIBusy(SSI0_BASE)) { } } } }
void Zone_Init(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); SSIDisable(SSI0_BASE); SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 2000000, 8); GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); SSIEnable(SSI0_BASE); while(SSIBusy(SSI0_BASE)) {} SSIDataPut(SSI0_BASE, ZONE_NONE); }
/* * ======== SPICC26XXDMA_hwInit ======== * This functions initializes the SPI hardware module. * * @pre Function assumes that the SPI handle is pointing to a hardware * module which has already been opened. */ static void SPICC26XXDMA_initHw(SPI_Handle handle) { SPICC26XX_Object *object; SPICC26XX_HWAttrs const *hwAttrs; Types_FreqHz freq; /* Get the pointer to the object and hwAttrs */ object = handle->object; hwAttrs = handle->hwAttrs; /* Disable SSI operation */ SSIDisable(hwAttrs->baseAddr); /* Disable SPI module interrupts */ SSIIntDisable(hwAttrs->baseAddr, SSI_RXOR | SSI_RXFF | SSI_RXTO | SSI_TXFF); SSIIntClear(hwAttrs->baseAddr, SSI_RXOR | SSI_RXTO); /* Set the SPI configuration */ BIOS_getCpuFreq(&freq); SSIConfigSetExpClk(hwAttrs->baseAddr, freq.lo, frameFormat[object->frameFormat], mode[object->mode], object->bitRate, object->dataSize); /* Print the configuration */ Log_print3(Diags_USER1, "SPI:(%p) CPU freq: %d; SPI freq to %d", hwAttrs->baseAddr, freq.lo, object->bitRate); }
//***************************************************************************** // //! Enable the SSI component of the OLED display driver. //! //! \param ulFrequency specifies the SSI Clock Frequency to be used. //! //! This function initializes the SSI interface to the OLED display. //! //! \return None. // //***************************************************************************** void RIT128x96x4Enable(unsigned long ulFrequency) { // // Disable the SSI port. // SSIDisable(SSI0_BASE); // // Configure the SSI0 port for master mode. // SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER, ulFrequency, 8); // // (Re)Enable SSI control of the FSS pin. // GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3); GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); // // Enable the SSI port. // SSIEnable(SSI0_BASE); // // Indicate that the RIT driver can use the SSI Port. // HWREGBITW(&g_ulSSIFlags, FLAG_SSI_ENABLED) = 1; }
/*#####################################################*/ bool _mcspi_set_baud(Mcspi_t *McspiStruct, unsigned long baud) { SSIDisable(McspiStruct->BaseAddr); SSIConfigSetExpClk(McspiStruct->BaseAddr, CoreFreq, SSI_FRF_MOTO_MODE_0, McspiStruct->Mode, baud, McspiStruct->WordSize); SSIEnable(McspiStruct->BaseAddr); McspiStruct->ClkDiv[McspiStruct->McspiNr] = baud; return true; }
static void prvSetupSPI(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI2); // set the SSI clock to the PIOSC clock SSIClockSourceSet(SSI2_BASE, SSI_CLOCK_SYSTEM); SSIConfigSetExpClk(SSI2_BASE, MAP_SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); MAP_SSIEnable(SSI2_BASE); }
//-------------------------------- void ssi_peripheral::Initialize() { MAP_SysCtlPeripheralEnable(m_rSpecification.m_nSSIPeripheral); MAP_SysCtlPeripheralEnable(m_rSpecification.m_nGPIOPeripheral); // Assign the SSI signals to the appropriate pins MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinRx); MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinClk); MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinTx); if (m_rSpecification.m_nSSIPinFss) { MAP_GPIOPinConfigure(m_rSpecification.m_nSSIPinFss); } // Set the GPIO AFSEL bits for the appropriate pins MAP_GPIOPinTypeSSI(m_rSpecification.m_nGPIOBase, m_rSpecification.m_nGPIOPins); // Set pull-up on the SSI Rx pin GPIOPadConfigSet(m_rSpecification.m_nGPIOBase, m_rSpecification.m_nGPIOInputPin, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); // Set standard on the SSI output pins GPIOPadConfigSet(m_rSpecification.m_nGPIOBase, m_rSpecification.m_nGPIOOutputPins, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD); // Configure the SSI peripheral SSIConfigSetExpClk(m_rSpecification.m_nSSIBase, SysCtlClockGet(), m_nProtocol, SSI_MODE_MASTER, m_nBitRate, 16); // Enable the SSI module. MAP_SSIEnable(m_rSpecification.m_nSSIBase); // Read any residual data from the SSI port. while (MAP_SSIDataGetNonBlocking(m_rSpecification.m_nSSIBase, &m_nDataRx[0])) { } m_bEmpty = true; // Enable the SSI interrupt switch (m_nDevice) { case ssi_peripheral::SSI0: g_pTheSSI0 = this; break; case ssi_peripheral::SSI1: g_pTheSSI1 = this; break; case ssi_peripheral::SSI2: g_pTheSSI2 = this; break; case ssi_peripheral::SSI3: g_pTheSSI3 = this; break; default: break; } SSIIntDisable(m_rSpecification.m_nSSIBase, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR); SSIIntClear(m_rSpecification.m_nSSIBase, SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR); (*((volatile uint32_t *) m_rSpecification.m_nSSI_CR1_R)) |= SSI_CR1_EOT; /* switch tx interrupt to eot int */ if (m_bNonBlocking) { SSIIntEnable(m_rSpecification.m_nSSIBase, SSI_TXFF); /* SSI_TXFF | SSI_RXFF | SSI_RXTO | SSI_RXOR */ MAP_IntEnable(m_rSpecification.m_nInterrupt); } }
//*************************************************// //initSSI //Prototype: void initSSI(void) //Description: init SPI module for communicate with vs1011e. //Returns: None. //*************************************************// void initSSI(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_4 | GPIO_PIN_5); GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_4| GPIO_PIN_5, GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD_WPU); SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 2000000, 8); SSIEnable(SSI0_BASE); }
void setup() { //--------------------- GENERAL --------------------- // Enable lazy stacking for interrupt handlers. This allows floating-point // instructions to be used within interrupt handlers, but at the expense of // extra stack usage. ROM_FPUEnable(); ROM_FPULazyStackingEnable(); // Set the clocking to run directly from the crystal. ROM_SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); ROM_IntMasterEnable(); ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); ROM_GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6); //--------------------- UART --------------------- ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0); GPIOPinConfigure(GPIO_PA0_U0RX); GPIOPinConfigure(GPIO_PA1_U0TX); ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1); // Configure the UART for 115,200, 8-N-1 operation. ROM_UARTConfigSetExpClk(UART0_BASE, ROM_SysCtlClockGet(), 115200, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); // Enable the UART interrupt. ROM_IntEnable(INT_UART0); ROM_UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT); //--------------------- SSI --------------------- SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); GPIOPinConfigure(GPIO_PA2_SSI0CLK); GPIOPinConfigure(GPIO_PA3_SSI0FSS); GPIOPinConfigure(GPIO_PA4_SSI0RX); GPIOPinConfigure(GPIO_PA5_SSI0TX); GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2); SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 10000, 8); SSIEnable(SSI0_BASE); }
static void sd_card_setspeed(int speed) { SSIDisable(SD_BASE_SSI); SSIConfigSetExpClk( SD_BASE_SSI, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, speed, 8 ); SSIEnable(SD_BASE_SSI); }
void SPI_init(){ SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); GPIOPinTypeSSI(GPIO_PORTA_BASE,GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5); GPIOPinConfigure(GPIO_PA2_SSI0CLK); GPIOPinConfigure(GPIO_PA4_SSI0RX); GPIOPinConfigure(GPIO_PA5_SSI0TX); SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SSIClockSourceSet(SSI0_BASE,SSI_CLOCK_PIOSC); SSIConfigSetExpClk(SSI0_BASE,SysCtlClockGet(),SSI_FRF_MOTO_MODE_0,SSI_MODE_MASTER,6000000,8); SSIEnable(SSI0_BASE); }
/* * Configura la interfaz SSI0 * * Notas: El formato Freescale SPI con SPO=1 y SPH=1 funciona bien con el TLV5616, * pero en cambio se configura con el formato TI, que es especifico para este integrado * */ void SSI0_Init(void) { #ifdef __CONFIGURACION_CON_REGISTROS__ volatile unsigned long delay; // Habilitar el modulo SSI y el puerto A SYSCTL_RCGCSSI_R |= SYSCTL_RCGCSSI_R0; SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R0; delay = SYSCTL_RCGCGPIO_R; // Esperar a que se activen los modulos // Configurar funciones alternativas en los pines PA2, 3, 5 GPIO_PORTA_AFSEL_R |= 0x2c; // Configurar la funcion de SSI en los pines GPIO_PORTA_PCTL_R = (GPIO_PORTA_PCTL_R & 0xff0f00ff) + GPIO_PCTL_PA2_SSI0CLK + GPIO_PCTL_PA3_SSI0FSS + GPIO_PCTL_PA5_SSI0TX; // Configurar los registros de funciones digitales, configurar pull-up o pull-down alternativamente GPIO_PORTA_AMSEL_R = 0; GPIO_PORTA_DEN_R |= 0x2c; // Configurar los formatos de trama // Deshabilitar el modulo SSI antes de hacer cambios SSI0_CR1_R &= ~SSI_CR1_SSE; // Connfigurar la operacion como maestro SSI0_CR1_R &= ~SSI_CR1_MS; // Configurar la fuente de reloj como reloj del sistema basado en un factor de division SSI0_CC_R &= ~SSI_CC_CS_M; // Configurar el prescaler para una frecuencia del modulo SSI de 1Mhz = 40MHz/40 SSI0_CPSR_R = (SSI0_CPSR_R & ~SSI_CPSR_CPSDVSR_M) + 20; // Configurar el serial clock rate, polaridad del reloj y fase, protocolo y tamaño de los datos SSI0_CR0_R &= ~(SSI_CR0_SCR_M); // SCR = 0 // SSI0_CR0_R |= SSI_CR0_SPO; // SPO = 1 // SSI0_CR0_R |= SSI_CR0_SPH; // SPH = 1 // SSI0_CR0_R = (SSI0_CR0_R & ~SSI_CR0_FRF_M) + SSI_CR0_FRF_MOTO; // Freescale SPI SSI0_CR0_R = (SSI0_CR0_R & ~SSI_CR0_FRF_M) + SSI_CR0_FRF_TI; // Texas Instruments Synchronous Serial Frame Format SSI0_CR0_R = (SSI0_CR0_R & ~SSI_CR0_DSS_M) + SSI_CR0_DSS_16; // 16 bits de datos // Finalmente, habilitar el modulo SPI SSI0_CR1_R |= SSI_CR1_SSE; #else // Habilitar el reloj SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); // Configurar los pines GPIOPinConfigure(GPIO_PA2_SSI0CLK); GPIOPinConfigure(GPIO_PA3_SSI0FSS); GPIOPinConfigure(GPIO_PA5_SSI0TX); GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5); // Configurar el modulo SSI y habilitarlo SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_TI, SSI_MODE_MASTER, 2000000, 16); SSIEnable(SSI0_BASE); #endif }
/** Initializes the Serial Peripheral Interface (SPI) interface to the Zigbee Module (ZM). @note Maximum module SPI clock speed is 4MHz. SPI port configured for clock polarity of 0, clock phase of 0, and MSB first. @note On the GW the Stellaris uses SSI0 to communicate with module @pre SPI pins configured correctly: - Clock, MOSI, MISO configured as SPI function - Chip Select configured as an output - SRDY configured as an input. @post SPI port is configured for communications with the module. */ void halSpiInitModule() { SSIDisable(SSI0_BASE); // Reconfigure the SSI Port for Module operation. // Clock polarity = inactive is LOW (CPOL=0); Clock Phase = 0; MSB first; Master Mode, 2mHz, data is 8bits wide; SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); // Enable the SSI Port. SSIEnable(SSI0_BASE); // Hold the module in reset SPI_SS_CLEAR(); }
void Ssi0Init(void) /*Act as Master*/ { SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); GPIOPinConfigure(GPIO_PA2_SSI0CLK); GPIOPinConfigure(GPIO_PA3_SSI0FSS); GPIOPinConfigure(GPIO_PA4_SSI0RX); // GPIOPinConfigure(GPIO_PA5_SSI0TX); GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2 | GPIO_PIN_4); SSIConfigSetExpClk(SSI0_BASE,SysCtlClockGet(),SSI_FRF_MOTO_MODE_2,SSI_MODE_MASTER,20000000,14); SSIEnable(SSI0_BASE); }
//------------------------------------LCD------------------------------------------- //初始化SPI端口 void SSI0_InitialSPI(void) { SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); GPIOPinConfigure(GPIO_PA2_SSI0CLK); GPIOPinConfigure(GPIO_PA3_SSI0FSS); GPIOPinConfigure(GPIO_PA5_SSI0TX); GPIOPinConfigure(GPIO_PA4_SSI0RX); GPIOPinTypeSSI(GPIO_PORTA_BASE,GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_2); SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER,50000, 16); SSIEnable(SSI0_BASE); SSI0_FlushFIFO(); }
bool _mcspi_open(new_mcspi *McspiStruct) { switch(McspiStruct->McspiNr) { case 0: SSIDisable(SSI0_BASE); IOCPortConfigureSet(McspiStruct->SckPin, IOC_PORT_MCU_SSI0_CLK, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->SckPin); IOCPortConfigureSet(McspiStruct->MisoPin, IOC_PORT_MCU_SSI0_RX, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_ENABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MisoPin); IOCPortConfigureSet(McspiStruct->MosiPin, IOC_PORT_MCU_SSI0_TX, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->MosiPin); IOCPortConfigureSet(McspiStruct->CsPin[0], IOC_PORT_MCU_SSI0_FSS, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->CsPin[0]); SSIConfigSetExpClk(SSI0_BASE, CoreFreq, SSI_FRF_MOTO_MODE_3, McspiStruct->Mode, McspiStruct->ClkDiv[McspiStruct->McspiNr], McspiStruct->WordSize); McspiStruct->BaseAddr = SSI0_BASE; break; case 1: SSIDisable(SSI1_BASE); IOCPortConfigureSet(McspiStruct->SckPin, IOC_PORT_MCU_SSI1_CLK, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->SckPin); IOCPortConfigureSet(McspiStruct->MisoPin, IOC_PORT_MCU_SSI1_RX, IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_ENABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) &= ~(1 << McspiStruct->MisoPin); IOCPortConfigureSet(McspiStruct->MosiPin, IOC_PORT_MCU_SSI1_TX, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->MosiPin); IOCPortConfigureSet(McspiStruct->CsPin[0], IOC_PORT_MCU_SSI1_FSS, IOC_CURRENT_8MA | IOC_STRENGTH_MAX | IOC_NO_IOPULL | IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | IOC_INT_DISABLE | IOC_IOMODE_NORMAL | IOC_NO_WAKE_UP | IOC_INPUT_DISABLE); HWREG(GPIO_BASE + GPIO_O_DOE31_0) |= (1 << McspiStruct->CsPin[0]); SSIConfigSetExpClk(SSI1_BASE, CoreFreq, SSI_FRF_MOTO_MODE_3, McspiStruct->Mode, McspiStruct->ClkDiv[McspiStruct->McspiNr], McspiStruct->WordSize); McspiStruct->BaseAddr = SSI1_BASE; break; default: return false; } SSIEnable(McspiStruct->BaseAddr); return true;//spi_enable(McspiStruct); }
void Ssi1_ad7567Init(void) /*Act as Master*/ { SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI1); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE); GPIOPinConfigure(GPIO_PE0_SSI1CLK); GPIOPinConfigure(GPIO_PE1_SSI1FSS); GPIOPinConfigure(GPIO_PE2_SSI1RX); GPIOPinConfigure(GPIO_PE3_SSI1TX); GPIOPinTypeSSI(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_1|GPIO_PIN_2 | GPIO_PIN_3 ); SSIConfigSetExpClk(SSI1_BASE,SysCtlClockGet(),SSI_FRF_MOTO_MODE_2,SSI_MODE_MASTER,20000000,14); SSIEnable(SSI1_BASE); }
/* * This configures the SSI. * Setups only the TX and configures the SSI to work at 6.4Mhz and 8bit packets. * It's 6.4Mhz because 6.4Mhz/8 is about 800Khz, the frequency needed for the WS2812B * */ void SPIInit() { // put your setup code here, to run once: SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0); SysCtlDelay(3); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA); SysCtlDelay(3); GPIOPinConfigure(GPIO_PA5_SSI0TX); GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5); SSIIntClear(SSI0_BASE,SSI_TXEOT); SSIConfigSetExpClk(SSI0_BASE, 80000000, SSI_FRF_MOTO_MODE_0,SSI_MODE_MASTER, 6400000, 8); SSIEnable(SSI0_BASE); }
void SPIController::configure(protocol_t protocol, mode_t mode, uint32_t bitrate, data_width_t data_width) { _data_width = data_width; SSIConfigSetExpClk(_base, ROM_SysCtlClockGet(), protocol, mode, bitrate, data_width); SSIEnable(_base); // empty receive fifos uint32_t dummy_read; while(SSIDataGetNonBlocking(_base, &dummy_read)) {} _read_mask = 0; for (uint8_t i=0; i<data_width; i++) { _read_mask |= (1<<i); } }
int main(void) { //Clock del sistema SysCtlClockSet(SYSCTL_SYSDIV_1 | SYSCTL_USE_OSC | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); //Configuro la UART1 para el GPS SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1); SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB); GPIOPinConfigure(GPIO_PB0_U1RX); GPIOPinConfigure(GPIO_PB1_U1TX); GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1); UARTConfigSetExpClk(UART1_BASE, SysCtlClockGet(), 9600, (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE)); //Uso el modulo SPI3 para el YEI3 SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); //Habilito el puerto correspondiente D SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD); //Configuro c/u de los pines para la funcion especificada GPIOPinConfigure(GPIO_PD0_SSI3CLK); GPIOPinConfigure(GPIO_PD1_SSI3FSS); GPIOPinConfigure(GPIO_PD2_SSI3RX); GPIOPinConfigure(GPIO_PD3_SSI3TX); GPIOPinTypeSSI(GPIO_PORTD_BASE, GPIO_PIN_3 | GPIO_PIN_2 | GPIO_PIN_1 | GPIO_PIN_0); //Configuro el SPI para trabajar a 115200bps SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 115200, 8); SSIEnable(SSI3_BASE); //Orden enviada al Yei return(0); }
//***************************************************************************** // // Enable the SSI Port for FatFs usage. // //***************************************************************************** void fs_enable(unsigned long ulFrequency) { // // Disable the SSI Port. // SSIDisable(SSI0_BASE); // // Reconfigure the SSI Port for Fat FS operation. // SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, ulFrequency, 8); // // Eanble the SSI Port. // SSIEnable(SSI0_BASE); }
void OrbitOledHostInit() { DelayInit(); /* Initialize SSI port 3. */ SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI3); GPIOPinTypeSSI(SCK_OLEDPort, SCK_OLED_PIN); GPIOPinTypeSSI(SDI_OLEDPort, SDI_OLED_PIN); GPIOPinConfigure(SDI_OLED); GPIOPinConfigure(SCK_OLED); SSIClockSourceSet(SSI3_BASE, SSI_CLOCK_SYSTEM); SSIConfigSetExpClk(SSI3_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 8000000, 8); SSIEnable(SSI3_BASE); /* Make power control pins be outputs with the supplies off */ GPIOPinWrite(VBAT_OLEDPort, VBAT_OLED, VBAT_OLED); GPIOPinWrite(VDD_OLEDPort, VDD_OLED, VDD_OLED); GPIOPinTypeGPIOOutput(VBAT_OLEDPort, VBAT_OLED); //VDD power control (1=off) GPIOPinTypeGPIOOutput(VDD_OLEDPort, VDD_OLED); //VBAT power control (1=off) /* Make the Data/Command select, Reset, and SSI CS pins be outputs. * The nDC_OLED pin is PD7 an is a special GPIO (it is an NMI pin) * Therefore, we must unlock it first: * 1. Write 0x4C4F434B to GPIOLOCK register to unlock the GPIO Commit register * 2. Write to appropriate bit in the Commit Register (bit 7) * 3. Re-lock the GPIOLOCK register */ HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = 0x4C4F434B; // unlock HWREG(GPIO_PORTD_BASE + GPIO_O_CR) |= 1 << 7; // allow writes HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = 0x0; // re-lock GPIOPinWrite(nDC_OLEDPort, nDC_OLED, nDC_OLED); GPIOPinTypeGPIOOutput(nDC_OLEDPort, nDC_OLED); GPIOPinWrite(nDC_OLEDPort, nDC_OLED, nDC_OLED); GPIOPinWrite(nRES_OLEDPort, nRES_OLED, nRES_OLED); GPIOPinTypeGPIOOutput(nRES_OLEDPort, nRES_OLED); GPIOPinWrite(nCS_OLEDPort, nCS_OLED, nCS_OLED); GPIOPinTypeGPIOOutput(nCS_OLEDPort, nCS_OLED); }
void Spi::enable(uint32_t baudrate) { GpioConfig& miso = miso_.getGpioConfig(); GpioConfig& mosi = mosi_.getGpioConfig(); GpioConfig& clk = clk_.getGpioConfig(); // GpioConfig& ncs = ncs_.getGpioConfig(); // Store baudrate in configuration if (baudrate != 0) { config_.baudrate = baudrate; } // Enable peripheral except in deep sleep modes (e.g. LPM1, LPM2, LPM3) SysCtrlPeripheralEnable(config_.peripheral); SysCtrlPeripheralSleepEnable(config_.peripheral); SysCtrlPeripheralDeepSleepDisable(config_.peripheral); // Reset peripheral previous to configuring it SSIDisable(config_.base); // Set IO clock as SPI0 clock source SSIClockSourceSet(config_.base, config_.clock); // Configure the MISO, MOSI, CLK and nCS pins as peripheral IOCPinConfigPeriphInput(miso.port, miso.pin, miso.ioc); IOCPinConfigPeriphOutput(mosi.port, mosi.pin, mosi.ioc); IOCPinConfigPeriphOutput(clk.port, clk.pin, clk.ioc); // IOCPinConfigPeriphOutput(ncs.port, ncs.pin, ncs.ioc); // Configure MISO, MOSI, CLK and nCS GPIOs GPIOPinTypeSSI(miso.port, miso.pin); GPIOPinTypeSSI(mosi.port, mosi.pin); GPIOPinTypeSSI(clk.port, clk.pin); // GPIOPinTypeSSI(ncs.port, ncs.pin); // Configure the SPI0 clock SSIConfigSetExpClk(config_.base, SysCtrlIOClockGet(), config_.protocol, \ config_.mode, config_.baudrate, config_.datawidth); // Enable the SPI0 module SSIEnable(config_.base); }