/**
* Initializes the QSSI RTX uDMA to transfer 4 bytes from memory to the QSSI TX FIFO
**/
void twe_initQSSIuDMAtx(void) {
SSIDMAEnable(twe_QSSI_COMM_BASE, SSI_DMA_TX);
uDMAChannelAssign(twe_QSSI_COMM_TX_UDMA_CHANNEL_ASSIGN);
// Place the uDMA channel attributes in a known state. These should already be disabled by default.
uDMAChannelAttributeDisable(twe_QSSI_COMM_TX_UDMA_CHANNEL,
UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT |
(UDMA_ATTR_HIGH_PRIORITY |
UDMA_ATTR_REQMASK));
// Configure the control parameters for the SSI2 RX channel. The channel
// will be used to transfer the ADC measurements to memory.
uDMAChannelControlSet(twe_QSSI_COMM_TX_UDMA_CHANNEL | UDMA_PRI_SELECT,
UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE |
UDMA_ARB_4);
// Set up the transfer parameters for the SSI2 Rx channel. This will
// configure the transfer buffers and the transfer size.
uDMAChannelTransferSet(twe_QSSI_COMM_TX_UDMA_CHANNEL | UDMA_PRI_SELECT,
UDMA_MODE_BASIC,
(void *)(twe_g_QSSItxBuffer), (void *)(TWE_UART_COMM_BASE + UART_O_DR),
4);
uDMAChannelAttributeEnable(twe_QSSI_COMM_TX_UDMA_CHANNEL, UDMA_ATTR_HIGH_PRIORITY);
//SSIIntEnable(ADC_SSI_BASE, SSI_DMARX);
//IntEnable(ADC_SSI_INT);
uDMAChannelEnable(twe_QSSI_COMM_TX_UDMA_CHANNEL);
}
/*
* ======== SPICC26XXDMA_configDMA ========
* This functions configures the transmit and receive DMA channels for a given
* SPI_Handle and SPI_Transaction
*
* @pre Function assumes that the handle and transaction is not NULL
*/
static void SPICC26XXDMA_configDMA(SPI_Handle handle, SPI_Transaction *transaction)
{
SPICC26XX_Object *object;
SPICC26XX_HWAttrs const *hwAttrs;
volatile tDMAControlTable *dmaControlTableEntry;
uint16_t numberOfBytes;
/* Get the pointer to the object and hwAttrs */
object = handle->object;
hwAttrs = handle->hwAttrs;
/* Calculate the number of bytes for the transfer */
numberOfBytes = ((uint16_t)(transaction->count) << (object->frameSize));
/* Setup RX side */
/* Set pointer to Rx control table entry */
dmaControlTableEntry = (hwAttrs->baseAddr == SSI0_BASE ? &dmaRxControlTableEntry0 : &dmaRxControlTableEntry1);
if (transaction->rxBuf) {
dmaControlTableEntry->ui32Control = dmaRxConfig[object->frameSize];
dmaControlTableEntry->pvDstEndAddr = (void *)((uint32_t)(transaction->rxBuf) + numberOfBytes - 1);
}
else {
dmaControlTableEntry->ui32Control = dmaNullConfig[object->frameSize];
dmaControlTableEntry->pvDstEndAddr = (void *) &(object->scratchBuf);
}
dmaControlTableEntry->pvSrcEndAddr = (void *)(hwAttrs->baseAddr + SSI_O_DR);
dmaControlTableEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)transaction->count);
/* Setup TX side */
/* Set pointer to Tx control table entry */
dmaControlTableEntry = (hwAttrs->baseAddr == SSI0_BASE ? &dmaTxControlTableEntry0 : &dmaTxControlTableEntry1);
if (transaction->txBuf) {
dmaControlTableEntry->ui32Control = dmaTxConfig[object->frameSize];
dmaControlTableEntry->pvSrcEndAddr = (void *)((uint32_t)(transaction->txBuf) + numberOfBytes - 1);
}
else {
dmaControlTableEntry->ui32Control = dmaNullConfig[object->frameSize];
dmaControlTableEntry->pvSrcEndAddr = (void *) &(hwAttrs->defaultTxBufValue);
}
dmaControlTableEntry->pvDstEndAddr = (void *)(hwAttrs->baseAddr + SSI_O_DR);
dmaControlTableEntry->ui32Control |= UDMACC26XX_SET_TRANSFER_SIZE((uint16_t)transaction->count);
/* Enable the channels */
UDMACC26XX_channelEnable(object->udmaHandle, (hwAttrs->rxChannelBitMask) | (hwAttrs->txChannelBitMask));
/* Enable the required DMA channels in the SPI module to start the transaction */
SSIDMAEnable(hwAttrs->baseAddr, SSI_DMA_TX | SSI_DMA_RX);
Log_print1(Diags_USER1,"SPI:(%p) DMA transfer enabled", hwAttrs->baseAddr);
Log_print5(Diags_USER2,"SPI:(%p) DMA transaction: %p, "
"rxBuf: %p; txBuf: %p; Count: %d",
hwAttrs->baseAddr,
(UArg)transaction,
(UArg)transaction->rxBuf,
(UArg)transaction->txBuf,
(UArg)transaction->count);
}
/**************************************************************************************************
* @fn npSpiUdmaPrepareRx
*
* @brief This function is called to set up uDMA for SPI RX. The uDMA and SPI must be
* initialized once already.
*
* input parameters
*
* None.
*
* output parameters
*
* None.
*
* @return None.
**************************************************************************************************
*/
static void npSpiUdmaPrepareRx(void)
{
uint32 ulDummy;
/* Flush the RX FIFO */
while(SSIDataGetNonBlocking(BSP_SPI_SSI_BASE, &ulDummy));
/* Prepare for the next one byte RX DMA */
uDMAChannelTransferSet(UDMA_CH10_SSI0RX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, SPI_DATA, npSpiBuf, 1);
uDMAChannelEnable(UDMA_CH10_SSI0RX);
/* Disable the TX channel in RX */
SSIDMADisable(BSP_SPI_SSI_BASE, SSI_DMA_TX);
SSIDMAEnable(BSP_SPI_SSI_BASE, SSI_DMA_RX);
}
/**************************************************************************************************
* @fn spi_tx
*
* @brief This function is called to send an SPI packet
*
* input parameters
*
* None.
*
* output parameters
*
* None.
*
* @return None.
**************************************************************************************************
*/
static void spi_tx(uint8* buf)
{
uint8 tx_len = buf[0] + 3;
osal_memcpy(npSpiBuf, buf, tx_len);
/* Disable the RX channel in TX */
SSIDMADisable(BSP_SPI_SSI_BASE, SSI_DMA_RX);
SSIDMAEnable(BSP_SPI_SSI_BASE, SSI_DMA_TX);
/* The transfer buffers and transfer size are now configured using BASIC mode */
uDMAChannelTransferSet(UDMA_CH11_SSI0TX | UDMA_PRI_SELECT,
UDMA_MODE_BASIC, npSpiBuf, SPI_DATA, tx_len);
/* Pull the SRDY pin high */
GPIOPinWrite(HAL_SPI_SRDY_BASE, HAL_SPI_SRDY_PIN, HAL_SPI_SRDY_PIN);
/* Enable the TX channel. */
uDMAChannelEnable(UDMA_CH11_SSI0TX);
}
/**************************************************************************************************
* @fn npSpiInit
*
* @brief This function is called to set up the SPI interface.
*
* input parameters
*
* None.
*
* output parameters
*
* None.
*
* @return None.
**************************************************************************************************
*/
void npSpiInit(void)
{
uint32 ulDummy;
if (ZNP_CFG1_UART == znpCfg1)
{
return;
}
/* Configure SRDY and deassert SRDY */
GPIOPinTypeGPIOOutput(HAL_SPI_SRDY_BASE, HAL_SPI_SRDY_PIN);
GPIOPinWrite(HAL_SPI_SRDY_BASE, HAL_SPI_SRDY_PIN, HAL_SPI_SRDY_PIN);
/* Configure MRDY and deassert MRDY */
GPIOPinTypeGPIOInput(HAL_SPI_MRDY_BASE, HAL_SPI_MRDY_PIN);
GPIOPinWrite(HAL_SPI_MRDY_BASE, HAL_SPI_MRDY_PIN, HAL_SPI_MRDY_PIN);
/* Enable SSI peripheral module */
SysCtrlPeripheralEnable(BSP_SPI_SSI_ENABLE_BM);
/* Delay is essential for this customer */
SysCtrlDelay(32);
/* Configure pin type */
GPIOPinTypeSSI(BSP_SPI_BUS_BASE, (BSP_SPI_MOSI | BSP_SPI_MISO | BSP_SPI_SCK | HAL_SPI_SS_PIN));
/* Map SSI signals to the correct GPIO pins and configure them as HW ctrl'd */
IOCPinConfigPeriphOutput(BSP_SPI_BUS_BASE, BSP_SPI_MISO, IOC_MUX_OUT_SEL_SSI0_TXD);
IOCPinConfigPeriphInput(BSP_SPI_BUS_BASE, BSP_SPI_SCK, IOC_CLK_SSIIN_SSI0);
IOCPinConfigPeriphInput(BSP_SPI_BUS_BASE, BSP_SPI_MOSI, IOC_SSIRXD_SSI0);
IOCPinConfigPeriphInput(BSP_SPI_BUS_BASE, HAL_SPI_SS_PIN, IOC_SSIFSSIN_SSI0);
/* Disable SSI function */
SSIDisable(BSP_SPI_SSI_BASE);
/* Set system clock as SSI clock source */
SSIClockSourceSet(BSP_SPI_SSI_BASE, SSI_CLOCK_SYSTEM);
/* Configure SSI module to Motorola/Freescale SPI mode 3 Slave:
* Polarity = 1, observed in scope from MSP430 master
* Phase = 1, observed in scope from MSP430 master
* Word size = 8 bits
* Clock = 2MHz, observed MSP430 master clock is 2049180Hz
*/
SSIConfigSetExpClk(BSP_SPI_SSI_BASE, SysCtrlClockGet(), SSI_FRF_MOTO_MODE_3,
SSI_MODE_SLAVE, 2000000UL, 8);
/* Register SPI uDMA complete interrupt */
SSIIntRegister(BSP_SPI_SSI_BASE, &npSpiUdmaCompleteIsr);
/* Enable uDMA complete interrupt for SPI RX and TX */
SSIDMAEnable(BSP_SPI_SSI_BASE, SSI_DMA_RX | SSI_DMA_TX);
/* Configure SPI priority */
IntPrioritySet(INT_SSI0, HAL_INT_PRIOR_SSI0);
IntPrioritySet(INT_GPIOB, HAL_INT_PRIOR_SSI_MRDY);
/* Enable the SSI function */
SSIEnable(BSP_SPI_SSI_BASE);
GPIOIntTypeSet(HAL_SPI_MRDY_BASE, HAL_SPI_MRDY_PIN, GPIO_BOTH_EDGES);
GPIOPortIntRegister(HAL_SPI_MRDY_BASE, *npSpiMrdyIsr);
GPIOPinIntEnable(HAL_SPI_MRDY_BASE, HAL_SPI_MRDY_PIN);
/* Initialize uDMA for SPI */
npSpiUdmaInit();
}
