void
starfire_pc_ittrans_init(int upaid)
{
paddr_t pa;
pa = STARFIRE_UPAID2UPS(upaid) | STARFIRE_PSI_BASE;
pa |= (STARFIRE_PSI_PCREG_OFF | STARFIRE_PC_INT_MAP);
/*
* Since we direct all interrupts to the boot processor, we
* simply program the port controller ITTR hardware with a
* single mapping.
*/
pa += CPU_UPAID * 0x10;
stwa(pa, ASI_PHYS_NON_CACHED, STARFIRE_UPAID2HWMID(cpu_myid()));
}
/*
* Setup and initialize the soft table that
* represent the Starfire interrupt target translation
* registers in the Port controller asics. There is one
* for each sysio/pci instance.
*/
void
pc_ittrans_init(int upa_id, caddr_t *ittptr_cookie)
{
int i;
uint64_t physaddr;
struct pc_ittrans_data *tmpptr;
ASSERT(ittptr_cookie != NULL);
/*
* Allocate the data structure to support starfire's
* interrupt target translations
*/
tmpptr = (struct pc_ittrans_data *)
kmem_zalloc(sizeof (struct pc_ittrans_data),
KM_SLEEP);
/* Initialize the ittrans lock */
mutex_init(&tmpptr->ittrans_lock, NULL, MUTEX_DEFAULT, NULL);
/*
* Construct the base physical address of the
* ITTR registers associated with this PC asics
*/
physaddr = STARFIRE_UPAID2UPS(upa_id);
physaddr |= (STARFIRE_PSI_BASE | STARFIRE_PSI_PCREG_OFF |
STARFIRE_PC_INT_MAP);
/*
* Initialize the ITTR table
* This soft table is used to represent the interrupt
* target translation hardware registers in the Starfire's
* PC asics. There are 32 slots and each slot consists of
* a mondovec regaddr entry and the physical address of
* the that ITT register. A empty slot is one whose
* mondovec entry is null. To reserve/use a slot for a
* particular intr mapping reg, we simply find
* a empty slot and write in the mondovec mapping
* regaddr into the mondovec field.
*/
for (i = 0; i < 32; i++) {
tmpptr->ittrans_mondovec[i] = NULL;
tmpptr->ittransreg_physaddr[i] = physaddr + i*16;
}
*ittptr_cookie = (caddr_t)tmpptr;
}
