static void i2c_event_handler(int port) { /* save and clear status */ i2c_sr1[port] = STM32_I2C_SR1(port); STM32_I2C_SR1(port) = 0; /* Confirm that you are not in master mode */ if (STM32_I2C_SR2(port) & (1 << 0)) { CPRINTS("slave ISR triggered in master mode, ignoring"); return; } /* transfer matched our slave address */ if (i2c_sr1[port] & (1 << 1)) { /* If it's a receiver slave */ if (!(STM32_I2C_SR2(port) & (1 << 2))) { dma_start_rx(dma_rx_option + port, sizeof(host_buffer), host_buffer); STM32_I2C_CR2(port) |= (1 << 11); rx_pending = 1; } /* cleared by reading SR1 followed by reading SR2 */ STM32_I2C_SR1(port); STM32_I2C_SR2(port); } else if (i2c_sr1[port] & (1 << 4)) { /* If it's a receiver slave */ if (!(STM32_I2C_SR2(port) & (1 << 2))) { /* Disable, and clear the DMA transfer complete flag */ dma_disable(DMAC_SLAVE_RX); dma_clear_isr(DMAC_SLAVE_RX); /* Turn off i2c's DMA flag */ STM32_I2C_CR2(port) &= ~(1 << 11); } /* clear STOPF bit by reading SR1 and then writing CR1 */ STM32_I2C_SR1(port); STM32_I2C_CR1(port) = STM32_I2C_CR1(port); } /* TxE event */ if (i2c_sr1[port] & (1 << 7)) { if (port == I2C2) { /* AP is waiting for EC response */ if (rx_pending) { i2c_process_command(); /* reset host buffer after end of transfer */ rx_pending = 0; } else { /* spurious read : return dummy value */ STM32_I2C_DR(port) = 0xec; } } } }
static void i2c_set_freq_port(const struct i2c_port_t *p) { int port = p->port; /* Disable port */ STM32_I2C_CR1(port) = 0; STM32_I2C_CR2(port) = 0; /* Set clock frequency */ switch (p->kbps) { case 1000: STM32_I2C_TIMINGR(port) = 0x50110103; break; case 400: STM32_I2C_TIMINGR(port) = 0x50330309; break; case 100: STM32_I2C_TIMINGR(port) = 0xB0420F13; break; default: /* unknown speed, defaults to 100kBps */ CPRINTS("I2C bad speed %d kBps", p->kbps); STM32_I2C_TIMINGR(port) = 0xB0420F13; } /* Enable port */ STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; }
static void i2c_init_port(unsigned int port) { const int i2c_clock_bit[] = {21, 22}; if (!(STM32_RCC_APB1ENR & (1 << i2c_clock_bit[port]))) { /* Only unwedge the bus if the clock is off */ if (i2c_claim(port) == EC_SUCCESS) { i2c_release(port); } /* enable I2C2 clock */ STM32_RCC_APB1ENR |= 1 << i2c_clock_bit[port]; } /* force reset of the i2c peripheral */ STM32_I2C_CR1(port) = 0x8000; STM32_I2C_CR1(port) = 0x0000; /* set clock configuration : standard mode (100kHz) */ STM32_I2C_CCR(port) = I2C_CCR; /* set slave address */ if (port == I2C2) STM32_I2C_OAR1(port) = I2C_ADDRESS; /* configuration : I2C mode / Periphal enabled, ACK enabled */ STM32_I2C_CR1(port) = (1 << 10) | (1 << 0); /* error and event interrupts enabled / input clock is 16Mhz */ STM32_I2C_CR2(port) = (1 << 9) | (1 << 8) | 0x10; /* clear status */ STM32_I2C_SR1(port) = 0; board_i2c_post_init(port); }
static void dump_i2c_reg(int port, const char *what) { CPRINTS("i2c CR1=%04x CR2=%04x SR1=%04x SR2=%04x %s", STM32_I2C_CR1(port), STM32_I2C_CR2(port), STM32_I2C_SR1(port), STM32_I2C_SR2(port), what); }
static int i2c_write_raw_slave(int port, void *buf, int len) { stm32_dma_chan_t *chan; int rv; /* we don't want to race with TxE interrupt event */ disable_i2c_interrupt(port); /* Configuring DMA1 channel DMAC_SLAVE_TX */ enable_ack(port); chan = dma_get_channel(DMAC_SLAVE_TX); dma_prepare_tx(dma_tx_option + port, len, buf); /* Start the DMA */ dma_go(chan); /* Configuring i2c to use DMA */ STM32_I2C_CR2(port) |= (1 << 11); if (in_interrupt_context()) { /* Poll for the transmission complete flag */ dma_wait(DMAC_SLAVE_TX); dma_clear_isr(DMAC_SLAVE_TX); } else { /* Wait for the transmission complete Interrupt */ dma_enable_tc_interrupt(DMAC_SLAVE_TX); rv = task_wait_event(DMA_TRANSFER_TIMEOUT_US); dma_disable_tc_interrupt(DMAC_SLAVE_TX); if (!(rv & TASK_EVENT_WAKE)) { CPRINTS("Slave timeout, resetting i2c"); i2c_init_port(port); } } dma_disable(DMAC_SLAVE_TX); STM32_I2C_CR2(port) &= ~(1 << 11); enable_i2c_interrupt(port); return len; }
static inline void dump_i2c_reg(int port) { #ifdef CONFIG_I2C_DEBUG CPRINTF("CR1 : %016b\n", STM32_I2C_CR1(port)); CPRINTF("CR2 : %016b\n", STM32_I2C_CR2(port)); CPRINTF("SR2 : %016b\n", STM32_I2C_SR2(port)); CPRINTF("SR1 : %016b\n", STM32_I2C_SR1(port)); CPRINTF("OAR1 : %016b\n", STM32_I2C_OAR1(port)); CPRINTF("OAR2 : %016b\n", STM32_I2C_OAR2(port)); CPRINTF("DR : %016b\n", STM32_I2C_DR(port)); CPRINTF("CCR : %016b\n", STM32_I2C_CCR(port)); CPRINTF("TRISE: %016b\n", STM32_I2C_TRISE(port)); #endif /* CONFIG_I2C_DEBUG */ }
static void i2c_set_freq_port(const struct i2c_port_t *p, enum stm32_i2c_clk_src src, enum i2c_freq freq) { int port = p->port; const uint32_t *regs = timingr_regs[src]; /* Disable port */ STM32_I2C_CR1(port) = 0; STM32_I2C_CR2(port) = 0; /* Set clock frequency */ STM32_I2C_TIMINGR(port) = regs[freq]; /* Enable port */ STM32_I2C_CR1(port) = STM32_I2C_CR1_PE; }
static void i2c_set_freq_port(const struct i2c_port_t *p) { int port = p->port; int freq = clock_get_freq(); /* Force peripheral reset and disable port */ STM32_I2C_CR1(port) = STM32_I2C_CR1_SWRST; STM32_I2C_CR1(port) = 0; /* Set clock frequency */ STM32_I2C_CCR(port) = freq / (2 * MSEC * p->kbps); STM32_I2C_CR2(port) = freq / SECOND; STM32_I2C_TRISE(port) = freq / SECOND + 1; /* Enable port */ STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; }
int i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_bytes, uint8_t *in, int in_bytes, int flags) { int rv = EC_SUCCESS; int i; ASSERT(out || !out_bytes); ASSERT(in || !in_bytes); /* Clear status */ STM32_I2C_ICR(port) = 0x3F38; STM32_I2C_CR2(port) = 0; if (out_bytes || !in_bytes) { /* Configure the write transfer */ STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) | slave_addr | (in_bytes == 0 ? STM32_I2C_CR2_AUTOEND : 0); /* let's go ... */ STM32_I2C_CR2(port) |= STM32_I2C_CR2_START; for (i = 0; i < out_bytes; i++) { rv = wait_isr(port, STM32_I2C_ISR_TXIS); if (rv) goto xfer_exit; /* Write next data byte */ STM32_I2C_TXDR(port) = out[i]; } } if (in_bytes) { if (out_bytes) { /* wait for completion of the write */ rv = wait_isr(port, STM32_I2C_ISR_TC); if (rv) goto xfer_exit; } /* Configure the read transfer */ STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | slave_addr | STM32_I2C_CR2_AUTOEND; /* START or repeated start */ STM32_I2C_CR2(port) |= STM32_I2C_CR2_START; for (i = 0; i < in_bytes; i++) { /* Wait for receive buffer not empty */ rv = wait_isr(port, STM32_I2C_ISR_RXNE); if (rv) goto xfer_exit; in[i] = STM32_I2C_RXDR(port); } } rv = wait_isr(port, STM32_I2C_ISR_STOP); if (rv) goto xfer_exit; xfer_exit: /* clear status */ STM32_I2C_ICR(port) = 0x3F38; /* On error, queue a stop condition */ if (rv) { /* queue a STOP condition */ STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP; /* wait for it to take effect */ /* Wait up to 100 us for bus idle */ for (i = 0; i < 10; i++) { if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY)) break; udelay(10); } /* * Allow bus to idle for at least one 100KHz clock = 10 us. * This allows slaves on the bus to detect bus-idle before * the next start condition. */ udelay(10); /* re-initialize the controller */ STM32_I2C_CR2(port) = 0; STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE; udelay(10); STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; } return rv; }
int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_bytes, uint8_t *in, int in_bytes, int flags) { int rv = EC_SUCCESS; int i; int xfer_start = flags & I2C_XFER_START; int xfer_stop = flags & I2C_XFER_STOP; #if defined(CONFIG_I2C_SCL_GATE_ADDR) && defined(CONFIG_I2C_SCL_GATE_PORT) if (port == CONFIG_I2C_SCL_GATE_PORT && slave_addr == CONFIG_I2C_SCL_GATE_ADDR) gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 1); #endif ASSERT(out || !out_bytes); ASSERT(in || !in_bytes); /* Clear status */ if (xfer_start) { STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; STM32_I2C_CR2(port) = 0; } if (out_bytes || !in_bytes) { /* * Configure the write transfer: if we are stopping then set * AUTOEND bit to automatically set STOP bit after NBYTES. * if we are not stopping, set RELOAD bit so that we can load * NBYTES again. if we are starting, then set START bit. */ STM32_I2C_CR2(port) = ((out_bytes & 0xFF) << 16) | slave_addr | ((in_bytes == 0 && xfer_stop) ? STM32_I2C_CR2_AUTOEND : 0) | ((in_bytes == 0 && !xfer_stop) ? STM32_I2C_CR2_RELOAD : 0) | (xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < out_bytes; i++) { rv = wait_isr(port, STM32_I2C_ISR_TXIS); if (rv) goto xfer_exit; /* Write next data byte */ STM32_I2C_TXDR(port) = out[i]; } } if (in_bytes) { if (out_bytes) { /* wait for completion of the write */ rv = wait_isr(port, STM32_I2C_ISR_TC); if (rv) goto xfer_exit; } /* * Configure the read transfer: if we are stopping then set * AUTOEND bit to automatically set STOP bit after NBYTES. * if we are not stopping, set RELOAD bit so that we can load * NBYTES again. if we were just transmitting, we need to * set START bit to send (re)start and begin read transaction. */ STM32_I2C_CR2(port) = ((in_bytes & 0xFF) << 16) | STM32_I2C_CR2_RD_WRN | slave_addr | (xfer_stop ? STM32_I2C_CR2_AUTOEND : 0) | (!xfer_stop ? STM32_I2C_CR2_RELOAD : 0) | (out_bytes || xfer_start ? STM32_I2C_CR2_START : 0); for (i = 0; i < in_bytes; i++) { /* Wait for receive buffer not empty */ rv = wait_isr(port, STM32_I2C_ISR_RXNE); if (rv) goto xfer_exit; in[i] = STM32_I2C_RXDR(port); } } /* * If we are stopping, then we already set AUTOEND and we should * wait for the stop bit to be transmitted. Otherwise, we set * the RELOAD bit and we should wait for transfer complete * reload (TCR). */ rv = wait_isr(port, xfer_stop ? STM32_I2C_ISR_STOP : STM32_I2C_ISR_TCR); if (rv) goto xfer_exit; xfer_exit: /* clear status */ if (xfer_stop) STM32_I2C_ICR(port) = STM32_I2C_ICR_ALL; /* On error, queue a stop condition */ if (rv) { /* queue a STOP condition */ STM32_I2C_CR2(port) |= STM32_I2C_CR2_STOP; /* wait for it to take effect */ /* Wait up to 100 us for bus idle */ for (i = 0; i < 10; i++) { if (!(STM32_I2C_ISR(port) & STM32_I2C_ISR_BUSY)) break; udelay(10); } /* * Allow bus to idle for at least one 100KHz clock = 10 us. * This allows slaves on the bus to detect bus-idle before * the next start condition. */ udelay(10); /* re-initialize the controller */ STM32_I2C_CR2(port) = 0; STM32_I2C_CR1(port) &= ~STM32_I2C_CR1_PE; udelay(10); STM32_I2C_CR1(port) |= STM32_I2C_CR1_PE; } #ifdef CONFIG_I2C_SCL_GATE_ADDR if (port == CONFIG_I2C_SCL_GATE_PORT && slave_addr == CONFIG_I2C_SCL_GATE_ADDR) gpio_set_level(CONFIG_I2C_SCL_GATE_GPIO, 0); #endif return rv; }
static inline void enable_i2c_interrupt(int port) { STM32_I2C_CR2(port) |= 3 << 8; }
static inline void disable_i2c_interrupt(int port) { STM32_I2C_CR2(port) &= ~(3 << 8); }