static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { /* FIXME */ struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; int ret, stype = SUBSTREAM_TYPE(substream); ret = 0; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: au_writel(AC97PCR_START(stype), AC97_PCR(pscdata)); au_sync(); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata)); au_sync(); break; default: ret = -EINVAL; } return ret; }
static int au1xi2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { struct au1xpsc_audio_data *ctx = snd_soc_dai_get_drvdata(dai); int stype = SUBSTREAM_TYPE(substream); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: /* power up */ WR(ctx, I2S_ENABLE, EN_D | EN_CE); WR(ctx, I2S_ENABLE, EN_CE); ctx->cfg |= (stype == PCM_TX) ? CFG_TN : CFG_RN; WR(ctx, I2S_CFG, ctx->cfg); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: ctx->cfg &= ~((stype == PCM_TX) ? CFG_TN : CFG_RN); WR(ctx, I2S_CFG, ctx->cfg); WR(ctx, I2S_ENABLE, EN_D); /* power off */ break; default: return -EINVAL; } return 0; }
static int au1xpsc_ac97_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; int ret, stype = SUBSTREAM_TYPE(substream); ret = 0; switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); au_sync(); au_writel(AC97PCR_START(stype), AC97_PCR(pscdata)); au_sync(); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: au_writel(AC97PCR_STOP(stype), AC97_PCR(pscdata)); au_sync(); while (au_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype)) asm volatile ("nop"); au_writel(AC97PCR_CLRFIFO(stype), AC97_PCR(pscdata)); au_sync(); break; default: ret = -EINVAL; } return ret; }
static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { /* FIXME */ struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; unsigned long r, stat; int chans, stype = SUBSTREAM_TYPE(substream); chans = params_channels(params); r = au_readl(AC97_CFG(pscdata)); stat = au_readl(AC97_STAT(pscdata)); /* already active? */ if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) { /* reject parameters not currently set up */ if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) || (pscdata->rate != params_rate(params))) return -EINVAL; } else { /* disable AC97 device controller first */ au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); au_sync(); /* set sample bitdepth: REG[24:21]=(BITS-2)/2 */ r &= ~PSC_AC97CFG_LEN_MASK; r |= PSC_AC97CFG_SET_LEN(params->msbits); /* channels: enable slots for front L/R channel */ if (stype == PCM_TX) { r &= ~PSC_AC97CFG_TXSLOT_MASK; r |= PSC_AC97CFG_TXSLOT_ENA(3); r |= PSC_AC97CFG_TXSLOT_ENA(4); } else { r &= ~PSC_AC97CFG_RXSLOT_MASK; r |= PSC_AC97CFG_RXSLOT_ENA(3); r |= PSC_AC97CFG_RXSLOT_ENA(4); } /* finally enable the AC97 controller again */ au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); au_sync(); pscdata->cfg = r; pscdata->rate = params_rate(params); } return 0; }
static int au1xpsc_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai) { struct au1xpsc_audio_data *pscdata = au1xpsc_i2s_workdata; int ret, stype = SUBSTREAM_TYPE(substream); switch (cmd) { case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_RESUME: ret = au1xpsc_i2s_start(pscdata, stype); break; case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_SUSPEND: ret = au1xpsc_i2s_stop(pscdata, stype); break; default: ret = -EINVAL; } return ret; }
static int au1xpsc_ac97_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct au1xpsc_audio_data *pscdata = au1xpsc_ac97_workdata; unsigned long r, ro, stat; int chans, stype = SUBSTREAM_TYPE(substream); chans = params_channels(params); r = ro = au_readl(AC97_CFG(pscdata)); stat = au_readl(AC97_STAT(pscdata)); if (stat & (PSC_AC97STAT_TB | PSC_AC97STAT_RB)) { if ((PSC_AC97CFG_GET_LEN(r) != params->msbits) || (pscdata->rate != params_rate(params))) return -EINVAL; } else { r &= ~PSC_AC97CFG_LEN_MASK; r |= PSC_AC97CFG_SET_LEN(params->msbits); if (stype == PCM_TX) { r &= ~PSC_AC97CFG_TXSLOT_MASK; r |= PSC_AC97CFG_TXSLOT_ENA(3); r |= PSC_AC97CFG_TXSLOT_ENA(4); } else { r &= ~PSC_AC97CFG_RXSLOT_MASK; r |= PSC_AC97CFG_RXSLOT_ENA(3); r |= PSC_AC97CFG_RXSLOT_ENA(4); } if (!(r ^ ro)) goto out; mutex_lock(&pscdata->lock); au_writel(r & ~PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); au_sync(); while (au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) asm volatile ("nop"); au_writel(r, AC97_CFG(pscdata)); au_sync(); au_writel(r | PSC_AC97CFG_DE_ENABLE, AC97_CFG(pscdata)); au_sync(); while (!(au_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) asm volatile ("nop"); mutex_unlock(&pscdata->lock); pscdata->cfg = r; pscdata->rate = params_rate(params); } out: return 0; }