int board_early_init_f (void) { volatile immap_t *im = (immap_t *) CFG_IMMR; u32 lpcaw; /* * Initialize Local Window for the CPLD registers access (CS2 selects * the CPLD chip) */ im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) | CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE); im->lpc.cs_cfg[2] = CFG_CS2_CFG; /* * According to MPC5121e RM, configuring local access windows should * be followed by a dummy read of the config register that was * modified last and an isync */ lpcaw = im->sysconf.lpcs2aw; __asm__ __volatile__ ("isync"); /* * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control * * Without this the flash identification routine fails, as it needs to issue * write commands in order to establish the device ID. */ #ifdef CONFIG_ADS5121_REV2 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; #else if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) { *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; } else { /* running from Backup flash */ *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32; } #endif /* * Configure Flash Speed */ *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG; if (SVR_MJREV (im->sysconf.spridr) >= 2) { *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING; } /* * Enable clocks */ im->clk.sccr[0] = SCCR1_CLOCKS_EN; im->clk.sccr[1] = SCCR2_CLOCKS_EN; return 0; }
int checkboard (void) { ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 spridr = in_be32(&im->sysconf.spridr); printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); /* initialize function mux & slew rate IO inter alia on IO Pins */ iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); if (SVR_MJREV (spridr) >= 2) iopin_initialize(rev2_silicon_pci_ioregs_init, 1); return 0; }