void __init adm5120_soc_init(void)
{
u32 code;
u32 clks;
code = SW_READ_REG(SWITCH_REG_CODE);
adm5120_product_code = CODE_GET_PC(code);
adm5120_revision = CODE_GET_REV(code);
adm5120_package = (CODE_GET_PK(code) == CODE_PK_BGA) ?
ADM5120_PACKAGE_BGA : ADM5120_PACKAGE_PQFP;
adm5120_nand_boot = CODE_GET_NAB(code);
clks = CODE_GET_CLKS(code);
adm5120_speed = ADM5120_SPEED_175;
if (clks & 1)
adm5120_speed += 25000000;
if (clks & 2)
adm5120_speed += 50000000;
}
void adm5120_ndelay(u32 ns)
{
u32 t;
SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
t = (ns+640) / 640;
t &= TIMER_PERIOD_MASK;
SW_WRITE_REG(SWITCH_REG_TIMER, t | TIMER_TE);
/* wait until the timer expires */
do {
t = SW_READ_REG(SWITCH_REG_TIMER_INT);
} while ((t & TIMER_INT_TOS) == 0);
/* leave the timer disabled */
SW_WRITE_REG(SWITCH_REG_TIMER, TIMER_PERIOD_DEFAULT);
SW_WRITE_REG(SWITCH_REG_TIMER_INT, (TIMER_INT_TOS | TIMER_INT_TOM));
}
static inline void wdt_reset_counter(void)
{
SW_READ_REG(SWITCH_REG_WDOG0);
}
static int inca_amdix(void)
{
u32 phyReg1 = 0;
u32 phyReg4 = 0;
u32 phyReg5 = 0;
u32 phyReg6 = 0;
u32 phyReg31 = 0;
u32 regEphy = 0;
int mdi_flag;
int retries;
/* Setup GPIO pins.
*/
*INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
*INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
#if 0
/* Wait for signal.
*/
retries = WAIT_SIGNAL_RETRIES;
while (--retries) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(17 << 16)); /* PHY_MCSR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
} while (phyReg1 & (1 << 31));
if (phyReg1 & (1 << 1)) {
/* Signal detected */
break;
}
}
if (!retries)
goto Fail;
#endif
/* Set MDI mode.
*/
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
mdi_flag = 1;
/* Wait for link.
*/
retries = WAIT_LINK_RETRIES;
while (--retries) {
udelay(LINK_RETRY_DELAY * 1000);
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(1 << 16)); /* PHY_BSR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
} while (phyReg1 & (1 << 31));
if (phyReg1 & (1 << 2)) {
/* Link is up */
break;
} else if (mdi_flag) {
/* Set MDIX mode */
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
mdi_flag = 0;
} else {
/* Set MDI mode */
*INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
mdi_flag = 1;
}
}
if (!retries) {
goto Fail;
} else {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(1 << 16)); /* PHY_BSR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
} while (phyReg1 & (1 << 31));
/* Auto-negotiation / Parallel detection complete
*/
if (phyReg1 & (1 << 5)) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(31 << 16)); /* PHY_SCSR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
} while (phyReg31 & (1 << 31));
switch ((phyReg31 >> 2) & 0x7) {
case INCA_SWITCH_PHY_SPEED_10H:
/* 10Base-T Half-duplex */
regEphy = 0;
break;
case INCA_SWITCH_PHY_SPEED_10F:
/* 10Base-T Full-duplex */
regEphy = INCA_IP_Switch_EPHY_DL;
break;
case INCA_SWITCH_PHY_SPEED_100H:
/* 100Base-TX Half-duplex */
regEphy = INCA_IP_Switch_EPHY_SL;
break;
case INCA_SWITCH_PHY_SPEED_100F:
/* 100Base-TX Full-duplex */
regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
break;
}
/* In case of Auto-negotiation,
* update the negotiated PAUSE support status
*/
if (phyReg1 & (1 << 3)) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(6 << 16)); /* PHY_ANER */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
} while (phyReg6 & (1 << 31));
/* We are Autoneg-able.
* Is Link partner also able to autoneg?
*/
if (phyReg6 & (1 << 0)) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(4 << 16)); /* PHY_ANAR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
} while (phyReg4 & (1 << 31));
/* We advertise PAUSE capab.
* Does link partner also advertise it?
*/
if (phyReg4 & (1 << 10)) {
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
(0x1 << 31) | /* RA */
(0x0 << 30) | /* Read */
(0x6 << 21) | /* LAN */
(5 << 16)); /* PHY_ANLPAR */
do {
SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
} while (phyReg5 & (1 << 31));
/* Link partner is PAUSE capab.
*/
if (phyReg5 & (1 << 10)) {
regEphy |= INCA_IP_Switch_EPHY_PL;
}
}
}
}
/* Link is up */
regEphy |= INCA_IP_Switch_EPHY_LL;
SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
}
}
static void inca_init_switch_chip(void)
{
u32 regValue;
/* To workaround a problem with collision counter
* (see Errata sheet).
*/
SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
#if 1
/* init MDIO configuration:
* MDS (Poll speed): 0x01 (4ms)
* PHY_LAN_ADDR: 0x06
* PHY_PC_ADDR: 0x05
* UEP (Use External PHY): 0x00 (Internal PHY is used)
* PS (Port Select): 0x00 (PT/UMM for LAN)
* PT (PHY Test): 0x00 (no test mode)
* UMM (Use MDIO Mode): 0x00 (state machine is disabled)
*/
SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
/* init PHY:
* SL (Auto Neg. Speed for LAN)
* SP (Auto Neg. Speed for PC)
* LL (Link Status for LAN)
* LP (Link Status for PC)
* DL (Duplex Status for LAN)
* DP (Duplex Status for PC)
* PL (Auto Neg. Pause Status for LAN)
* PP (Auto Neg. Pause Status for PC)
*/
SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
/* MDIO_ACC:
* RA (Request/Ack) 0x01 (Request)
* RW (Read/Write) 0x01 (Write)
* PHY_ADDR 0x05 (PC)
* REG_ADDR 0x00 (PHY_BCR: basic control register)
* PHY_DATA 0x8000
* Reset - software reset
* LB (loop back) - normal
* SS (speed select) - 10 Mbit/s
* ANE (auto neg. enable) - enable
* PD (power down) - normal
* ISO (isolate) - normal
* RAN (restart auto neg.) - normal
* DM (duplex mode) - half duplex
* CT (collision test) - enable
*/
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
/* MDIO_ACC:
* RA (Request/Ack) 0x01 (Request)
* RW (Read/Write) 0x01 (Write)
* PHY_ADDR 0x06 (LAN)
* REG_ADDR 0x00 (PHY_BCR: basic control register)
* PHY_DATA 0x8000
* Reset - software reset
* LB (loop back) - normal
* SS (speed select) - 10 Mbit/s
* ANE (auto neg. enable) - enable
* PD (power down) - normal
* ISO (isolate) - normal
* RAN (restart auto neg.) - normal
* DM (duplex mode) - half duplex
* CT (collision test) - enable
*/
SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
#endif
/* Make sure the CPU port is disabled for now. We
* don't want packets to get stacked for us until
* we enable DMA and are prepared to receive them.
*/
SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
/* CRC GEN is enabled.
*/
regValue |= 0x00000200;
SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
/* ADD TAG is disabled.
*/
SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
regValue &= ~0x00000002;
SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
}
