/* Calculate Ultra DMA timings */
static int
pmac_ide_udma_enable(ide_drive_t *drive, int idx)
{
byte bits = drive->id->dma_ultra & 0x1f;
byte feature = udma_bits_to_command(bits);
int cycleTime, accessTime;
int rdyToPauseTicks, cycleTicks;
u32 *timings;
/* Set feature on drive */
printk("%s: Enabling Ultra DMA %d\n", drive->name, feature & 0xf);
if (pmac_ide_do_setfeature(drive, feature)) {
printk("%s: Failed !\n", drive->name);
return 0;
}
/* which drive is it ? */
if (drive->select.all & 0x10)
timings = &pmac_ide[idx].timings[1];
else
timings = &pmac_ide[idx].timings[0];
cycleTime = udma_timings[feature & 0xf].cycleTime;
accessTime = udma_timings[feature & 0xf].accessTime;
rdyToPauseTicks = SYSCLK_TICKS_UDMA(accessTime * 1000);
cycleTicks = SYSCLK_TICKS_UDMA(cycleTime * 1000);
*timings = ((*timings) & 0xe00fffff) |
((cycleTicks << 1) | (rdyToPauseTicks << 5) | 1) << 20;
return 1;
}
static int
set_timings_mdma(int intf, u32 *timings, byte speed)
{
int cycleTime, accessTime;
int accessTicks, recTicks;
/* Calculate accesstime and cycle time */
cycleTime = mdma_timings[speed & 0xf].cycleTime;
accessTime = mdma_timings[speed & 0xf].accessTime;
if ((pmac_ide[intf].kind == controller_ohare) && (cycleTime < 150))
cycleTime = 150;
/* For ata-4 controller */
if (pmac_ide[intf].kind == controller_kl_ata4) {
accessTicks = SYSCLK_TICKS_UDMA(accessTime * 1000);
recTicks = SYSCLK_TICKS_UDMA(cycleTime * 1000) - accessTicks;
*timings = ((*timings) & 0xffe003ff) |
(accessTicks | (recTicks << 5)) << 10;
} else {
int halfTick = 0;
int origAccessTime = accessTime;
int origCycleTime = cycleTime;
accessTicks = SYSCLK_TICKS(accessTime);
if (accessTicks < 1)
accessTicks = 1;
accessTime = accessTicks * IDE_SYSCLK_NS;
recTicks = SYSCLK_TICKS(cycleTime - accessTime) - 1;
if (recTicks < 1)
recTicks = 1;
cycleTime = (recTicks + 1 + accessTicks) * IDE_SYSCLK_NS;
/* KeyLargo ata-3 don't support the half-tick stuff */
if ((pmac_ide[intf].kind != controller_kl_ata3) &&
(accessTicks > 1) &&
((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
((cycleTime - IDE_SYSCLK_NS) >= origCycleTime)) {
halfTick = 1;
accessTicks--;
}
*timings = ((*timings) & 0x7FF) |
(accessTicks | (recTicks << 5) | (halfTick << 10)) << 11;
}
return 0;
}
/* Calculate PIO timings */
static void
pmac_ide_tuneproc(ide_drive_t *drive, byte pio)
{
ide_pio_data_t d;
int i;
u32 *timings;
int accessTicks, recTicks;
i = pmac_ide_find(drive);
if (i < 0)
return;
pio = ide_get_best_pio_mode(drive, pio, 4, &d);
accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
if (drive->select.all & 0x10)
timings = &pmac_ide[i].timings[1];
else
timings = &pmac_ide[i].timings[0];
if (pmac_ide[i].kind == controller_kl_ata4) {
/* The "ata-4" IDE controller of Core99 machines */
accessTicks = SYSCLK_TICKS_UDMA(ide_pio_timings[pio].active_time * 1000);
recTicks = SYSCLK_TICKS_UDMA(d.cycle_time * 1000) - accessTicks;
*timings = ((*timings) & 0x1FFFFFC00) | accessTicks | (recTicks << 5);
} else {
/* The old "ata-3" IDE controller */
accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
if (accessTicks < 4)
accessTicks = 4;
recTicks = SYSCLK_TICKS(d.cycle_time) - accessTicks - 4;
if (recTicks < 1)
recTicks = 1;
*timings = ((*timings) & 0xFFFFFF800) | accessTicks | (recTicks << 5);
}
#ifdef IDE_PMAC_DEBUG
printk(KERN_ERR "ide_pmac: Set PIO timing for mode %d, reg: 0x%08x\n",
pio, *timings);
#endif
if (drive->select.all == IN_BYTE(IDE_SELECT_REG))
pmac_ide_selectproc(drive);
}
static int
set_timings_udma(int intf, u32 *timings, byte speed)
{
int cycleTime, accessTime;
int rdyToPauseTicks, cycleTicks;
if (pmac_ide[intf].kind != controller_kl_ata4)
return 1;
cycleTime = udma_timings[speed & 0xf].cycleTime;
accessTime = udma_timings[speed & 0xf].accessTime;
rdyToPauseTicks = SYSCLK_TICKS_UDMA(accessTime * 1000);
cycleTicks = SYSCLK_TICKS_UDMA(cycleTime * 1000);
*timings = ((*timings) & 0xe00fffff) |
((cycleTicks << 1) | (rdyToPauseTicks << 5) | 1) << 20;
return 0;
}
/* Calculate MultiWord DMA timings */
static int
pmac_ide_mdma_enable(ide_drive_t *drive, int idx)
{
byte bits = drive->id->dma_mword & 0x07;
byte feature = dma_bits_to_command(bits);
u32 *timings;
int cycleTime, accessTime;
int accessTicks, recTicks;
struct hd_driveid *id = drive->id;
int ret;
/* Set feature on drive */
printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, feature & 0xf);
ret = pmac_ide_do_setfeature(drive, feature);
if (ret) {
printk(KERN_WARNING "%s: Failed !\n", drive->name);
return 0;
}
if (!drive->init_speed)
drive->init_speed = feature;
/* which drive is it ? */
if (drive->select.all & 0x10)
timings = &pmac_ide[idx].timings[1];
else
timings = &pmac_ide[idx].timings[0];
/* Calculate accesstime and cycle time */
cycleTime = mdma_timings[feature & 0xf].cycleTime;
accessTime = mdma_timings[feature & 0xf].accessTime;
if ((id->field_valid & 2) && (id->eide_dma_time))
cycleTime = id->eide_dma_time;
if ((pmac_ide[idx].kind == controller_ohare) && (cycleTime < 150))
cycleTime = 150;
/* For ata-4 controller */
if (pmac_ide[idx].kind == controller_kl_ata4) {
accessTicks = SYSCLK_TICKS_UDMA(accessTime * 1000);
recTicks = SYSCLK_TICKS_UDMA(cycleTime * 1000) - accessTicks;
*timings = ((*timings) & 0xffe003ff) |
(accessTicks | (recTicks << 5)) << 10;
} else {
int halfTick = 0;
int origAccessTime = accessTime;
int origCycleTime = cycleTime;
accessTicks = SYSCLK_TICKS(accessTime);
if (accessTicks < 1)
accessTicks = 1;
accessTime = accessTicks * IDE_SYSCLK_NS;
recTicks = SYSCLK_TICKS(cycleTime - accessTime) - 1;
if (recTicks < 1)
recTicks = 1;
cycleTime = (recTicks + 1 + accessTicks) * IDE_SYSCLK_NS;
/* KeyLargo ata-3 don't support the half-tick stuff */
if ((pmac_ide[idx].kind != controller_kl_ata3) &&
(accessTicks > 1) &&
((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
((cycleTime - IDE_SYSCLK_NS) >= origCycleTime)) {
halfTick = 1;
accessTicks--;
}
*timings = ((*timings) & 0x7FF) |
(accessTicks | (recTicks << 5) | (halfTick << 10)) << 11;
}
#ifdef IDE_PMAC_DEBUG
printk(KERN_INFO "ide_pmac: Set MDMA timing for mode %d, reg: 0x%08x\n",
feature & 0xf, *timings);
#endif
drive->current_speed = feature;
return 1;
}
