static void si4700_sleep(int snooze)
{
if (snooze)
{
/** power down **/
/* ENABLE high, DISABLE high */
si4700_write_set(POWERCFG,
POWERCFG_DISABLE | POWERCFG_ENABLE);
/* Bits self-clear once placed in powerdown. */
cache[POWERCFG] &= ~(POWERCFG_DISABLE | POWERCFG_ENABLE);
}
else
{
/** power up **/
/* ENABLE high, DISABLE low */
si4700_write_masked(POWERCFG, POWERCFG_ENABLE,
POWERCFG_DISABLE | POWERCFG_ENABLE);
sleep(110 * HZ / 1000);
/* init register cache */
si4700_read(16);
#if SI4700_GPIO_SETUP != 0
si4700_write_masked(SYSCONFIG1, SI4700_GPIO_SETUP,
SYSCONFIG1_GPIO1 | SYSCONFIG1_GPIO2 |
SYSCONFIG1_GPIO3);
#endif
si4700_write_masked(SYSCONFIG2,
SYSCONFIG2_SKEETHw(SEEK_THRESHOLD) |
SYSCONFIG2_VOLUMEw(0xF),
SYSCONFIG2_VOLUME | SYSCONFIG2_SEEKTH);
}
}
static void si4700_sleep(int snooze)
{
if (snooze)
{
/** power down **/
#ifdef HAVE_RDS_CAP
if (cache[CHIPID] & CHIPID_DEV_0) {
si4700_rds_powerup(false);
si4700_write_clear(SYSCONFIG1, SYSCONFIG1_RDS | SYSCONFIG1_RDSIEN);
}
#endif
/* ENABLE high, DISABLE high */
si4700_write_set(POWERCFG,
POWERCFG_DISABLE | POWERCFG_ENABLE);
/* Bits self-clear once placed in powerdown. */
cache[POWERCFG] &= ~(POWERCFG_DISABLE | POWERCFG_ENABLE);
tuner_power(false);
}
else
{
tuner_power(true);
/* read all registers */
si4700_read(16);
#ifdef SI4700_USE_INTERNAL_OSCILLATOR
/* Enable the internal oscillator
(Si4702-16 needs this register to be initialised to 0x100) */
si4700_write_set(TEST1, TEST1_XOSCEN | 0x100);
sleep(HZ/2);
#endif
/** power up **/
/* ENABLE high, DISABLE low */
si4700_write_masked(POWERCFG, POWERCFG_ENABLE,
POWERCFG_DISABLE | POWERCFG_ENABLE);
sleep(110 * HZ / 1000);
/* init register cache */
si4700_read(16);
#ifdef SI4700_USE_MO_ST_I
si4700_write_masked(SYSCONFIG1, SYSCONFIG1_GPIO3_MO_ST_I,
SYSCONFIG1_GPIO3);
#endif
/* set mono->stereo switching RSSI range to lowest setting */
si4700_write_masked(SYSCONFIG1, SYSCONFIG1_BLNDADJ_19_37_RSSI,
SYSCONFIG1_BLNDADJ);
si4700_write_masked(SYSCONFIG2,
SYSCONFIG2_SKEETHw(SEEK_THRESHOLD) |
SYSCONFIG2_VOLUMEw(0xF),
SYSCONFIG2_VOLUME | SYSCONFIG2_SEEKTH);
#ifdef HAVE_RDS_CAP
/* enable RDS and RDS interrupt if supported (bit 9 of CHIPID) */
if (cache[CHIPID] & CHIPID_DEV_0) {
/* Is Si4701/2/3 - Enable RDS and interrupt */
si4700_write_set(SYSCONFIG1, SYSCONFIG1_RDS | SYSCONFIG1_RDSIEN);
si4700_write_masked(SYSCONFIG1, SYSCONFIG1_GPIO2_STC_RDS_I,
SYSCONFIG1_GPIO2);
si4700_rds_powerup(true);
}
#endif
}
}
