void SetPROM_32K_Bank( INT bank )
{
SetPROM_8K_Bank( 4, bank*4+0 );
SetPROM_8K_Bank( 5, bank*4+1 );
SetPROM_8K_Bank( 6, bank*4+2 );
SetPROM_8K_Bank( 7, bank*4+3 );
}
void Mapper075::Write( WORD addr, BYTE data )
{
switch( addr & 0xF000 ) {
case 0x8000:
SetPROM_8K_Bank( 4, data );
break;
case 0x9000:
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
reg[0] = (reg[0] & 0x0F) | ((data & 0x02) << 3);
reg[1] = (reg[1] & 0x0F) | ((data & 0x04) << 2);
SetVROM_4K_Bank( 0, reg[0] );
SetVROM_4K_Bank( 4, reg[1] );
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
case 0xC000:
SetPROM_8K_Bank( 6, data );
break;
case 0xE000:
reg[0] = (reg[0] & 0x10) | (data & 0x0F);
SetVROM_4K_Bank( 0, reg[0] );
break;
case 0xF000:
reg[1] = (reg[1] & 0x10) | (data & 0x0F);
SetVROM_4K_Bank( 4, reg[1] );
break;
}
}
void Mapper076::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
reg = data;
break;
case 0x8001:
switch( reg & 0x07 ) {
case 2:
SetVROM_2K_Bank( 0, data );
break;
case 3:
SetVROM_2K_Bank( 2, data );
break;
case 4:
SetVROM_2K_Bank( 4, data );
break;
case 5:
SetVROM_2K_Bank( 6, data );
break;
case 6:
SetPROM_8K_Bank( 4, data );
break;
case 7:
SetPROM_8K_Bank( 5, data );
break;
}
break;
}
}
void SetPROM_32K_Bank( INT bank0, INT bank1, INT bank2, INT bank3 )
{
SetPROM_8K_Bank( 4, bank0 );
SetPROM_8K_Bank( 5, bank1 );
SetPROM_8K_Bank( 6, bank2 );
SetPROM_8K_Bank( 7, bank3 );
}
void Mapper091::WriteLow( WORD addr, BYTE data )
{
//DEBUGOUT( "$%04X:$%02X(%3d) L=%3d\n", addr, data, data, nes->GetScanline() );
switch( addr & 0xF003 ) {
case 0x6000:
case 0x6001:
case 0x6002:
case 0x6003:
SetVROM_2K_Bank( (addr&0x03)*2, data );
break;
case 0x7000:
SetPROM_8K_Bank( 4, data );
break;
case 0x7001:
SetPROM_8K_Bank( 5, data );
break;
case 0x7002:
irq_enable = 0;
irq_counter = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x7003:
irq_enable = 1;
break;
}
}
void MapperUNL_KS7037::Sync()
{
SetPROM_8K_Bank(4,reg[6]);//8000~9FFF
SetPROM_8K_Bank(6,reg[7]);//C000~DFFF
SetPROM_8K_Bank(7,PROM_8K_SIZE-1);//E000~FFFF
SetVROM_8K_Bank( 0 );
SetVRAM_Mirror(reg[2]&1,reg[4]&1,reg[3]&1,reg[5]&1);
}
void Mapper114::SetBank_CPU()
{
if( reg_m & 0x80 ) {
SetPROM_16K_Bank( 4, reg_m & 0x1F );
} else {
SetPROM_8K_Bank( 4, reg_b[4] );
SetPROM_8K_Bank( 5, reg_b[5] );
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper050 SMB2J //
//////////////////////////////////////////////////////////////////////////
void Mapper050::Reset()
{
irq_enable = 0;
SetPROM_8K_Bank( 3, 15 );
SetPROM_8K_Bank( 4, 8 );
SetPROM_8K_Bank( 5, 9 );
SetPROM_8K_Bank( 6, 0 );
SetPROM_8K_Bank( 7, 11 );
if( VROM_1K_SIZE ) {
SetVROM_8K_Bank( 0 );
}
}
void Mapper022::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
SetPROM_8K_Bank( 4, data );
break;
case 0x9000:
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4H );
else SetVRAM_Mirror( VRAM_MIRROR4L );
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
case 0xB000:
SetVROM_1K_Bank( 0, data>>1 );
break;
case 0xB001:
SetVROM_1K_Bank( 1, data>>1 );
break;
case 0xC000:
SetVROM_1K_Bank( 2, data>>1 );
break;
case 0xC001:
SetVROM_1K_Bank( 3, data>>1 );
break;
case 0xD000:
SetVROM_1K_Bank( 4, data>>1 );
break;
case 0xD001:
SetVROM_1K_Bank( 5, data>>1 );
break;
case 0xE000:
SetVROM_1K_Bank( 6, data>>1 );
break;
case 0xE001:
SetVROM_1K_Bank( 7, data>>1 );
break;
}
}
void Mapper046::SetBank()
{
SetPROM_8K_Bank( 4, reg[0]*8+reg[2]*4+0 );
SetPROM_8K_Bank( 5, reg[0]*8+reg[2]*4+1 );
SetPROM_8K_Bank( 6, reg[0]*8+reg[2]*4+2 );
SetPROM_8K_Bank( 7, reg[0]*8+reg[2]*4+3 );
SetVROM_1K_Bank( 0, reg[1]*64+reg[3]*8+0 );
SetVROM_1K_Bank( 1, reg[1]*64+reg[3]*8+1 );
SetVROM_1K_Bank( 2, reg[1]*64+reg[3]*8+2 );
SetVROM_1K_Bank( 3, reg[1]*64+reg[3]*8+3 );
SetVROM_1K_Bank( 4, reg[1]*64+reg[3]*8+4 );
SetVROM_1K_Bank( 5, reg[1]*64+reg[3]*8+5 );
SetVROM_1K_Bank( 6, reg[1]*64+reg[3]*8+6 );
SetVROM_1K_Bank( 7, reg[1]*64+reg[3]*8+7 );
}
void Mapper175::Read( WORD addr, BYTE data)
{
if( addr == 0xFFFC ) {
SetPROM_16K_Bank( 4, reg_dat & 0x0F );
SetPROM_8K_Bank( 6, (reg_dat & 0x0F)*2 );
}
}
void Mapper117::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
SetPROM_8K_Bank( 4, data );
break;
case 0x8001:
SetPROM_8K_Bank( 5, data );
break;
case 0x8002:
SetPROM_8K_Bank( 6, data );
break;
case 0xA000:
SetVROM_1K_Bank( 0, data );
break;
case 0xA001:
SetVROM_1K_Bank( 1, data );
break;
case 0xA002:
SetVROM_1K_Bank( 2, data );
break;
case 0xA003:
SetVROM_1K_Bank( 3, data );
break;
case 0xA004:
SetVROM_1K_Bank( 4, data );
break;
case 0xA005:
SetVROM_1K_Bank( 5, data );
break;
case 0xA006:
SetVROM_1K_Bank( 6, data );
break;
case 0xA007:
SetVROM_1K_Bank( 7, data );
break;
case 0xC001:
case 0xC002:
case 0xC003:
irq_counter = data;
break;
case 0xE000:
irq_enable = data & 1;
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
}
}
void Mapper032::Write( WORD addr, BYTE data )
{
switch( addr & 0xF000 ) {
case 0x8000:
if( reg & 0x02 ) {
SetPROM_8K_Bank( 6, data );
} else {
SetPROM_8K_Bank( 4, data );
}
break;
case 0x9000:
reg = data;
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
}
switch( addr & 0xF007 ) {
case 0xB000:
case 0xB001:
case 0xB002:
case 0xB003:
case 0xB004:
case 0xB005:
SetVROM_1K_Bank( addr & 0x0007, data );
break;
case 0xB006:
SetVROM_1K_Bank( 6, data );
if( patch && (data & 0x40) ) {
SetVRAM_Mirror( 0, 0, 0, 1 );
}
break;
case 0xB007:
SetVROM_1K_Bank( 7, data );
if( patch && (data & 0x40) ) {
SetVRAM_Mirror( 0, 0, 0, 0 );
}
break;
}
}
void Mapper045::SetBank_CPU_7( INT data )
{
data &= (reg[3] & 0x3F) ^ 0xFF;
data &= 0x3F;
data |= reg[1];
SetPROM_8K_Bank( 7, data );
p[3] = data;
}
// Famicom Jump 2
void Mapper016::WriteSubB( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
case 0x8001:
case 0x8002:
case 0x8003:
reg[0] = data & 0x01;
SetPROM_8K_Bank( 4, reg[0]*0x20+reg[2]*2+0 );
SetPROM_8K_Bank( 5, reg[0]*0x20+reg[2]*2+1 );
break;
case 0x8004:
case 0x8005:
case 0x8006:
case 0x8007:
reg[1] = data & 0x01;
SetPROM_8K_Bank( 6, reg[1]*0x20+0x1E );
SetPROM_8K_Bank( 7, reg[1]*0x20+0x1F );
break;
case 0x8008:
reg[2] = data;
SetPROM_8K_Bank( 4, reg[0]*0x20+reg[2]*2+0 );
SetPROM_8K_Bank( 5, reg[0]*0x20+reg[2]*2+1 );
SetPROM_8K_Bank( 6, reg[1]*0x20+0x1E );
SetPROM_8K_Bank( 7, reg[1]*0x20+0x1F );
break;
case 0x8009:
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x800A:
irq_enable = data & 0x01;
irq_counter = irq_latch;
// if( !irq_enable ) {
// nes->cpu->ClrIRQ( IRQ_MAPPER );
// }
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x800B:
irq_latch = (irq_latch & 0xFF00) | data;
break;
case 0x800C:
irq_latch = ((INT)data << 8) | (irq_latch & 0x00FF);
break;
case 0x800D:
break;
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper040 SMB2J //
//////////////////////////////////////////////////////////////////////////
void Mapper040::Reset()
{
irq_enable = 0;
irq_line = 0;
SetPROM_8K_Bank( 3, 6 );
SetPROM_32K_Bank( 4, 5, 0, 7 );
if( VROM_1K_SIZE ) {
SetVROM_8K_Bank( 0 );
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper042 Mario Baby //
//////////////////////////////////////////////////////////////////////////
void Mapper042::Reset()
{
irq_enable = 0;
irq_counter = 0;
SetPROM_8K_Bank( 3, 0 );
SetPROM_32K_Bank( PROM_8K_SIZE-4, PROM_8K_SIZE-3, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
if( VROM_1K_SIZE ) {
SetVROM_8K_Bank( 0 );
}
}
void Mapper175::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
if( data & 0x04 ) {
SetVRAM_Mirror( VRAM_HMIRROR );
} else {
SetVRAM_Mirror( VRAM_VMIRROR );
}
break;
case 0xA000:
reg_dat = data;
SetPROM_8K_Bank( 7, (reg_dat & 0x0F)*2+1 );
SetVROM_8K_Bank( reg_dat & 0x0F );
break;
}
}
void Mapper040::Write( WORD addr, BYTE data )
{
switch( addr & 0xE000 ) {
case 0x8000:
irq_enable = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xA000:
irq_enable = 0xFF;
irq_line = 37;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xC000:
break;
case 0xE000:
SetPROM_8K_Bank( 6, data&0x07 );
break;
}
}
void Mapper090::SetBank_CPU()
{
if( prg_size == 0 ) {
SetPROM_32K_Bank( PROM_8K_SIZE-4, PROM_8K_SIZE-3, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
} else
if( prg_size == 1 ) {
SetPROM_32K_Bank( prg_reg[1]*2, prg_reg[1]*2+1, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
} else
if( prg_size == 2 ) {
if( prg_E000 ) {
SetPROM_32K_Bank( prg_reg[0], prg_reg[1], prg_reg[2], prg_reg[3] );
} else {
if( prg_6000 ) {
SetPROM_8K_Bank( 3, prg_reg[3] );
}
SetPROM_32K_Bank( prg_reg[0], prg_reg[1], prg_reg[2], PROM_8K_SIZE-1 );
}
} else {
SetPROM_32K_Bank( prg_reg[3], prg_reg[2], prg_reg[1], prg_reg[0] );
}
}
void Mapper042::Write( WORD addr, BYTE data )
{
switch( addr & 0xE003 ) {
case 0xE000:
SetPROM_8K_Bank( 3, data&0x0F );
break;
case 0xE001:
if( data&0x08 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
case 0xE002:
if( data&0x02 ) {
irq_enable = 0xFF;
} else {
irq_enable = 0;
irq_counter = 0;
}
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
}
}
void Mapper009::Write( WORD addr, BYTE data )
{
switch( addr & 0xF000 ) {
case 0xA000:
SetPROM_8K_Bank( 4, data );
break;
case 0xB000:
reg[0] = data;
if( latch_a == 0xFD ) {
SetVROM_4K_Bank( 0, reg[0] );
}
break;
case 0xC000:
reg[1] = data;
if( latch_a == 0xFE ) {
SetVROM_4K_Bank( 0, reg[1] );
}
break;
case 0xD000:
reg[2] = data;
if( latch_b == 0xFD ) {
SetVROM_4K_Bank( 4, reg[2] );
}
break;
case 0xE000:
reg[3] = data;
if( latch_b == 0xFE ) {
SetVROM_4K_Bank( 4, reg[3] );
}
break;
case 0xF000:
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
}
}
void Mapper025::Write( WORD addr, BYTE data )
{
//if( addr >= 0xF000 )
//DEBUGOUT( "M25 WR $%04X=$%02X L=%3d\n", addr, data, nes->GetScanline() );
switch( addr & 0xF000 ) {
case 0x8000:
if(reg[10] & 0x02) {
reg[9] = data;
SetPROM_8K_Bank( 6, data );
} else {
reg[8] = data;
SetPROM_8K_Bank( 4, data );
}
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
}
switch( addr & 0xF00F ) {
case 0x9000:
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x9001:
case 0x9004:
if((reg[10] & 0x02) != (data & 0x02)) {
BYTE swap = reg[8];
reg[8] = reg[9];
reg[9] = swap;
SetPROM_8K_Bank( 4, reg[8] );
SetPROM_8K_Bank( 6, reg[9] );
}
reg[10] = data;
break;
case 0xB000:
reg[0] = (reg[0] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 0, reg[0] );
break;
case 0xB002:
case 0xB008:
reg[0] = (reg[0] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 0, reg[0] );
break;
case 0xB001:
case 0xB004:
reg[1] = (reg[1] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 1, reg[1] );
break;
case 0xB003:
case 0xB00C:
reg[1] = (reg[1] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 1, reg[1] );
break;
case 0xC000:
reg[2] = (reg[2] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 2, reg[2] );
break;
case 0xC002:
case 0xC008:
reg[2] = (reg[2] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 2, reg[2] );
break;
case 0xC001:
case 0xC004:
reg[3] = (reg[3] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 3, reg[3] );
break;
case 0xC003:
case 0xC00C:
reg[3] = (reg[3] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 3, reg[3] );
break;
case 0xD000:
reg[4] = (reg[4] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 4, reg[4] );
break;
case 0xD002:
case 0xD008:
reg[4] = (reg[4] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 4, reg[4] );
break;
case 0xD001:
case 0xD004:
reg[5] = (reg[5] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 5, reg[5] );
break;
case 0xD003:
case 0xD00C:
reg[5] = (reg[5] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 5, reg[5] );
break;
case 0xE000:
reg[6] = (reg[6] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 6, reg[6] );
break;
case 0xE002:
case 0xE008:
reg[6] = (reg[6] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 6, reg[6] );
break;
case 0xE001:
case 0xE004:
reg[7] = (reg[7] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 7, reg[7] );
break;
case 0xE003:
case 0xE00C:
reg[7] = (reg[7] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 7, reg[7] );
break;
case 0xF000:
irq_latch = (irq_latch & 0xF0) | (data & 0x0F);
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF002:
case 0xF008:
irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4);
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF001:
case 0xF004:
irq_enable = data & 0x03;
// irq_counter = 0x100 - irq_latch;
irq_counter = irq_latch;
irq_clock = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF003:
case 0xF00C:
irq_enable = (irq_enable & 0x01)*3;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
}
}
void Mapper027::Write( WORD addr, BYTE data )
{
switch( addr & 0xF0CF ) {
case 0x8000:
if(reg[8] & 0x02) {
SetPROM_8K_Bank( 6, data );
} else {
SetPROM_8K_Bank( 4, data );
}
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
case 0x9000:
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x9002:
case 0x9080:
reg[8] = data;
break;
case 0xB000:
reg[0] = (reg[0] & 0xFF0) | (data & 0x0F);
SetVROM_1K_Bank( 0, reg[0] );
break;
case 0xB001:
reg[0] = (reg[0] & 0x0F) | (data<< 4);
SetVROM_1K_Bank( 0, reg[0] );
break;
case 0xB002:
reg[1] = (reg[1] & 0xFF0) | (data & 0x0F);
SetVROM_1K_Bank( 1, reg[1] );
break;
case 0xB003:
reg[1] = (reg[1] & 0x0F) | (data<< 4);
SetVROM_1K_Bank( 1, reg[1] );
break;
case 0xC000:
reg[2] = (reg[2] & 0xFF0) | (data & 0x0F);
SetVROM_1K_Bank( 2, reg[2] );
break;
case 0xC001:
reg[2] = (reg[2] & 0x0F) | (data<< 4);
SetVROM_1K_Bank( 2, reg[2] );
break;
case 0xC002:
reg[3] = (reg[3] & 0xFF0) | (data & 0x0F);
SetVROM_1K_Bank( 3, reg[3] );
break;
case 0xC003:
reg[3] = (reg[3] & 0x0F) | (data<< 4);
SetVROM_1K_Bank( 3, reg[3] );
break;
case 0xD000:
reg[4] = (reg[4] & 0xFF0) | (data & 0x0F);
SetVROM_1K_Bank( 4, reg[4] );
break;
case 0xD001:
reg[4] = (reg[4] & 0x0F) | (data<< 4);
SetVROM_1K_Bank( 4, reg[4] );
break;
case 0xD002:
reg[5] = (reg[5] & 0xFF0) | (data & 0x0F);
SetVROM_1K_Bank( 5, reg[5] );
break;
case 0xD003:
reg[5] = (reg[5] & 0x0F) | (data << 4);
SetVROM_1K_Bank( 5, reg[5] );
break;
case 0xE000:
reg[6] = (reg[6] & 0xFF0) | (data & 0x0F);
SetVROM_1K_Bank( 6, reg[6] );
break;
case 0xE001:
reg[6] = (reg[6] & 0x0F) | (data << 4);
SetVROM_1K_Bank( 6, reg[6] );
break;
case 0xE002:
reg[7] = (reg[7] & 0xFF0) | (data & 0x0F);
SetVROM_1K_Bank( 7, reg[7] );
break;
case 0xE003:
reg[7] = (reg[7] & 0x0F) | (data<< 4);
SetVROM_1K_Bank( 7, reg[7] );
break;
case 0xF000:
irq_latch = (irq_latch & 0xF0) | (data & 0x0F);
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF001:
irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4);
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF003:
irq_enable = (irq_enable & 0x01) * 3;
irq_clock = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF002:
irq_enable = data & 0x03;
if( irq_enable & 0x02 ) {
irq_counter = irq_latch;
irq_clock = 0;
}
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
}
}
void Mapper083::Write( WORD addr, BYTE data )
{
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
switch( addr ) {
case 0x8000:
case 0xB000:
case 0xB0FF:
case 0xB1FF:
reg[0] = data;
chr_bank = (data&0x30)<<4;
SetPROM_16K_Bank( 4, data );
SetPROM_16K_Bank( 6, (data&0x30)|0x0F );
break;
case 0x8100:
reg[1] = data & 0x80;
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x8200:
irq_counter = (irq_counter&0xFF00)|(INT)data;
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x8201:
irq_counter = (irq_counter&0x00FF)|((INT)data<<8);
irq_enable = reg[1];
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x8300:
SetPROM_8K_Bank( 4, data );
break;
case 0x8301:
SetPROM_8K_Bank( 5, data );
break;
case 0x8302:
SetPROM_8K_Bank( 6, data );
break;
case 0x8310:
if( patch ) {
SetVROM_2K_Bank( 0, chr_bank|data );
} else {
SetVROM_1K_Bank( 0, chr_bank|data );
}
break;
case 0x8311:
if( patch ) {
SetVROM_2K_Bank( 2, chr_bank|data );
} else {
SetVROM_1K_Bank( 1, chr_bank|data );
}
break;
case 0x8312:
SetVROM_1K_Bank( 2, chr_bank|data );
break;
case 0x8313:
SetVROM_1K_Bank( 3, chr_bank|data );
break;
case 0x8314:
SetVROM_1K_Bank( 4, chr_bank|data );
break;
case 0x8315:
SetVROM_1K_Bank( 5, chr_bank|data );
break;
case 0x8316:
if( patch ) {
SetVROM_2K_Bank( 4, chr_bank|data );
} else {
SetVROM_1K_Bank( 6, chr_bank|data );
}
break;
case 0x8317:
if( patch ) {
SetVROM_2K_Bank( 6, chr_bank|data );
} else {
SetVROM_1K_Bank( 7, chr_bank|data );
}
break;
case 0x8318:
SetPROM_16K_Bank( 4, (reg[0]&0x30)|data );
break;
}
}
void Mapper033::Write( WORD addr, BYTE data )
{
// LOG( "Mapper033 addr=%04X data=%02X", addr&0xFFFF, data&0xFF );
switch( addr ) {
case 0x8000:
if( patch ) {
if( data & 0x40 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
SetPROM_8K_Bank( 4, data & 0x1F );
} else {
SetPROM_8K_Bank( 4, data );
}
break;
case 0x8001:
if( patch ) {
SetPROM_8K_Bank( 5, data & 0x1F );
} else {
SetPROM_8K_Bank( 5, data );
}
break;
case 0x8002:
reg[0] = data;
SetBank();
break;
case 0x8003:
reg[1] = data;
SetBank();
break;
case 0xA000:
reg[2] = data;
SetBank();
break;
case 0xA001:
reg[3] = data;
SetBank();
break;
case 0xA002:
reg[4] = data;
SetBank();
break;
case 0xA003:
reg[5] = data;
SetBank();
break;
#if 0
case 0xC003:
case 0xE003:
reg[6] = data;
SetBank();
break;
case 0xC000:
irq_counter = data;
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xC001:
case 0xC002:
case 0xE001:
case 0xE002:
irq_enable = data;
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
#else
case 0xC000:
irq_latch = data;
irq_counter = irq_latch;
break;
case 0xC001:
irq_counter = irq_latch;
break;
case 0xC002:
irq_enable = 1;
break;
case 0xC003:
irq_enable = 0;
break;
case 0xE001:
case 0xE002:
case 0xE003:
break;
#endif
case 0xE000:
if( data & 0x40 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
}
}
void Mapper194::Write( WORD addr, BYTE data )
{
SetPROM_8K_Bank( 3, data );
}
void MapperUNL_LH09::Write( WORD A, BYTE data )
{
if(A==0x8001)
SetPROM_8K_Bank( 3, (data/2)&0xF );
}
void MapperUNL_LH09::Reset()
{
SetPROM_8K_Bank( 3, 0 );
SetPROM_32K_Bank( PROM_8K_SIZE-4, PROM_8K_SIZE-3, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
}
void Mapper252::Write( WORD addr, BYTE data )
{
if( (addr & 0xF000) == 0x8000 ) {
SetPROM_8K_Bank( 4, data );
return;
}
if( (addr & 0xF000) == 0xA000 ) {
SetPROM_8K_Bank( 5, data );
return;
}
switch( addr & 0xF00C ) {
case 0xB000:
reg[0] = (reg[0] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 0, reg[0] );
break;
case 0xB004:
reg[0] = (reg[0] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 0, reg[0] );
break;
case 0xB008:
reg[1] = (reg[1] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 1, reg[1] );
break;
case 0xB00C:
reg[1] = (reg[1] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 1, reg[1] );
break;
case 0xC000:
reg[2] = (reg[2] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 2, reg[2] );
break;
case 0xC004:
reg[2] = (reg[2] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 2, reg[2] );
break;
case 0xC008:
reg[3] = (reg[3] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 3, reg[3] );
break;
case 0xC00C:
reg[3] = (reg[3] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 3, reg[3] );
break;
case 0xD000:
reg[4] = (reg[4] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 4, reg[4] );
break;
case 0xD004:
reg[4] = (reg[4] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 4, reg[4] );
break;
case 0xD008:
reg[5] = (reg[5] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 5, reg[5] );
break;
case 0xD00C:
reg[5] = (reg[5] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 5, reg[5] );
break;
case 0xE000:
reg[6] = (reg[6] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 6, reg[6] );
break;
case 0xE004:
reg[6] = (reg[6] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 6, reg[6] );
break;
case 0xE008:
reg[7] = (reg[7] & 0xF0) | (data & 0x0F);
SetVROM_1K_Bank( 7, reg[7] );
break;
case 0xE00C:
reg[7] = (reg[7] & 0x0F) | ((data & 0x0F) << 4);
SetVROM_1K_Bank( 7, reg[7] );
break;
case 0xF000:
irq_latch = (irq_latch & 0xF0) | (data & 0x0F);
irq_occur = 0;
break;
case 0xF004:
irq_latch = (irq_latch & 0x0F) | ((data & 0x0F) << 4);
irq_occur = 0;
break;
case 0xF008:
irq_enable = data & 0x03;
if( irq_enable & 0x02 ) {
irq_counter = irq_latch;
irq_clock = 0;
}
irq_occur = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0xF00C:
irq_enable = (irq_enable & 0x01) * 3;
irq_occur = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
}
}
