void Mapper076::Write( WORD addr, BYTE data )
{
switch( addr ) {
case 0x8000:
reg = data;
break;
case 0x8001:
switch( reg & 0x07 ) {
case 2:
SetVROM_2K_Bank( 0, data );
break;
case 3:
SetVROM_2K_Bank( 2, data );
break;
case 4:
SetVROM_2K_Bank( 4, data );
break;
case 5:
SetVROM_2K_Bank( 6, data );
break;
case 6:
SetPROM_8K_Bank( 4, data );
break;
case 7:
SetPROM_8K_Bank( 5, data );
break;
}
break;
}
}
void Mapper135::SetBank_PPU()
{
SetVROM_2K_Bank( 0, 0|(chr0l<<1)|(chrch<<4) );
SetVROM_2K_Bank( 2, 1|(chr0h<<1)|(chrch<<4) );
SetVROM_2K_Bank( 4, 0|(chr1l<<1)|(chrch<<4) );
SetVROM_2K_Bank( 6, 1|(chr1h<<1)|(chrch<<4) );
}
void Mapper033::SetBank()
{
SetVROM_2K_Bank( 0, reg[0] );
SetVROM_2K_Bank( 2, reg[1] );
// if( reg[6] & 0x01 ) {
SetVROM_1K_Bank( 4, reg[2] );
SetVROM_1K_Bank( 5, reg[3] );
SetVROM_1K_Bank( 6, reg[4] );
SetVROM_1K_Bank( 7, reg[5] );
// } else {
// SetVROM_2K_Bank( 4, reg[0] );
// SetVROM_2K_Bank( 6, reg[1] );
// }
}
void Mapper091::WriteLow( WORD addr, BYTE data )
{
//DEBUGOUT( "$%04X:$%02X(%3d) L=%3d\n", addr, data, data, nes->GetScanline() );
switch( addr & 0xF003 ) {
case 0x6000:
case 0x6001:
case 0x6002:
case 0x6003:
SetVROM_2K_Bank( (addr&0x03)*2, data );
break;
case 0x7000:
SetPROM_8K_Bank( 4, data );
break;
case 0x7001:
SetPROM_8K_Bank( 5, data );
break;
case 0x7002:
irq_enable = 0;
irq_counter = 0;
nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x7003:
irq_enable = 1;
break;
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper077 Irem Early Mapper #0 //
//////////////////////////////////////////////////////////////////////////
void Mapper077::Reset()
{
SetPROM_32K_Bank( 0 );
SetVROM_2K_Bank( 0, 0 );
SetCRAM_2K_Bank( 2, 1 );
SetCRAM_2K_Bank( 4, 2 );
SetCRAM_2K_Bank( 6, 3 );
}
void Mapper090::SetBank_PPU()
{
INT bank[8];
for( INT i = 0; i < 8; i++ ) {
bank[i] = ((INT)chh_reg[i]<<8)|((INT)chl_reg[i]);
}
if( chr_size == 0 ) {
SetVROM_8K_Bank( bank[0] );
} else
if( chr_size == 1 ) {
SetVROM_4K_Bank( 0, bank[0] );
SetVROM_4K_Bank( 4, bank[4] );
} else
if( chr_size == 2 ) {
SetVROM_2K_Bank( 0, bank[0] );
SetVROM_2K_Bank( 2, bank[2] );
SetVROM_2K_Bank( 4, bank[4] );
SetVROM_2K_Bank( 6, bank[6] );
} else {
SetVROM_8K_Bank( bank[0], bank[1], bank[2], bank[3], bank[4], bank[5], bank[6], bank[7] );
}
}
void Mapper083::Write( WORD addr, BYTE data )
{
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
switch( addr ) {
case 0x8000:
case 0xB000:
case 0xB0FF:
case 0xB1FF:
reg[0] = data;
chr_bank = (data&0x30)<<4;
SetPROM_16K_Bank( 4, data );
SetPROM_16K_Bank( 6, (data&0x30)|0x0F );
break;
case 0x8100:
reg[1] = data & 0x80;
data &= 0x03;
if( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
else if( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
else if( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
else SetVRAM_Mirror( VRAM_MIRROR4H );
break;
case 0x8200:
irq_counter = (irq_counter&0xFF00)|(INT)data;
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x8201:
irq_counter = (irq_counter&0x00FF)|((INT)data<<8);
irq_enable = reg[1];
// nes->cpu->ClrIRQ( IRQ_MAPPER );
break;
case 0x8300:
SetPROM_8K_Bank( 4, data );
break;
case 0x8301:
SetPROM_8K_Bank( 5, data );
break;
case 0x8302:
SetPROM_8K_Bank( 6, data );
break;
case 0x8310:
if( patch ) {
SetVROM_2K_Bank( 0, chr_bank|data );
} else {
SetVROM_1K_Bank( 0, chr_bank|data );
}
break;
case 0x8311:
if( patch ) {
SetVROM_2K_Bank( 2, chr_bank|data );
} else {
SetVROM_1K_Bank( 1, chr_bank|data );
}
break;
case 0x8312:
SetVROM_1K_Bank( 2, chr_bank|data );
break;
case 0x8313:
SetVROM_1K_Bank( 3, chr_bank|data );
break;
case 0x8314:
SetVROM_1K_Bank( 4, chr_bank|data );
break;
case 0x8315:
SetVROM_1K_Bank( 5, chr_bank|data );
break;
case 0x8316:
if( patch ) {
SetVROM_2K_Bank( 4, chr_bank|data );
} else {
SetVROM_1K_Bank( 6, chr_bank|data );
}
break;
case 0x8317:
if( patch ) {
SetVROM_2K_Bank( 6, chr_bank|data );
} else {
SetVROM_1K_Bank( 7, chr_bank|data );
}
break;
case 0x8318:
SetPROM_16K_Bank( 4, (reg[0]&0x30)|data );
break;
}
}
