void Mapper075::Write( WORD addr, BYTE data )
{
switch( addr & 0xF000 ) {
case 0x8000:
SetPROM_8K_Bank( 4, data );
break;
case 0x9000:
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
reg[0] = (reg[0] & 0x0F) | ((data & 0x02) << 3);
reg[1] = (reg[1] & 0x0F) | ((data & 0x04) << 2);
SetVROM_4K_Bank( 0, reg[0] );
SetVROM_4K_Bank( 4, reg[1] );
break;
case 0xA000:
SetPROM_8K_Bank( 5, data );
break;
case 0xC000:
SetPROM_8K_Bank( 6, data );
break;
case 0xE000:
reg[0] = (reg[0] & 0x10) | (data & 0x0F);
SetVROM_4K_Bank( 0, reg[0] );
break;
case 0xF000:
reg[1] = (reg[1] & 0x10) | (data & 0x0F);
SetVROM_4K_Bank( 4, reg[1] );
break;
}
}
//////////////////////////////////////////////////////////////////////////
// Mapper009 Nintendo MMC2 //
//////////////////////////////////////////////////////////////////////////
void Mapper009::Reset()
{
SetPROM_32K_Bank( 0, PROM_8K_SIZE-3, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
reg[0] = 0; reg[1] = 4;
reg[2] = 0; reg[3] = 0;
latch_a = 0xFE;
latch_b = 0xFE;
SetVROM_4K_Bank( 0, 4 );
SetVROM_4K_Bank( 4, 0 );
nes->ppu->SetChrLatchMode( TRUE );
}
void Mapper009::PPU_ChrLatch( WORD addr )
{
if( (addr&0x1FF0) == 0x0FD0 && latch_a != 0xFD ) {
latch_a = 0xFD;
SetVROM_4K_Bank( 0, reg[0] );
} else if( (addr&0x1FF0) == 0x0FE0 && latch_a != 0xFE ) {
latch_a = 0xFE;
SetVROM_4K_Bank( 0, reg[1] );
} else if( (addr&0x1FF0) == 0x1FD0 && latch_b != 0xFD ) {
latch_b = 0xFD;
SetVROM_4K_Bank( 4, reg[2] );
} else if( (addr&0x1FF0) == 0x1FE0 && latch_b != 0xFE ) {
latch_b = 0xFE;
SetVROM_4K_Bank( 4, reg[3] );
}
}
void Mapper090::SetBank_PPU()
{
INT bank[8];
for( INT i = 0; i < 8; i++ ) {
bank[i] = ((INT)chh_reg[i]<<8)|((INT)chl_reg[i]);
}
if( chr_size == 0 ) {
SetVROM_8K_Bank( bank[0] );
} else
if( chr_size == 1 ) {
SetVROM_4K_Bank( 0, bank[0] );
SetVROM_4K_Bank( 4, bank[4] );
} else
if( chr_size == 2 ) {
SetVROM_2K_Bank( 0, bank[0] );
SetVROM_2K_Bank( 2, bank[2] );
SetVROM_2K_Bank( 4, bank[4] );
SetVROM_2K_Bank( 6, bank[6] );
} else {
SetVROM_8K_Bank( bank[0], bank[1], bank[2], bank[3], bank[4], bank[5], bank[6], bank[7] );
}
}
void Mapper009::Write( WORD addr, BYTE data )
{
switch( addr & 0xF000 ) {
case 0xA000:
SetPROM_8K_Bank( 4, data );
break;
case 0xB000:
reg[0] = data;
if( latch_a == 0xFD ) {
SetVROM_4K_Bank( 0, reg[0] );
}
break;
case 0xC000:
reg[1] = data;
if( latch_a == 0xFE ) {
SetVROM_4K_Bank( 0, reg[1] );
}
break;
case 0xD000:
reg[2] = data;
if( latch_b == 0xFD ) {
SetVROM_4K_Bank( 4, reg[2] );
}
break;
case 0xE000:
reg[3] = data;
if( latch_b == 0xFE ) {
SetVROM_4K_Bank( 4, reg[3] );
}
break;
case 0xF000:
if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
break;
}
}
void Mapper001::Write( WORD addr, BYTE data )
{
// DEBUGOUT( "MMC1 %04X=%02X\n", addr&0xFFFF,data&0xFF );
if( wram_patch == 1 && addr == 0xBFFF ) {
wram_count++;
wram_bank += data&0x01;
if( wram_count == 5 ) {
if( wram_bank ) {
SetPROM_Bank( 3, &WRAM[0x2000], BANKTYPE_RAM );
} else {
SetPROM_Bank( 3, &WRAM[0x0000], BANKTYPE_RAM );
}
wram_bank = wram_count = 0;
}
}
if( patch != 1 ) {
if((addr & 0x6000) != (last_addr & 0x6000)) {
shift = regbuf = 0;
}
last_addr = addr;
}
if( data & 0x80 ) {
shift = regbuf = 0;
// reg[0] = 0x0C; // D3=1,D2=1
reg[0] |= 0x0C; // D3=1,D2=1 残りはリセットされない
return;
}
if( data&0x01 ) regbuf |= 1<<shift;
if( ++shift < 5 )
return;
addr = (addr&0x7FFF)>>13;
reg[addr] = regbuf;
// DEBUGOUT( "MMC1 %d=%02X\n", addr&0xFFFF,regbuf&0xFF );
regbuf = 0;
shift = 0;
if( patch != 1 ) {
// For Normal Cartridge
switch( addr ) {
case 0:
if( reg[0] & 0x02 ) {
if( reg[0] & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
else SetVRAM_Mirror( VRAM_VMIRROR );
} else {
if( reg[0] & 0x01 ) SetVRAM_Mirror( VRAM_MIRROR4H );
else SetVRAM_Mirror( VRAM_MIRROR4L );
}
break;
case 1:
// Register #1
if( VROM_1K_SIZE ) {
if( reg[0] & 0x10 ) {
// CHR 4K bank lower($0000-$0FFF)
SetVROM_4K_Bank( 0, reg[1] );
// CHR 4K bank higher($1000-$1FFF)
SetVROM_4K_Bank( 4, reg[2] );
} else {
// CHR 8K bank($0000-$1FFF)
SetVROM_8K_Bank( reg[1]>>1 );
}
} else {
// For Romancia
if( reg[0] & 0x10 ) {
SetCRAM_4K_Bank( 0, reg[1] );
}
}
break;
case 2:
// Register #2
if( VROM_1K_SIZE ) {
if( reg[0] & 0x10 ) {
// CHR 4K bank lower($0000-$0FFF)
SetVROM_4K_Bank( 0, reg[1] );
// CHR 4K bank higher($1000-$1FFF)
SetVROM_4K_Bank( 4, reg[2] );
} else {
// CHR 8K bank($0000-$1FFF)
SetVROM_8K_Bank( reg[1]>>1 );
}
} else {
// For Romancia
if( reg[0] & 0x10 ) {
SetCRAM_4K_Bank( 4, reg[2] );
}
}
break;
case 3:
if( !(reg[0] & 0x08) ) {
// PRG 32K bank ($8000-$FFFF)
SetPROM_32K_Bank( reg[3]>>1 );
} else {
void Mapper122::WriteLow( WORD addr, BYTE data )
{
if( addr == 0x6000 ) {
SetVROM_4K_Bank( 0, data & 0x07 );
SetVROM_4K_Bank( 4, (data & 0x70)>>4 );
}
