int main() { int delay; unsigned int inchar; unsigned int newlr; //Disable cache on OCM Xil_SetTlbAttributes(0xFFFF0000,0x14de2); // S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b0 SetupIntrSystem(&IntcInstancePtr); print("CPU0: writing startaddress for cpu1\n\r"); Xil_Out32(CPU1STARTADR, 0x00200000); dmb(); //waits until write has finished print("CPU0: sending the SEV to wake up CPU1\n\r"); sev(); while(1){ inchar = getchar(); newlr = getchar(); //for( delay = 0; delay < OP_DELAY; delay++)//wait //{} xil_printf("value %d",inchar); Xil_Out8(LED_PAT,inchar); } return 0; }
int init_platform() { #if __MICROBLAZE__ || __PPC__ enable_caches(); #ifdef PLATFORM_STDOUT_IS_16550 /* if we have a uart 16550, then that needs to be initialized */ XUartNs550_SetBaud(PLATFORM_STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, PLATFORM_BAUDRATE); XUartNs550_mSetLineControlReg(PLATFORM_STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); #endif platform_setup_interrupts(); /* initialize file system layer */ if (platform_init_fs() < 0) return -1; #endif #ifdef __arm__ if (Init_ScuTimer() != XST_SUCCESS) while(1); SetupIntrSystem(&TimerInstance, TIMER_IRPT_INTR); /* initialize file system layer */ if (platform_init_fs() < 0) return -1; #endif return 0; }
int Init_Zycap(XScuGic * InterruptController) { int Status; fatfs=malloc(sizeof(FATFS)); Status = SD_Init(fatfs); if (Status != XST_SUCCESS) { print("file system init failed\n\r"); exit(XST_FAILURE); } XDcfg_0 = XDcfg_Initialize(XPAR_XDCFG_0_DEVICE_ID); CdmaCfgPtr = XAxiDma_LookupConfig(XPAR_AXI_DMA_0_DEVICE_ID); if (!CdmaCfgPtr) { xil_printf("DMA pointer failed\r\n"); return XST_FAILURE; } Status = XAxiDma_CfgInitialize(&xcdma , CdmaCfgPtr); if (Status != XST_SUCCESS) { xil_printf("DMA initialization failed\r\n",Status); return XST_FAILURE; } //print("DMA init done\n\r"); Status = SetupIntrSystem(InterruptController, &xcdma, TX_INTR_ID); if (Status != XST_SUCCESS) { xil_printf("Failed intr setup\r\n"); return XST_FAILURE; } //Enable all interrupts XAxiDma_IntrEnable(&xcdma, XAXIDMA_IRQ_ALL_MASK,XAXIDMA_DMA_TO_DEVICE); bs_list = init_bs_list(MAX_BS_NUM); return XST_SUCCESS; }
/* * Main function * * This is main entry point to demonstrate this example. * * @return None * ******************************************************************************/ int main(){ int Status; XAxiVdma InstancePtr; XAxiVdma InstancePtr_1; xil_printf("\n--- Entering main() --- \r\n"); xil_printf("Starting the first VDMA \n\r"); /* Calling the API to configure and start VDMA without frame counter interrupt */ Status = run_triple_frame_buffer(&InstancePtr, 0, 1920, 1080, srcBuffer, 100, 0); if (Status != XST_SUCCESS) { xil_printf("Transfer of frames failed with error = %d\r\n",Status); return XST_FAILURE; } else { xil_printf("Transfer of frames started \r\n"); } xil_printf("Starting the second VDMA \r\n"); /* Calling the API to configure and start second VDMA with frame counter interrupt * Please note source buffer pointer is being offset a bit */ Status = run_triple_frame_buffer(&InstancePtr_1, 1, 1920, 1080, srcBuffer + 0x1000000, 100, 1); if (Status != XST_SUCCESS){ xil_printf("Transfer of frames failed with error = %d\r\n",Status); return XST_FAILURE; } else { xil_printf("Transfer of frames started \r\n"); } /* Enabling the interrupt for second VDMA */ SetupIntrSystem(&InstancePtr_1, XPAR_INTC_0_AXIVDMA_1_MM2S_INTROUT_VEC_ID, XPAR_INTC_0_AXIVDMA_1_S2MM_INTROUT_VEC_ID); /* Infinite while loop to let it run */ while(1); }
int XAxiCdma_HybridIntrExample(XScuGic *IntcInstancePtr, XAxiCdma *InstancePtr, u16 DeviceId,u32 IntrId) #endif { XAxiCdma_Config *CfgPtr; int Status; int SubmitTries = 10; /* Retry to submit */ /* Initialize the XAxiCdma device. */ CfgPtr = XAxiCdma_LookupConfig(DeviceId); if (!CfgPtr) { xdbg_printf(XDBG_DEBUG_ERROR, "Cannot find config structure for device %d\r\n", XPAR_AXICDMA_0_DEVICE_ID); return XST_FAILURE; } Status = XAxiCdma_CfgInitialize(InstancePtr, CfgPtr, CfgPtr->BaseAddress); if (Status != XST_SUCCESS) { xdbg_printf(XDBG_DEBUG_ERROR, "Initialization failed with %d\r\n", Status); return XST_FAILURE; } /* Setup the interrupt system */ Status = SetupIntrSystem(IntcInstancePtr, InstancePtr, IntrId); if (Status != XST_SUCCESS) { xdbg_printf(XDBG_DEBUG_ERROR, "Setup Intr system failed with %d\r\n", Status); return XST_FAILURE; } /* Enable all (completion/error/delay) interrupts */ XAxiCdma_IntrEnable(InstancePtr, XAXICDMA_XR_IRQ_ALL_MASK); /* First simple transfer */ Done = 0; Error = 0; Status = DoSimpleTransfer(InstancePtr, BUFFER_BYTESIZE, SubmitTries); if(Status != XST_SUCCESS) { DisableIntrSystem(IntcInstancePtr, IntrId); return XST_FAILURE; } xil_printf("First simple transfer successful\r\n"); /* The scatter gather transfer */ Done = 0; Error = 0; Status = DoSgTransfer(InstancePtr); if(Status != XST_SUCCESS) { DisableIntrSystem(IntcInstancePtr, IntrId); return XST_FAILURE; } xil_printf("Scatter gather transfer successful\r\n"); /* Second simple transfer */ Done = 0; Error = 0; Status = DoSimpleTransfer(InstancePtr, BUFFER_BYTESIZE, SubmitTries); if(Status != XST_SUCCESS) { DisableIntrSystem(IntcInstancePtr, IntrId); return XST_FAILURE; } xil_printf("Second simple transfer successful\r\n"); /* Test finishes successfully, clean up and return */ DisableIntrSystem(IntcInstancePtr, IntrId); return XST_SUCCESS; }
/** * * Main function * * This function is the main entry of the interrupt test. It does the following: * - Set up the output terminal if UART16550 is in the hardware build * - Initialize the DMA engine * - Set up Tx and Rx channels * - Set up the interrupt system for the Tx and Rx interrupts * - Submit a transfer * - Wait for the transfer to finish * - Check transfer status * - Disable Tx and Rx interrupts * - Print test status and exit * * @param None * * @return - XST_SUCCESS if tests pass * - XST_FAILURE if fails. * * @note None. * ******************************************************************************/ int main(void) { int Status; XAxiDma_Config *Config; /* Initial setup for Uart16550 */ #ifdef XPAR_UARTNS550_0_BASEADDR Uart550_Setup(); #endif xil_printf("\r\n--- Entering main() --- \r\n"); Config = XAxiDma_LookupConfig(DMA_DEV_ID); if (!Config) { xil_printf("No config found for %d\r\n", DMA_DEV_ID); return XST_FAILURE; } /* Initialize DMA engine */ XAxiDma_CfgInitialize(&AxiDma, Config); if(!XAxiDma_HasSg(&AxiDma)) { xil_printf("Device configured as Simple mode \r\n"); return XST_FAILURE; } /* Set up TX/RX channels to be ready to transmit and receive packets */ Status = TxSetup(&AxiDma); if (Status != XST_SUCCESS) { xil_printf("Failed TX setup\r\n"); return XST_FAILURE; } Status = RxSetup(&AxiDma); if (Status != XST_SUCCESS) { xil_printf("Failed RX setup\r\n"); return XST_FAILURE; } /* Set up Interrupt system */ Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID, 1); if (Status != XST_SUCCESS) { xil_printf("Failed intr setup\r\n"); return XST_FAILURE; } /* Initialize flags before start transfer test */ TxDone = 0; RxDone = 0; Error = 0; /* Send a packet */ Status = SendPacket(&AxiDma, TDEST0, TID0, PACKET0_DATA); if (Status != XST_SUCCESS) { xil_printf("Failed send packet\r\n"); return XST_FAILURE; } /* * Wait TX done and RX done */ while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) || (RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) { /* NOP */ } if (Error) { xil_printf("Failed test transmit%s done, " "receive%s done\r\n", TxDone? "":" not", RxDone? "":" not"); goto Done; }else { /* * Test finished, check data */ Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER, RxPacket1, PACKET0_DATA); if (Status != XST_SUCCESS) { xil_printf("Data check failed\r\n"); goto Done; } } xil_printf("Sent Packet with Tdest 0 Successfully\n\r"); /* Initialize flags before start transfer test */ TxDone = 0; RxDone = 0; Error = 0; /* Send a packet */ Status = SendPacket(&AxiDma, TDEST1, TID1, PACKET1_DATA); if (Status != XST_SUCCESS) { xil_printf("Failed send packet\r\n"); return XST_FAILURE; } /* * Wait TX done and RX done */ while (((TxDone < NUMBER_OF_BDS_TO_TRANSFER) || (RxDone < NUMBER_OF_BDS_TO_TRANSFER)) && !Error) { /* NOP */ } if (Error) { xil_printf("Failed test transmit%s done, " "receive%s done\r\n", TxDone? "":" not", RxDone? "":" not"); goto Done; }else { /* * Test finished, check data */ Status = CheckData(MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER, RxPacket0, PACKET1_DATA); if (Status != XST_SUCCESS) { xil_printf("Data check failed\r\n"); goto Done; } } /* Disable TX and RX Ring interrupts and return success */ DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID); xil_printf("Sent Packet with Tdest 1 Successfully\n\r"); xil_printf("AXI DMA SG interrupt Test passed\r\n"); Done: xil_printf("--- Exiting main() --- \r\n"); if (Status != XST_SUCCESS) { return XST_FAILURE; } return XST_SUCCESS; }
/** * * Main function * * This function is the main entry point of the example on DMA core. It sets up * DMA engine to be ready to receive and send frames, and start the transfers. * It waits for the transfer of the specified number of frame sets, and check * for transfer errors. * * @return * - XST_SUCCESS if example finishes successfully * - XST_FAILURE if example fails. * * @note None. * ******************************************************************************/ int vdma_setup(XIntc controller) { Intc = controller; int Status; XAxiVdma_Config *Config; XAxiVdma_FrameCounter FrameCfg; WriteDone = 0; ReadDone = 0; WriteError = 0; ReadError = 0; ReadFrameAddr = READ_ADDRESS_BASE; WriteFrameAddr = WRITE_ADDRESS_BASE; xil_printf("\r\n--- Entering vdma_setup() --- \r\n"); /* The information of the XAxiVdma_Config comes from hardware build. * The user IP should pass this information to the AXI DMA core. */ Config = XAxiVdma_LookupConfig(DMA_DEVICE_ID); if (!Config) { xil_printf( "No video DMA found for ID %d\r\n", DMA_DEVICE_ID); return XST_FAILURE; } /* Initialize DMA engine */ Status = XAxiVdma_CfgInitialize(&AxiVdma, Config, Config->BaseAddress); if (Status != XST_SUCCESS) { xil_printf( "Configuration Initialization failed %d\r\n", Status); return XST_FAILURE; } Status = XAxiVdma_SetFrmStore(&AxiVdma, NUMBER_OF_READ_FRAMES, XAXIVDMA_READ); if (Status != XST_SUCCESS) { xil_printf( "Setting Frame Store Number Failed in Read Channel" " %d\r\n", Status); return XST_FAILURE; } Status = XAxiVdma_SetFrmStore(&AxiVdma, NUMBER_OF_WRITE_FRAMES, XAXIVDMA_WRITE); if (Status != XST_SUCCESS) { xil_printf( "Setting Frame Store Number Failed in Write Channel" " %d\r\n", Status); return XST_FAILURE; } /* Setup frame counter and delay counter for both channels * * This is to monitor the progress of the test only * * WARNING: In free-run mode, interrupts may overwhelm the system. * In that case, it is better to disable interrupts. */ FrameCfg.ReadFrameCount = NUMBER_OF_READ_FRAMES; FrameCfg.WriteFrameCount = NUMBER_OF_WRITE_FRAMES; FrameCfg.ReadDelayTimerCount = DELAY_TIMER_COUNTER; FrameCfg.WriteDelayTimerCount = DELAY_TIMER_COUNTER; Status = XAxiVdma_SetFrameCounter(&AxiVdma, &FrameCfg); if (Status != XST_SUCCESS) { xil_printf( "Set frame counter failed %d\r\n", Status); if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } /* * Setup your video IP that writes to the memory */ /* Setup the write channel */ Status = WriteSetup(&AxiVdma); if (Status != XST_SUCCESS) { xil_printf( "Write channel setup failed %d\r\n", Status); if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } /* * Setup your video IP that reads from the memory */ /* Setup the read channel */ Status = ReadSetup(&AxiVdma); if (Status != XST_SUCCESS) { xil_printf( "Read channel setup failed %d\r\n", Status); if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } Status = SetupIntrSystem(&AxiVdma, READ_INTR_ID, WRITE_INTR_ID); if (Status != XST_SUCCESS) { xil_printf( "Setup interrupt system failed %d\r\n", Status); return XST_FAILURE; } /* Register callback functions */ // XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_GENERAL, ReadCallBack, // (void *)&AxiVdma, XAXIVDMA_READ); // // XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_ERROR, // ReadErrorCallBack, (void *)&AxiVdma, XAXIVDMA_READ); XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_GENERAL, WriteCallBack, (void *)&AxiVdma, XAXIVDMA_WRITE); XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_ERROR, WriteErrorCallBack, (void *)&AxiVdma, XAXIVDMA_WRITE); /* Enable your video IP interrupts if needed */ /* Start the DMA engine to transfer */ Status = StartTransfer(&AxiVdma); if (Status != XST_SUCCESS) { if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } /* Enable DMA read and write channel interrupts * * If interrupts overwhelms the system, please do not enable interrupt */ // XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_FRMCNT_MASK, XAXIVDMA_WRITE); // XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_FRMCNT_MASK, XAXIVDMA_READ); /* Every set of frame buffer finish causes a completion interrupt */ // while ((WriteDone < NUM_TEST_FRAME_SETS) && !ReadError && // (ReadDone < NUM_TEST_FRAME_SETS) && !WriteError) { // /* NOP */ // } // if (ReadError || WriteError) { // xil_printf("Test has transfer error %d/%d\r\n", // ReadError, WriteError); // // Status = XST_FAILURE; // } // else { // xil_printf("Test passed\r\n"); // } xil_printf("\r\n--- Exiting vdma_setup() --- \r\n"); // DisableIntrSystem(READ_INTR_ID, WRITE_INTR_ID); if (Status != XST_SUCCESS) { if(Status == XST_VDMA_MISMATCH_ERROR) xil_printf("DMA Mismatch Error\r\n"); return XST_FAILURE; } return XST_SUCCESS; }
/** * * Main function * * This function is the main entry of the interrupt test. It does the following: * Set up the output terminal if UART16550 is in the hardware build * Initialize the DMA engine * Set up Tx and Rx channels * Set up the interrupt system for the Tx and Rx interrupts * Submit a transfer * Wait for the transfer to finish * Check transfer status * Disable Tx and Rx interrupts * Print test status and exit * * @param None * * @return * - XST_SUCCESS if example finishes successfully * - XST_FAILURE if example fails. * * @note None. * ******************************************************************************/ int main(void) { int Status; XAxiDma_Config *Config; int Tries = NUMBER_OF_TRANSFERS; int Index; u8 *TxBufferPtr; u8 *RxBufferPtr; u8 Value; TxBufferPtr = (u8 *)TX_BUFFER_BASE ; RxBufferPtr = (u8 *)RX_BUFFER_BASE; /* Initial setup for Uart16550 */ #ifdef XPAR_UARTNS550_0_BASEADDR Uart550_Setup(); #endif xil_printf("\r\n--- Entering main() --- \r\n"); Config = XAxiDma_LookupConfig(DMA_DEV_ID); if (!Config) { xil_printf("No config found for %d\r\n", DMA_DEV_ID); return XST_FAILURE; } /* Initialize DMA engine */ Status = XAxiDma_CfgInitialize(&AxiDma, Config); if (Status != XST_SUCCESS) { xil_printf("Initialization failed %d\r\n", Status); return XST_FAILURE; } if(XAxiDma_HasSg(&AxiDma)){ xil_printf("Device configured as SG mode \r\n"); return XST_FAILURE; } /* Set up Interrupt system */ Status = SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID); if (Status != XST_SUCCESS) { xil_printf("Failed intr setup\r\n"); return XST_FAILURE; } /* Disable all interrupts before setup */ XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DMA_TO_DEVICE); XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA); /* Enable all interrupts */ XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DMA_TO_DEVICE); XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK, XAXIDMA_DEVICE_TO_DMA); /* Initialize flags before start transfer test */ TxDone = 0; RxDone = 0; Error = 0; Value = TEST_START_VALUE; for(Index = 0; Index < MAX_PKT_LEN; Index ++) { TxBufferPtr[Index] = Value; Value = (Value + 1) & 0xFF; } /* Flush the SrcBuffer before the DMA transfer, in case the Data Cache * is enabled */ Xil_DCacheFlushRange((u32)TxBufferPtr, MAX_PKT_LEN); #ifdef __aarch64__ Xil_DCacheFlushRange((UINTPTR)RxBufferPtr, MAX_PKT_LEN); #endif /* Send a packet */ for(Index = 0; Index < Tries; Index ++) { Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA); if (Status != XST_SUCCESS) { return XST_FAILURE; } Status = XAxiDma_SimpleTransfer(&AxiDma,(u32) TxBufferPtr, MAX_PKT_LEN, XAXIDMA_DMA_TO_DEVICE); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Wait TX done and RX done */ while (!TxDone && !RxDone && !Error) { /* NOP */ } if (Error) { xil_printf("Failed test transmit%s done, " "receive%s done\r\n", TxDone? "":" not", RxDone? "":" not"); goto Done; } /* * Test finished, check data */ Status = CheckData(MAX_PKT_LEN, 0xC); if (Status != XST_SUCCESS) { xil_printf("Data check failed\r\n"); goto Done; } } xil_printf("AXI DMA interrupt example test passed\r\n"); /* Disable TX and RX Ring interrupts and return success */ DisableIntrSystem(&Intc, TX_INTR_ID, RX_INTR_ID); Done: xil_printf("--- Exiting main() --- \r\n"); return XST_SUCCESS; }
int XAxiCdma_SgIntrExample(XScuGic *IntcInstancePtr, XAxiCdma *InstancePtr, u16 DeviceId,u32 IntrId) #endif { XAxiCdma_Config *CfgPtr; int Status; u8 *SrcPtr; u8 *DstPtr; SrcPtr = (u8 *)TransmitBufferPtr; DstPtr = (u8 *)ReceiveBufferPtr; #ifdef __aarch64__ Xil_SetTlbAttributes(BD_SPACE_BASE, MARK_UNCACHEABLE); #endif /* Initialize the XAxiCdma device. */ CfgPtr = XAxiCdma_LookupConfig(DeviceId); if (!CfgPtr) { xdbg_printf(XDBG_DEBUG_ERROR, "Cannot find config structure for device %d\r\n", XPAR_AXICDMA_0_DEVICE_ID); return XST_FAILURE; } Status = XAxiCdma_CfgInitialize(InstancePtr, CfgPtr, CfgPtr->BaseAddress); if (Status != XST_SUCCESS) { xdbg_printf(XDBG_DEBUG_ERROR, "Initialization failed with %d\r\n", Status); return XST_FAILURE; } /* Setup the BD ring */ Status = SetupTransfer(InstancePtr); if (Status != XST_SUCCESS) { xdbg_printf(XDBG_DEBUG_ERROR, "Setup BD ring failed with %d\r\n", Status); return XST_FAILURE; } /* Setup the interrupt system */ Status = SetupIntrSystem(IntcInstancePtr, InstancePtr, IntrId); if (Status != XST_SUCCESS) { xdbg_printf(XDBG_DEBUG_ERROR, "Setup Intr system failed with %d\r\n", Status); return XST_FAILURE; } /* Enable completion and error interrupts */ XAxiCdma_IntrEnable(InstancePtr, XAXICDMA_XR_IRQ_ALL_MASK); /* Start the DMA transfer */ Status = DoTransfer(InstancePtr); if (Status != XST_SUCCESS) { xdbg_printf(XDBG_DEBUG_ERROR, "Do transfer failed with %d\r\n", Status); return XST_FAILURE; } /* Wait until the DMA transfer is done */ while ((Done < NUMBER_OF_BDS_TO_TRANSFER) && !Error) { /* Wait */ } if(Error) { xdbg_printf(XDBG_DEBUG_ERROR, "Transfer has error %x\r\n", (unsigned int)XAxiCdma_GetError(InstancePtr)); DisableIntrSystem(IntcInstancePtr, IntrId); return XST_FAILURE; } /* Transfer completes successfully, check data */ Status = CheckData(SrcPtr, DstPtr, MAX_PKT_LEN * NUMBER_OF_BDS_TO_TRANSFER); if (Status != XST_SUCCESS) { xdbg_printf(XDBG_DEBUG_ERROR, "Check data failed for sg " "transfer\r\n"); DisableIntrSystem(IntcInstancePtr, IntrId); return XST_FAILURE; } /* Test finishes successfully, clean up and return */ DisableIntrSystem(IntcInstancePtr, IntrId); return XST_SUCCESS; }
/** * * This function demonstrates the usage Traffic Generator * It does the following: * - Set up the output terminal if UART16550 is in the hardware build * - Initialize the AXI Traffic Generator device * - Initialize Master RAM * - Initialize commands and add them to list * - Program internal command and parameter RAMs * - Start Master Logic * - Wait for the master logic to finish * - Check for errors * - Read Master RAM and verify data * - Return test status and exit * * @param InstancePtr is a pointer to the instance of the * XTrafGen component. * @param DeviceId is Device ID of the Axi Traffic Generator Device, * typically XPAR_<TRAFGEN_instance>_DEVICE_ID value from * xparameters.h. * * @return -XST_SUCCESS to indicate success * -XST_FAILURE to indicate failure * ******************************************************************************/ int XTrafGenInterruptExample(XTrafGen *InstancePtr, u16 DeviceId) { XTrafGen_Config *Config; XTrafGen_Cmd Cmd; XTrafGen_Cmd *CmdPtr = &Cmd; u32 MasterRamIndex = 0; int Status = XST_SUCCESS; int Index; /* Initial setup for Uart16550 */ #ifdef XPAR_UARTNS550_0_BASEADDR Uart550_Setup(); #endif /* Initialize the Device Configuration Interface driver */ Config = XTrafGen_LookupConfig(DeviceId); if (!Config) { xil_printf("No config found for %d\r\n", DeviceId); return XST_FAILURE; } /* * This is where the virtual address would be used, this example * uses physical address. */ Status = XTrafGen_CfgInitialize(InstancePtr, Config, Config->BaseAddress); if (Status != XST_SUCCESS) { xil_printf("Initialization failed\n\r"); return Status; } /* Program Master RAM with Test Data */ XTrafGen_AccessMasterRam(InstancePtr, MasterRamIndex, sizeof(MasterRamData), XTG_WRITE, MasterRamData); /* Initialize default command fields */ InitDefaultCommands(CmdPtr); /* Add Valid Command for Write Region */ CmdPtr->CRamCmd.Address = AXI_ADDRESS; CmdPtr->CRamCmd.MasterRamIndex = 0x0; CmdPtr->CRamCmd.Length = TEST_LENGTH - 1; CmdPtr->RdWrFlag = XTG_WRITE; CmdPtr->CRamCmd.ValidCmd = 1; CmdPtr->CRamCmd.MyDepend = 0; CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr, XTG_WRITE) + 1; Status = XTrafGen_AddCommand(InstancePtr, CmdPtr); if (Status != XST_SUCCESS) { xil_printf("AddCommand() failed\n\r"); return Status; } /* Add Valid Command for Read Region */ CmdPtr->CRamCmd.Address = AXI_ADDRESS; CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX; CmdPtr->CRamCmd.Length = 7; CmdPtr->CRamCmd.Size = 0x2; CmdPtr->RdWrFlag = XTG_READ; CmdPtr->CRamCmd.ValidCmd = 1; CmdPtr->CRamCmd.MyDepend = 0; /* Make this command dependent on Write logic command 1 */ CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr, XTG_WRITE) + 1; Status = XTrafGen_AddCommand(InstancePtr, CmdPtr); if (Status != XST_SUCCESS) { xil_printf("AddCommand() failed\n\r"); return Status; } /* Add second valid command to Write Region */ CmdPtr->CRamCmd.Address = AXI_ADDRESS + MSTRRAM_INDEX; CmdPtr->CRamCmd.MasterRamIndex = MSTRRAM_INDEX; CmdPtr->CRamCmd.Length = 0; CmdPtr->RdWrFlag = XTG_WRITE; CmdPtr->CRamCmd.ValidCmd = 1; CmdPtr->CRamCmd.MyDepend = 0; /* Make this command dependent on Read logic command 1 */ CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr, XTG_READ) + 1; Status = XTrafGen_AddCommand(InstancePtr, CmdPtr); if (Status != XST_SUCCESS) { xil_printf("AddCommand() failed\n\r"); return Status; } /* Add invalid command at the end of Write Queue */ CmdPtr->CRamCmd.Address = AXI_ADDRESS; CmdPtr->CRamCmd.MasterRamIndex = 0x0; CmdPtr->RdWrFlag = XTG_WRITE; CmdPtr->CRamCmd.Size = 0; CmdPtr->CRamCmd.ValidCmd = 0; CmdPtr->CRamCmd.MyDepend = 0; /* Make this command dependent on Read logic command 1 */ CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr, XTG_READ) + 1;; Status = XTrafGen_AddCommand(InstancePtr, CmdPtr); if (Status != XST_SUCCESS) { xil_printf("AddCommand() failed\n\r"); return Status; } /* Add invalid command at the end of Read Queue */ CmdPtr->CRamCmd.MasterRamIndex = 0x0; CmdPtr->RdWrFlag = XTG_READ; CmdPtr->CRamCmd.Length = 0; CmdPtr->CRamCmd.Size = 0x0; CmdPtr->CRamCmd.ValidCmd = 0; /* Make this command dependent on Write logic command 2 */ CmdPtr->CRamCmd.OtherDepend = XTrafGen_GetLastValidIndex(InstancePtr, XTG_WRITE) + 1; Status = XTrafGen_AddCommand(InstancePtr, CmdPtr); if (Status != XST_SUCCESS) { xil_printf("AddCommand() failed\n\r"); return Status; } /* Display Command list */ #ifdef DEBUG XTrafGen_PrintCmds(InstancePtr); #endif /* Program all prepared commands */ Status = XTrafGen_WriteCmdsToHw(InstancePtr); if (Status != XST_SUCCESS) { xil_printf("WriteCmdsToHw() failed\n\r"); return Status; } /* Enable Complete Interrupt bit */ XTrafGen_EnableMasterCmpInterrupt(InstancePtr); /* Set up Interrupt system */ Status = SetupIntrSystem(&Intc, InstancePtr, CMP_INTR_ID, ERR_INTR_ID); if (Status != XST_SUCCESS) { xil_printf("Failed intr setup\r\n"); return Status; } /* Initialize flags before start transfer test */ Done = 0; Error = 0; /* Start Master Logic */ XTrafGen_StartMasterLogic(InstancePtr); while (!Done && !Error); if (Error) { xil_printf("Errors in transfer\r\n"); return XST_FAILURE; } /* Read Master RAM */ XTrafGen_AccessMasterRam(InstancePtr, MSTRRAM_INDEX, sizeof(MasterRamData), XTG_READ, VerifyRamData); /* Verify Data */ for (Index = 0 ; Index < TEST_LENGTH - 1; Index++) { if (VerifyRamData[Index] != MasterRamData[Index]) { xil_printf("Data Mismatch\n\r"); return XST_FAILURE; } } DisableIntrSystem(&Intc, CMP_INTR_ID, ERR_INTR_ID); return Status; }