void
set_palette (void)
{
int i, j;
if (console_blanked || vt_cons[fg_console]->vc_mode == KD_GRAPHICS)
return;
if (tga_type == 0) { /* 8-plane */
BT485_WRITE(0x00, BT485_ADDR_PAL_WRITE);
TGA_WRITE_REG(BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
for (i = 0; i < 16; i++) {
j = color_table[i];
TGA_WRITE_REG(default_red[j]|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
TGA_WRITE_REG(default_grn[j]|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
TGA_WRITE_REG(default_blu[j]|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
}
} else {
BT463_LOAD_ADDR(0x0000);
TGA_WRITE_REG((BT463_PALETTE<<2), TGA_RAMDAC_REG);
for (i = 0; i < 16; i++) {
j = color_table[i];
TGA_WRITE_REG(default_red[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
TGA_WRITE_REG(default_grn[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
TGA_WRITE_REG(default_blu[j]|(BT463_PALETTE<<10), TGA_RAMDAC_REG);
}
}
}
/*
* Hide the cursor from view, during blanking, usually...
*/
void
hide_cursor(void)
{
unsigned long flags;
save_flags(flags); cli();
if (tga_type == 0) {
BT485_WRITE(0x20, BT485_CMD_2);
} else {
TGA_WRITE_REG(0x03, TGA_VALID_REG); /* SCANNING and BLANK */
}
restore_flags(flags);
}
/**
* tgafb_set_par - Optional function. Alters the hardware state.
* @info: frame buffer structure that represents a single frame buffer
*/
static int
tgafb_set_par(struct fb_info *info)
{
static unsigned int const deep_presets[4] = {
0x00004000,
0x0000440d,
0xffffffff,
0x0000441d
};
static unsigned int const rasterop_presets[4] = {
0x00000003,
0x00000303,
0xffffffff,
0x00000303
};
static unsigned int const mode_presets[4] = {
0x00000000,
0x00000300,
0xffffffff,
0x00000300
};
static unsigned int const base_addr_presets[4] = {
0x00000000,
0x00000001,
0xffffffff,
0x00000001
};
struct tga_par *par = (struct tga_par *) info->par;
int tga_bus_pci = TGA_BUS_PCI(par->dev);
int tga_bus_tc = TGA_BUS_TC(par->dev);
u32 htimings, vtimings, pll_freq;
u8 tga_type;
int i;
/* Encode video timings. */
htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
| (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
vtimings = (info->var.yres & TGA_VERT_ACTIVE);
htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
htimings |= TGA_HORIZ_POLARITY;
if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
vtimings |= TGA_VERT_POLARITY;
par->htimings = htimings;
par->vtimings = vtimings;
par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
/* Store other useful values in par. */
par->xres = info->var.xres;
par->yres = info->var.yres;
par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
par->bits_per_pixel = info->var.bits_per_pixel;
tga_type = par->tga_type;
/* First, disable video. */
TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
/* Write the DEEP register. */
while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
continue;
mb();
TGA_WRITE_REG(par, deep_presets[tga_type] |
(par->sync_on_green ? 0x0 : 0x00010000),
TGA_DEEP_REG);
while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
continue;
mb();
/* Write some more registers. */
TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
/* Calculate & write the PLL. */
tgafb_set_pll(par, pll_freq);
/* Write some more registers. */
TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
/* Init video timing regs. */
TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
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