Exemple #1
0
void Pwm_stm32::write_channel(void)
{
    //select the output period
    if (TIM_ARR(timer_) > period_)
    {
        print_util_dbg_print("should keep slower period.\r\n");
    }
    else
    {
        TIM_ARR(timer_) = period_;
    }
    
    if(channel_id_ == PWM_STM32_CHANNEL_1)
    {
        //select duty cycle
        TIM_CCR1(timer_) = duty_cyle_;
    }
    else if(channel_id_ == PWM_STM32_CHANNEL_2)
    {
        //select duty cycle
        TIM_CCR2(timer_) = duty_cyle_;
    }
    else if(channel_id_ == PWM_STM32_CHANNEL_3)
    {
        //select duty cycle
        TIM_CCR3(timer_) = duty_cyle_;
    }
    else if(channel_id_ == PWM_STM32_CHANNEL_4)
    {
        //select duty cycle
        TIM_CCR4(timer_) = duty_cyle_;
    }
}
Exemple #2
0
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value)
{
	switch (oc_id) {
	case TIM_OC1:
		TIM_CCR1(timer_peripheral) = value;
		break;
	case TIM_OC2:
		TIM_CCR2(timer_peripheral) = value;
		break;
	case TIM_OC3:
		TIM_CCR3(timer_peripheral) = value;
		break;
	case TIM_OC4:
		TIM_CCR4(timer_peripheral) = value;
		break;
	case TIM_OC1N:
	case TIM_OC2N:
	case TIM_OC3N:
		/* Ignoring as this option applies to the whole channel. */
		break;
	}
}
Exemple #3
0
bool Pwm_stm32::init(void)
{
    bool success = true;
    
    /* Enable peripheral port & TIM clock. */
    //rcc_periph_clock_enable(RCC_GPIOx);
    rcc_periph_clock_enable(pwm_config_.rcc_timer_config);

    gpio_mode_setup(pwm_config_.gpio_config.port, GPIO_MODE_AF, GPIO_PUPD_NONE, pwm_config_.gpio_config.pin);
    gpio_set_af(pwm_config_.gpio_config.port, pwm_config_.gpio_config.alt_fct, pwm_config_.gpio_config.pin);
    gpio_set_output_options(pwm_config_.gpio_config.port, GPIO_OTYPE_PP, GPIO_OSPEED_100MHZ, pwm_config_.gpio_config.port);
  
    //WARNING Common to all channels of that TIMER
    //select prescaler
    TIM_PSC(pwm_config_.timer_config) = prescaler_;
    //select the output period
    TIM_ARR(pwm_config_.timer_config) = period_;
    //enable the autoreload
    TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_ARPE;
    //select counting mode (edge-aligned)
    TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_CMS_EDGE;
    //counting up
    TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_DIR_UP;
    //enable counter
    TIM_CR1(pwm_config_.timer_config) |= TIM_CR1_CEN;

    //CHANNEL SPECIFIC
    if (pwm_config_.channel_config == PWM_STM32_CHANNEL_1)
    {
        //Disable channel1
        TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC1E; 
        //Reset output compare
        TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_OC1M_MASK;
        TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_CC1S_MASK;

        //Select output mode
        TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_CC1S_OUT;
        //select polarity low
        TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC1NP;
        //select PWM mode 1
        TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC1M_PWM1;

        //select duty cycle
        TIM_CCR1(pwm_config_.timer_config) = duty_cyle_;

        //set the preload bit
        TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC1PE;
        
        //enable capture/compare
        TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC1E;
    }
    else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_2)
    {
        //Disable channel2
        TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC2E; 
        //Reset output compare
        TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_OC2M_MASK;
        TIM_CCMR1(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR1_CC2S_MASK;

        //Select output mode
        TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_CC2S_OUT;
        //select polarity low
        TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC2NP;
        //select PWM mode 1
        TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC2M_PWM1;

        //select duty cycle
        TIM_CCR2(pwm_config_.timer_config) = duty_cyle_;

        //set the preload bit
        TIM_CCMR1(pwm_config_.timer_config) |= TIM_CCMR1_OC2PE;
        
        //enable capture/compare
        TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC2E;
    }
    else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_3)
    {
        //Disable channel3
        TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC3E; 
        //Reset output compare
        TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_OC3M_MASK;
        TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_CC3S_MASK;

        //Select output mode
        TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_CC3S_OUT;
        //select polarity low
        TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC3NP;
        //select PWM mode 1
        TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC3M_PWM1;

        //select duty cycle
        TIM_CCR3(pwm_config_.timer_config) = duty_cyle_;

        //set the preload bit
        TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC3PE;
        
        //enable capture/compare
        TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC3E;
    }
    else if (pwm_config_.channel_config == PWM_STM32_CHANNEL_4)
    {
        //Disable channel4
        TIM_CCER(pwm_config_.timer_config) &= (uint16_t)~TIM_CCER_CC4E; 
        //Reset output compare
        TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_OC4M_MASK;
        TIM_CCMR2(pwm_config_.timer_config) &= (uint16_t)~TIM_CCMR2_CC4S_MASK;

        //Select output mode
        TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_CC4S_OUT;
        //select polarity low
        TIM_CCER(pwm_config_.timer_config) |= (1 << 15); //TODO TIM_CCER_CC4NP does not exist in libopencm3 library
        //select PWM mode 1
        TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC4M_PWM1;

        //select duty cycle
        TIM_CCR4(pwm_config_.timer_config) = duty_cyle_;

        //set the preload bit
        TIM_CCMR2(pwm_config_.timer_config) |= TIM_CCMR2_OC4PE;
        
        //enable capture/compare
        TIM_CCER(pwm_config_.timer_config) |= TIM_CCER_CC4E;
    }

    return success;
}