/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
/*!< At this stage the microcontroller clock setting is already configured,
this is done through SystemInit() function which is called from startup
files (startup_stm32f40_41xxx.s/startup_stm32f427_437xx.s/startup_stm32f429_439xx.s)
before to branch to application main.
To reconfigure the default setting of SystemInit() function, refer to
system_stm32f4xx.c file
*/
/* TIM1 Configuration */
TIM_Config();
/* Time base configuration */
/* -----------------------------------------------------------------------
TIM1 Configuration: generate 1 PWM signal using the DMA burst mode:
TIM1 input clock (TIM1CLK) is set to 2 * APB2 clock (PCLK2),
since APB2 prescaler is different from 1.
TIM1CLK = 2 * PCLK2
PCLK2 = HCLK / 2
=> TIM1CLK = 2 * (HCLK / 2) = HCLK = SystemCoreClock
To get TIM1 counter clock at 24 MHz, the prescaler is computed as follows:
Prescaler = (TIM1CLK / TIM1 counter clock) - 1
Prescaler = (SystemCoreClock /24 MHz) - 1
The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1)
= 24 MHz / 4096 = 5.85 KHz
TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR)* 100 = 33.33%
Note:
SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file.
Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
function to update SystemCoreClock variable value. Otherwise, any configuration
based on this variable will be incorrect.
----------------------------------------------------------------------- */
TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t) (SystemCoreClock / 24000000) - 1;
TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
/* TIM Configuration in PWM Mode */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = 0xFFF;
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
/* TIM1 DMAR Base register and DMA Burst Length Config */
TIM_DMAConfig(TIM1, TIM_DMABase_ARR, TIM_DMABurstLength_3Transfers);
/* TIM1 DMA Update enable */
TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
/* TIM1 enable */
TIM_Cmd(TIM1, ENABLE);
/* TIM1 PWM Outputs Enable */
TIM_CtrlPWMOutputs(TIM1, ENABLE);
/* Enable DMA2 Stream5 */
DMA_Cmd(DMA2_Stream5, ENABLE);
/* Wait until DMA2 Stream5 end of Transfer */
while (!DMA_GetFlagStatus(DMA2_Stream5, DMA_FLAG_TCIF5))
{
}
/* Infinite loop */
while(1)
{
}
}
/**
* @brief Configure the TIM1 Pins.
* @param None
* @retval None
*/
static void TIM_Config(void)
{
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
GPIO_InitTypeDef GPIO_InitStructure;
/* TIM1 clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
/* GPIOA clock enable */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
/* DMA2 clock enable */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
/* GPIOA Configuration: PA8(TIM1 CH1) as alternate function push-pull ------*/
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* Connect TIM pins to AF2 */
GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_2);
/* Time base configuration */
/* -----------------------------------------------------------------------
TIM1 Configuration: generate 1 PWM signal using the DMA burst mode:
TIM1 input clock (TIM1CLK) is set to APB2 clock (PCLK2)
TIM1CLK = PCLK2
PCLK2 = HCLK
=> TIM1CLK = HCLK = SystemCoreClock
To get TIM1 counter clock at 24 MHz, the prescaler is computed as follows:
Prescaler = (TIM1CLK / TIM1 counter clock) - 1
Prescaler = (SystemCoreClock /24 MHz) - 1
TIM1 Frequency = TIM1 counter clock/(ARR + 1)
= 24 MHz / 4096 = 5.85 KHz
TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR)* 100 = 33.33%
Note:
SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f0xx.c file.
Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
function to update SystemCoreClock variable value. Otherwise, any configuration
based on this variable will be incorrect.
----------------------------------------------------------------------- */
TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t) (SystemCoreClock / 24000000) - 1;
TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
/* TIM Configuration in PWM Mode */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = 0xFFF;
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
/* TIM1 DMAR Base register and DMA Burst Length Config */
TIM_DMAConfig(TIM1, TIM_DMABase_ARR, TIM_DMABurstLength_3Transfers);
/* TIM1 DMA Update enable */
TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
/* TIM1 enable */
TIM_Cmd(TIM1, ENABLE);
/* TIM1 PWM Outputs Enable */
TIM_CtrlPWMOutputs(TIM1, ENABLE);
}
/**
* @brief Main program
* @param None
* @retval None
*/
int main(void)
{
/*!< At this stage the microcontroller clock setting is already configured,
this is done through SystemInit() function which is called from startup
file (startup_stm32f10x_xx.s) before to branch to application main.
To reconfigure the default setting of SystemInit() function, refer to
system_stm32f10x.c file
*/
/* TIM1 and GPIOA clock enable */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA, ENABLE);
/* DMA clock enable */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
/* GPIOA Configuration: Channel 1 as alternate function push-pull */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStructure);
/* TIM1 DeInit */
TIM_DeInit(TIM1);
/* DMA1 Channel5 Config */
DMA_DeInit(DMA1_Channel5);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)TIM1_DMAR_ADDRESS;
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)SRC_Buffer;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_BufferSize = 3;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(DMA1_Channel5, &DMA_InitStructure);
/* Time base configuration */
/* -----------------------------------------------------------------------
TIM1 Configuration: generate 1 PWM signal using the DMA burst mode:
The TIM1CLK frequency is set to SystemCoreClock (Hz), to get TIM1 counter
clock at 24 MHz the Prescaler is computed as following:
- Prescaler = (TIM1CLK / TIM1 counter clock) - 1
SystemCoreClock is set to 72 MHz for Low-density, Medium-density, High-density
and Connectivity line devices and to 24 MHz for Low-Density Value line and
Medium-Density Value line devices
The TIM1 period is 5.8 KHz: TIM1 Frequency = TIM1 counter clock/(ARR + 1)
= 24 MHz / 4096 = 5.8KHz KHz
TIM1 Channel1 duty cycle = (TIM1_CCR1/ TIM1_ARR)* 100 = 33.33%
----------------------------------------------------------------------- */
TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t) (SystemCoreClock / 24000000) - 1;
TIM_TimeBaseStructure.TIM_ClockDivision = 0x0;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
/* TIM Configuration in PWM Mode */
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
TIM_OCInitStructure.TIM_Pulse = 0xFFF;
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
/* TIM1 DMAR Base register and DMA Burst Length Config */
TIM_DMAConfig(TIM1, TIM_DMABase_ARR, TIM_DMABurstLength_3Transfers);
/* TIM1 DMA Update enable */
TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
/* TIM1 enable */
TIM_Cmd(TIM1, ENABLE);
/* TIM1 PWM Outputs Enable */
TIM_CtrlPWMOutputs(TIM1, ENABLE);
/* DMA1 Channel5 enable */
DMA_Cmd(DMA1_Channel5, ENABLE);
/* Wait until DMA1 Channel5 end of Transfer */
while (!DMA_GetFlagStatus(DMA1_FLAG_TC5))
{
}
/* Infinite loop */
while(1)
{
}
}
/*************************************************************
* TIM4 Initialization
**************************************************************/
void TIM4_Init()
{
#if (STRCMP($tim4IntEn$, 0) == 0)
NVIC_InitTypeDef NVIC_InitStructure;
#endif
#if (STRCMP($ch1_0Pin$, DISABLE) == 0 || STRCMP($ch1_1Pin$, DISABLE) == 0 || \
STRCMP($ch2_0Pin$, DISABLE) == 0 || STRCMP($ch2_1Pin$, DISABLE) == 0 || \
STRCMP($ch3_0Pin$, DISABLE) == 0 || STRCMP($ch3_1Pin$, DISABLE) == 0 || \
STRCMP($ch4_0Pin$, DISABLE) == 0 || STRCMP($ch4_1Pin$, DISABLE) == 0)
GPIO_InitTypeDef GPIO_InitStructure;
#endif
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
#if ( (STRCMP($ch1En$, DISABLE) == 0 && STRCMP($ch1sel$, CAPTURE_ENABLE) == 0) || \
(STRCMP($ch2En$, DISABLE) == 0 && STRCMP($ch2sel$, CAPTURE_ENABLE) == 0) || \
(STRCMP($ch3En$, DISABLE) == 0 && STRCMP($ch3sel$, CAPTURE_ENABLE) == 0) || \
(STRCMP($ch4En$, DISABLE) == 0 && STRCMP($ch4sel$, CAPTURE_ENABLE) == 0) )
TIM_OCInitTypeDef TIM_OCInitStructure;
#endif
#if ( (STRCMP($ch1En$, DISABLE) == 0 && STRCMP($ch1sel$, COMPARE_ENABLE) == 0) || \
(STRCMP($ch2En$, DISABLE) == 0 && STRCMP($ch2sel$, COMPARE_ENABLE) == 0) || \
(STRCMP($ch3En$, DISABLE) == 0 && STRCMP($ch3sel$, COMPARE_ENABLE) == 0) || \
(STRCMP($ch4En$, DISABLE) == 0 && STRCMP($ch4sel$, COMPARE_ENABLE) == 0) )
TIM_ICInitTypeDef TIM_ICInitStructure;
#endif
//PUT_A_NEW_LINE_HERE
//
// Enable TIM4 clock
//
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
#if (STRCMP($tim4PinRemap$, DEFAULT) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Enable TIM4's GPIOD, GPIOE, AFIO clock
//
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE);
#else
//PUT_A_NEW_LINE_HERE
//
// Enable TIM4's GPIOB , GPIOE, AFIO clock
//
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE);
#endif
#if (STRCMP($tim4PinRemap$, DEFAULT) == 1)
#if (STRCMP($ch1_0Pin$, DISABLE) == 0 || STRCMP($ch2_0Pin$, DISABLE) == 0 || STRCMP($ch3_0Pin$, DISABLE) == 0 || STRCMP($ch4_0Pin$, DISABLE) == 0)
//
// Configure TIM4 pins: ETR, CH1, CH2, CH3, CH4, when Pin Remap is Default
//
#endif
#if (STRCMP($etrPin$, DISABLE) == 0)
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOE, &GPIO_InitStructure);
#endif
#if (STRCMP($ch1_0Pin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
#if (STRCMP($ch1sel$, CAPTURE_ENABLE) == 1)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
#else
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
#endif
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOB, &GPIO_InitStructure);
#endif
#if (STRCMP($ch2_0Pin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
#if (STRCMP($ch2sel$, CAPTURE_ENABLE) == 1)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
#else
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
#endif
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOB, &GPIO_InitStructure);
#endif
#if (STRCMP($ch3_0Pin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
#if (STRCMP($ch3sel$, CAPTURE_ENABLE) == 1)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
#else
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
#endif
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOB, &GPIO_InitStructure);
#endif
#if (STRCMP($ch4_0Pin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
#if (STRCMP($ch4sel$, CAPTURE_ENABLE) == 1)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
#else
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
#endif
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOB, &GPIO_InitStructure);
#endif
#endif
#if (STRCMP($tim4PinRemap$, GPIO_Remap_TIM4) == 1)
//
// Configure TIM4 pins: ETR, CH1, CH2, CH3, CH4, when Pin Remap is PartialRemap1
//
GPIO_PinRemapConfig(GPIO_Remap_TIM4, ENABLE);
#if (STRCMP($etrPin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOE, &GPIO_InitStructure);
#endif
#if (STRCMP($ch1_1Pin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
#if (STRCMP($ch1sel$, CAPTURE_ENABLE) == 1)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
#else
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
#endif
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);
#endif
#if (STRCMP($ch2_1Pin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
#if (STRCMP($ch2sel$, CAPTURE_ENABLE) == 1)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
#else
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
#endif
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);
#endif
#if (STRCMP($ch3_0Pin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14;
#if (STRCMP($ch3sel$, CAPTURE_ENABLE) == 1)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
#else
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
#endif
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);
#endif
#if (STRCMP($ch4_0Pin$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
#if (STRCMP($ch4sel$, CAPTURE_ENABLE) == 1)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
#else
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
#endif
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);
#endif
#endif
//PUT_A_NEW_LINE_HERE
//
// Initializes the TIM4 Time Base Unit
//
TIM_TimeBaseStructure.TIM_Period = $tim4Period$;
TIM_TimeBaseStructure.TIM_Prescaler = $tim4Psclr$;
TIM_TimeBaseStructure.TIM_ClockDivision = $tim4ClkDiv$;
TIM_TimeBaseStructure.TIM_CounterMode = $tim4CntMode$;
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
#if (STRCMP($tim4ARRMode$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Enables Preload register on ARR
//
TIM_ARRPreloadConfig(TIM3, ENABLE);
#endif
#if (STRCMP($ch1En$, DISABLE) == 0)
#if (STRCMP($ch1sel$, CAPTURE_ENABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Initializes Output Compare Channel1 of the TIM4
//
TIM_OCInitStructure.TIM_OCMode = $oc1Mode$;
TIM_OCInitStructure.TIM_OutputState = $oc1State$;
TIM_OCInitStructure.TIM_Pulse = $oc1Pluse$;
TIM_OCInitStructure.TIM_OCPolarity = $oc1Polar$;
TIM_OC1Init(TIM4, &TIM_OCInitStructure);
#if (STRCMP($oc1Preload$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Enables Preload register on CCR1
//
TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Enable);
#endif
#if (STRCMP($oc1Preload$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Clears or safeguards the OCREF1 signal on an external event
//
TIM_ClearOC1Ref(TIM4, TIM_OCClear_Enable);
#endif
#if ( STRCMP($oc1FastEn$, DISABLE) == 0 && (STRCMP($oc1Mode$, TIM_OCMode_PWM1) == 1 || STRCMP($oc1Mode$, TIM_OCMode_PWM2) == 1) )
//PUT_A_NEW_LINE_HERE
//
// Configures the TIM4 Output Compare Channel1 Fast feature
//
TIM_OC1FastConfig(TIM4, TIM_OCClear_Enable);
#endif
#endif
#if (STRCMP($ch1sel$, COMPARE_ENABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Initializes Input Capture Channel1 of the TIM4
//
TIM_ICInitStructure.TIM_Channel = TIM_Channel_1;
TIM_ICInitStructure.TIM_ICPolarity = $ic1Polar$;
TIM_ICInitStructure.TIM_ICSelection = $ic1Sel$;
TIM_ICInitStructure.TIM_ICPrescaler = $ic1Psc$;
TIM_ICInitStructure.TIM_ICFilter = $ic1Filter$;
TIM_ICInit(TIM4, &TIM_ICInitStructure);
#endif
#endif
#if (STRCMP($ch2En$, DISABLE) == 0)
#if (STRCMP($ch2sel$, CAPTURE_ENABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Initializes Output Compare Channel2 of the TIM4
//
TIM_OCInitStructure.TIM_OCMode = $oc2Mode$;
TIM_OCInitStructure.TIM_OutputState = $oc2State$;
TIM_OCInitStructure.TIM_Pulse = $oc2Pluse$;
TIM_OCInitStructure.TIM_OCPolarity = $oc2Polar$;
TIM_OC2Init(TIM4, &TIM_OCInitStructure);
#if (STRCMP($oc2Preload$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Enables Preload register on CCR2
//
TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable);
#endif
#if (STRCMP($oc2Preload$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Clears or safeguards the OCREF2 signal on an external event
//
TIM_ClearOC2Ref(TIM4, TIM_OCClear_Enable);
#endif
#if ( STRCMP($oc2FastEn$, DISABLE) == 0 && (STRCMP($oc2Mode$, TIM_OCMode_PWM1) == 1 || STRCMP($oc2Mode$, TIM_OCMode_PWM2) == 1) )
//PUT_A_NEW_LINE_HERE
//
// Configures the TIM4 Output Compare Channel2 Fast feature
//
TIM_OC2FastConfig(TIM4, TIM_OCClear_Enable);
#endif
#endif
#if (STRCMP($ch2sel$, COMPARE_ENABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Initializes Input Capture Channel2 of the TIM4
//
TIM_ICInitStructure.TIM_Channel = TIM_Channel_2;
TIM_ICInitStructure.TIM_ICPolarity = $ic2Polar$;
TIM_ICInitStructure.TIM_ICSelection = $ic2Sel$;
TIM_ICInitStructure.TIM_ICPrescaler = $ic2Psc$;
TIM_ICInitStructure.TIM_ICFilter = $ic2Filter$;
TIM_ICInit(TIM4, &TIM_ICInitStructure);
#endif
#endif
#if (STRCMP($ch3En$, DISABLE) == 0)
#if (STRCMP($ch3sel$, CAPTURE_ENABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Initializes Output Compare Channel3 of the TIM4
//
TIM_OCInitStructure.TIM_OCMode = $oc3Mode$;
TIM_OCInitStructure.TIM_OutputState = $oc3State$;
TIM_OCInitStructure.TIM_Pulse = $oc3Pluse$;
TIM_OCInitStructure.TIM_OCPolarity = $oc3Polar$;
TIM_OC3Init(TIM4, &TIM_OCInitStructure);
#if (STRCMP($oc3Preload$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Enables Preload register on CCR3
//
TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable);
#endif
#if (STRCMP($oc3Preload$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Clears or safeguards the OCREF3 signal on an external event
//
TIM_ClearOC3Ref(TIM4, TIM_OCClear_Enable);
#endif
#if ( STRCMP($oc3FastEn$, DISABLE) == 0 && (STRCMP($oc3Mode$, TIM_OCMode_PWM1) == 1 || STRCMP($oc3Mode$, TIM_OCMode_PWM2) == 1) )
//PUT_A_NEW_LINE_HERE
//
// Configures the TIM4 Output Compare Channel3 Fast feature
//
TIM_OC3FastConfig(TIM4, TIM_OCClear_Enable);
#endif
#endif
#if (STRCMP($ch3sel$, COMPARE_ENABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Initializes Input Capture Channel3 of the TIM4
//
TIM_ICInitStructure.TIM_Channel = TIM_Channel_3;
TIM_ICInitStructure.TIM_ICPolarity = $ic3Polar$;
TIM_ICInitStructure.TIM_ICSelection = $ic3Sel$;
TIM_ICInitStructure.TIM_ICPrescaler = $ic3Psc$;
TIM_ICInitStructure.TIM_ICFilter = $ic3Filter$;
TIM_ICInit(TIM4, &TIM_ICInitStructure);
#endif
#endif
#if (STRCMP($ch4En$, DISABLE) == 0)
#if (STRCMP($ch4sel$, CAPTURE_ENABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Initializes Output Compare Channel4 of the TIM4
//
TIM_OCInitStructure.TIM_OCMode = $oc4Mode$;
TIM_OCInitStructure.TIM_OutputState = $oc4State$;
TIM_OCInitStructure.TIM_Pulse = $oc4Pluse$;
TIM_OCInitStructure.TIM_OCPolarity = $oc4Polar$;
TIM_OC4Init(TIM4, &TIM_OCInitStructure);
#if (STRCMP($oc4Preload$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Enables Preload register on CCR4
//
TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable);
#endif
#if (STRCMP($oc4Preload$, DISABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Clears or safeguards the OCREF4 signal on an external event
//
TIM_ClearOC4Ref(TIM4, TIM_OCClear_Enable);
#endif
#if ( STRCMP($oc4FastEn$, DISABLE) == 0 && (STRCMP($oc4Mode$, TIM_OCMode_PWM1) == 1 || STRCMP($oc4Mode$, TIM_OCMode_PWM2) == 1) )
//PUT_A_NEW_LINE_HERE
//
// Configures the TIM4 Output Compare Channel4 Fast feature
//
TIM_OC4FastConfig(TIM4, TIM_OCClear_Enable);
#endif
#endif
#if (STRCMP($ch4sel$, COMPARE_ENABLE) == 0)
//PUT_A_NEW_LINE_HERE
//
// Initializes Input Capture Channel4 of the TIM4
//
TIM_ICInitStructure.TIM_Channel = TIM_Channel_4;
TIM_ICInitStructure.TIM_ICPolarity = $ic4Polar$;
TIM_ICInitStructure.TIM_ICSelection = $ic4Sel$;
TIM_ICInitStructure.TIM_ICPrescaler = $ic4Psc$;
TIM_ICInitStructure.TIM_ICFilter = $ic4Filter$;
TIM_ICInit(TIM4, &TIM_ICInitStructure);
#endif
#endif
//PUT_A_NEW_LINE_HERE
//
// Enables TIM4 peripheral
//
TIM_Cmd(TIM4, ENABLE);
#if (STRCMP($masterEn$, DISABLE) == 0 && STRCMP($masterTRGOSrc$, None) == 0)
//PUT_A_NEW_LINE_HERE
//
// Selects the TIM4 Trigger Output Mode
//
TIM_SelectOutputTrigger(TIM4, $masterTRGOSrc$);
#endif
#if (STRCMP($slaveEn$, DISABLE) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Sets the TIM4 Master/Slave Mode
//
TIM_SelectMasterSlaveMode(TIM4, TIM_MasterSlaveMode_Enable);
#endif
#if (STRCMP($slaveEn$, DISABLE) == 0 && STRCMP($slaveModeSet$, Disable(Internal Clock)) == 0)
//PUT_A_NEW_LINE_HERE
//
// Selects the TIM4 Slave Mode
//
TIM_SelectSlaveMode(TIM4, $slaveModeSet$);
#endif
#if (STRCMP($onePulseEn$, TIM_OPMode_Repetitive) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Selects the TIM4's One Pulse Mode
//
TIM_SelectOnePulseMode(TIM4, TIM_OPMode_Single);
#endif
#if (STRCMP($hallSensorEn$, DISABLE) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Enables the TIM4's Hall sensor interface
//
TIM_SelectHallSensor(TIM4, ENABLE);
#endif
#if (STRCMP($encoderEn$, DISABLE) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Configures the TIM4 Encoder Interface
//
TIM_EncoderInterfaceConfig(TIM4, $extiCh1OutputPin$,
$EncodeIC1Polar$, $EncodeIC2Polar$);
#endif
#if (STRCMP($interClkEn$, ENABLE) == 0 )
#if (STRCMP($interTrigr$, DISABLE) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Configures the TIM4 Internal Trigger as External Clock
//
TIM_ITRxExternalClockConfig(TIM4, $interTrigr$);
#endif
#if (STRCMP($timxTrigr$, DISABLE) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Configures the TIM4 Trigger as External Clock
//
TIM_TIxExternalClockConfig(TIM4, $timxTrigr$, TIM_ICPolarity_Rising, 0x0);
#endif
#if (STRCMP($extTrigr$, DISABLE) == 0 )
#if (STRCMP($extTrigr$, ExternalTriggerMode1) == 1 )
//PUT_A_NEW_LINE_HERE
//
// Configures the External clock Mode1
//
TIM_ETRClockMode1Config(TIM4, TIM_ExtTRGPSC_OFF, TIM_ExtTRGPolarity_Inverted, 0x0);
#endif
#if (STRCMP($extTrigr$, ExternalTriggerMode2) == 1 )
//PUT_A_NEW_LINE_HERE
//
// Configures the External clock Mode2
//
TIM_ETRClockMode2Config(TIM4, TIM_ExtTRGPSC_OFF, TIM_ExtTRGPolarity_Inverted, 0x0);
#endif
#endif
#endif
#if (STRCMP($evtUpdate$, DISABLE) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Enables the TIM4 Update event
//
TIM_UpdateRequestConfig(TIM4, $updateRqstSrc$);
TIM_UpdateDisableConfig(TIM4, DISABLE);
#endif
#if (STRCMP($tim4IntEn$, 0) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Enables TIM4 interrupts
//
TIM_ITConfig(TIM4, $tim4IntEn$, ENABLE);
NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
#endif
#if (STRCMP($tim4dmaEn$, DISABLE) == 0 )
//PUT_A_NEW_LINE_HERE
//
// Enables the TIM4's DMA Requests
//
TIM_DMAConfig(TIM4, $dmaBaseAddr$, $dmaBurstLen$);
#if (STRCMP($tim4dmaRqstSrc$, 0) == 0 )
TIM_DMACmd(TIM4, $tim4dmaRqstSrc$, ENABLE);
#endif
TIM_SelectCCDMA(TIM4, ENABLE);
#endif
}
