void artmagic_from_shiftreg(address_space *space, offs_t address, UINT16 *data)
{
artmagic_state *state = space->machine().driver_data<artmagic_state>();
UINT16 *vram = address_to_vram(state, &address);
if (vram)
memcpy(&vram[address], data, TOBYTE(0x2000));
}
void tms340x0_device::write_pixel_r_t_32(offs_t offset, UINT32 data)
{
/* TODO: plane masking */
UINT32 a = TOBYTE(offset & 0xffffffe0);
data = (this->*m_raster_op)(data, TMS34010_RDMEM_DWORD(a));
if (data)
TMS34010_WRMEM_DWORD(a, data);
}
void wfield_16(offs_t offset,UINT32 data)
{
if (offset & 0x0f)
{
WFIELDMAC(0xffff,1);
}
else
{
TMS34010_WRMEM_WORD(TOBYTE(offset),data);
}
}
void wfield_16(UINT32 bitaddr, UINT32 data)
{
if (bitaddr&0x0f)
{
WFIELDMAC(0xffff,1);
}
else
{
TMS34010_WRMEM_WORD(TOBYTE(bitaddr),data);
}
}
INT32 rfield_z_16(UINT32 bitaddr)
{
if (bitaddr&0x0f)
{
RFIELDMAC_Z(0xffff,1);
}
else
{
return TMS34010_RDMEM_WORD(TOBYTE(bitaddr));
}
}
UINT32 rfield_s_08(offs_t offset)
{
UINT32 ret;
if (offset & 0x07)
{
RFIELDMAC(0xff,9);
}
else
ret = TMS34010_RDMEM(TOBYTE(offset));
return (INT32)(INT8)ret;
}
UINT32 rfield_z_16(offs_t offset)
{
UINT32 ret;
if (offset & 0x0f)
{
RFIELDMAC(0xffff,1);
}
else
ret = TMS34010_RDMEM_WORD(TOBYTE(offset));
return ret;
}
INT32 rfield_s_16(UINT32 bitaddr)
{
if (bitaddr&0x0f)
{
RFIELDMAC_S(0xffff,1);
return (INT32)(INT16)ret;
}
else
{
return (INT32)(INT16)TMS34010_RDMEM_WORD(TOBYTE(bitaddr));
}
}
INT32 rfield_s_08(UINT32 bitaddr)
{
if (bitaddr&0x07)
{
RFIELDMAC_S(0xff,9);
return (INT32)(INT8)ret;
}
else
{
return (INT32)(INT8)TMS34010_RDMEM(TOBYTE(bitaddr));
}
}
UINT32 rfield_s_16(offs_t offset)
{
UINT32 ret;
if (offset & 0x0f)
{
RFIELDMAC(0xffff,1);
}
else
{
ret = TMS34010_RDMEM_WORD(TOBYTE(offset));
}
return (INT32)(INT16)ret;
}
inline INT16 tms340x0_device::PARAM_WORD()
{
UINT32 pc = TOBYTE(m_pc);
m_pc += 2 << 3;
return m_direct->read_word(pc);
}
inline INT32 tms340x0_device::PARAM_LONG()
{
UINT32 pc = TOBYTE(m_pc);
m_pc += 4 << 3;
return (UINT16)m_direct->read_raw_word(pc) | (m_direct->read_raw_word(pc + 2) << 16);
}
void tms340x0_device::write_pixel_r_16(offs_t offset, UINT32 data)
{
/* TODO: plane masking */
UINT32 a = TOBYTE(offset & 0xfffffff0);
TMS34010_WRMEM_WORD(a, (this->*m_raster_op)(data, TMS34010_RDMEM_WORD(a)));
}
void tms340x0_device::write_pixel_t_32(offs_t offset, UINT32 data)
{
/* TODO: plane masking */
if (data)
TMS34010_WRMEM_DWORD(TOBYTE(offset & 0xffffffe0), data);
}
void tms340x0_device::write_pixel_16(offs_t offset, UINT32 data)
{
/* TODO: plane masking */
TMS34010_WRMEM_WORD(TOBYTE(offset & 0xfffffff0), data);
}
UINT32 tms340x0_device::read_pixel_32(offs_t offset)
{
/* TODO: Plane masking */
return TMS34010_RDMEM_DWORD(TOBYTE(offset & 0xffffffe0));
}
void artmagic_to_shiftreg(address_space *space, offs_t address, UINT16 *data)
{
UINT16 *vram = address_to_vram(&address);
if (vram)
memcpy(data, &vram[address], TOBYTE(0x2000));
}
}
}
static struct tms34010_config master_config =
{
0, /* halt on reset */
NULL, /* generate interrupt */
exterm_to_shiftreg_master, /* write to shiftreg function */
exterm_from_shiftreg_master /* read from shiftreg function */
};
static struct MemoryReadAddress master_readmem[] =
{
{ TOBYTE(0x00000000), TOBYTE(0x000fffff), exterm_master_videoram_r },
{ TOBYTE(0x00c800e0), TOBYTE(0x00c800ef), exterm_master_speedup_r },
{ TOBYTE(0x00c00000), TOBYTE(0x00ffffff), MRA_BANK1 },
{ TOBYTE(0x01000000), TOBYTE(0x0100000f), MRA_NOP }, /* Off by one bug in RAM test, prevent log entry */
{ TOBYTE(0x01200000), TOBYTE(0x012fffff), exterm_host_data_r },
{ TOBYTE(0x01400000), TOBYTE(0x0140000f), exterm_input_port_0_1_r },
{ TOBYTE(0x01440000), TOBYTE(0x0144000f), exterm_input_port_2_3_r },
{ TOBYTE(0x01480000), TOBYTE(0x0148000f), input_port_4_r },
{ TOBYTE(0x01800000), TOBYTE(0x01807fff), paletteram_word_r },
{ TOBYTE(0x01808000), TOBYTE(0x0180800f), MRA_NOP }, /* Off by one bug in RAM test, prevent log entry */
{ TOBYTE(0x02800000), TOBYTE(0x02807fff), MRA_BANK2 },
{ TOBYTE(0x03000000), TOBYTE(0x03ffffff), exterm_coderom_r },
{ TOBYTE(0x3f000000), TOBYTE(0x3fffffff), exterm_coderom_r },
{ TOBYTE(0xc0000000), TOBYTE(0xc00001ff), tms34010_io_register_r },
{ TOBYTE(0xff000000), TOBYTE(0xffffffff), MRA_BANK3 },
{ -1 } /* end of table */
/* shortcuts for reading opcodes */
inline UINT32 tms340x0_device::ROPCODE()
{
UINT32 pc = TOBYTE(m_pc);
m_pc += 2 << 3;
return m_direct->read_word(pc);
}
inline INT16 tms340x0_device::PARAM_WORD_NO_INC()
{
return m_direct->read_word(TOBYTE(m_pc));
}
inline INT32 tms340x0_device::PARAM_LONG_NO_INC()
{
UINT32 pc = TOBYTE(m_pc);
return (UINT16)m_direct->read_word(pc) | (m_direct->read_word(pc + 2) << 16);
}
void artmagic_from_shiftreg(offs_t address, UINT16 *data)
{
UINT16 *vram = address_to_vram(&address);
if (vram)
memcpy(&vram[address], data, TOBYTE(0x2000));
}
static void coolpool_from_shiftreg(address_space &space, UINT32 address, UINT16 *shiftreg)
{
coolpool_state *state = space.machine().driver_data<coolpool_state>();
memcpy(&state->m_vram_base[TOWORD(address) & ~TOWORD(0xfff)], shiftreg, TOBYTE(0x1000));
}
