static void __init tx4927_irq_pic_init(void) { unsigned long flags; int i; TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n", TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = 0; irq_desc[i].depth = 2; irq_desc[i].handler = &tx4927_irq_pic_type; } setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); spin_lock_irqsave(&tx4927_pic_lock, flags); TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */ spin_unlock_irqrestore(&tx4927_pic_lock, flags); return; }
static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits) { unsigned long val = 0; val = TX4927_RD(pic_reg); val &= (~clr_bits); val |= (set_bits); TX4927_WR(pic_reg, val); return; }
int tx4927_irq_nested(void) { int sw_irq = 0; u32 level2; TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "-\n"); level2 = TX4927_RD(0xff1ff6a0); TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=level2a=0x%x\n", level2); if ((level2 & 0x10000) == 0) { level2 &= 0x1f; TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=level2b=0x%x\n", level2); sw_irq = TX4927_IRQ_PIC_BEG + level2; TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST3, "=sw_irq=%d\n", sw_irq); if (sw_irq == 27) { TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq-%d\n", sw_irq); #ifdef CONFIG_TOSHIBA_RBTX4927 { sw_irq = toshiba_rbtx4927_irq_nested(sw_irq); } #endif TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST4, "=irq+%d\n", sw_irq); } } TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST2, "=sw_irq=%d\n", sw_irq); TX4927_IRQ_DPRINTK(TX4927_IRQ_NEST1, "+\n"); return (sw_irq); }
void print_addr(char *hdr, char *key, u32 addr) { printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr)); return; }
void print_pic(char *key, u32 reg, char *name) { printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, TX4927_RD(reg)); return; }
void toshiba_rbtx4927_irq_dump_pics(char *s) { u32 level0_m; u32 level0_s; u32 level1_m; u32 level1_s; u32 level2; u32 level2_p; u32 level2_s; u32 level3_m; u32 level3_s; u32 level4_m; u32 level4_s; u32 level5_m; u32 level5_s; if (s == NULL) s = "null"; level0_m = (read_c0_status() & 0x0000ff00) >> 8; level0_s = (read_c0_cause() & 0x0000ff00) >> 8; level1_m = level0_m; level1_s = level0_s & 0x87; level2 = TX4927_RD(0xff1ff6a0); level2_p = (((level2 & 0x10000)) ? 0 : 1); level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; level4_m = inb(0x21); outb(0x0A, 0x20); level4_s = inb(0x20); level5_m = inb(0xa1); outb(0x0A, 0xa0); level5_s = inb(0xa0); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "dump_raw_pic() "); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "cp0:m=0x%02x/s=0x%02x ", level0_m, level0_s); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "cp0:m=0x%02x/s=0x%02x ", level1_m, level1_s); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "pic:e=0x%02x/s=0x%02x ", level2_p, level2_s); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "ioc:m=0x%02x/s=0x%02x ", level3_m, level3_s); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "sbm:m=0x%02x/s=0x%02x ", level4_m, level4_s); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "sbs:m=0x%02x/s=0x%02x ", level5_m, level5_s); TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", s); }