VOID
TimerInit (
VOID
)
{
UINTN Timer = FixedPcdGet32(PcdOmap35xxFreeTimer);
UINT32 TimerBaseAddress = TimerBase(Timer);
// Set source clock for GPT3 & GPT4 to SYS_CLK
MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);
// Set count & reload registers
MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);
MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);
// Disable interrupts
MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);
// Start Timer
MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);
//Disable OMAP Watchdog timer (WDT2)
MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);
DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));
MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);
}
/**
Setup all the hardware needed for the debug agents timer.
This function is used to set up debug enviroment. It may enable interrupts.
**/
VOID
EFIAPI
DebugAgentTimerIntialize (
VOID
)
{
UINT32 TimerBaseAddress;
UINT32 TimerNumber;
TimerNumber = PcdGet32(PcdOmap35xxDebugAgentTimer);
gVector = InterruptVectorForTimer (TimerNumber);
// Set up the timer registers
TimerBaseAddress = TimerBase (TimerNumber);
gTISR = TimerBaseAddress + GPTIMER_TISR;
gTCLR = TimerBaseAddress + GPTIMER_TCLR;
gTLDR = TimerBaseAddress + GPTIMER_TLDR;
gTCRR = TimerBaseAddress + GPTIMER_TCRR;
gTIER = TimerBaseAddress + GPTIMER_TIER;
if ((TimerNumber < 2) || (TimerNumber > 9)) {
// This code assumes one the General Purpose timers is used
// GPT2 - GPT9
CpuDeadLoop ();
}
// Set source clock for GPT2 - GPT9 to SYS_CLK
MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2));
}
UINTN
EFIAPI
NanoSecondDelay (
IN UINTN NanoSeconds
)
{
UINT32 Delay;
UINT32 StartTime;
UINT32 CurrentTime;
UINT32 ElapsedTime;
UINT32 TimerCountRegister;
Delay = (NanoSeconds / PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)) + 1;
TimerCountRegister = TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR;
StartTime = MmioRead32 (TimerCountRegister);
do
{
CurrentTime = MmioRead32 (TimerCountRegister);
ElapsedTime = CurrentTime - StartTime;
} while (ElapsedTime < Delay);
NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds);
return NanoSeconds;
}
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR);
}
/**
Initialize the state information for the Timer Architectural Protocol and
the Timer Debug support protocol that allows the debugger to break into a
running program.
@param ImageHandle of the loaded driver
@param SystemTable Pointer to the System Table
@retval EFI_SUCCESS Protocol registered
@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
@retval EFI_DEVICE_ERROR Hardware problems
**/
EFI_STATUS
EFIAPI
TimerInitialize (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
UINT32 TimerBaseAddress;
// Find the interrupt controller protocol. ASSERT if not found.
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
ASSERT_EFI_ERROR (Status);
// Set up the timer registers
TimerBaseAddress = TimerBase (FixedPcdGet32(PcdOmap35xxArchTimer));
TISR = TimerBaseAddress + GPTIMER_TISR;
TCLR = TimerBaseAddress + GPTIMER_TCLR;
TLDR = TimerBaseAddress + GPTIMER_TLDR;
TCRR = TimerBaseAddress + GPTIMER_TCRR;
TIER = TimerBaseAddress + GPTIMER_TIER;
// Disable the timer
Status = TimerDriverSetTimerPeriod (&gTimer, 0);
ASSERT_EFI_ERROR (Status);
// Install interrupt handler
gVector = InterruptVectorForTimer (FixedPcdGet32(PcdOmap35xxArchTimer));
Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler);
ASSERT_EFI_ERROR (Status);
// Turn on the functional clock for Timer
MmioOr32 (CM_FCLKEN_PER, CM_FCLKEN_PER_EN_GPT3_ENABLE);
// Set up default timer
Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
ASSERT_EFI_ERROR (Status);
// Install the Timer Architectural Protocol onto a new handle
Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
&gEfiTimerArchProtocolGuid, &gTimer,
NULL
);
ASSERT_EFI_ERROR(Status);
return Status;
}
}
UINT64
EFIAPI
GetPerformanceCounter (
VOID
)
{
return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TCRR);
}
UINT64
EFIAPI
GetPerformanceCounterProperties (
OUT UINT64 *StartValue, OPTIONAL
OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
// Timer starts with the reload value
*StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap35xxFreeTimer)) + GPTIMER_TLDR);
}
if (EndValue != NULL) {
// Timer counts up to 0xFFFFFFFF
*EndValue = 0xFFFFFFFF;
}
return PcdGet64(PcdEmbeddedPerformanceCounterFrequencyInHz);
}
