void vfnUART_Config(void) { SIM_SOPT2 |= SIM_SOPT2_UART0SRC(1); SIM_SCGC4 |= SIM_SCGC4_UART0_MASK; SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; UART0_BDL = UART0_BDL_SBR(137); UART0_C2 = UART0_C2_TE_MASK; PORTA_PCR1= PORT_PCR_MUX(2) | PORT_PCR_PE_MASK; PORTA_PCR2= PORT_PCR_MUX(2) | PORT_PCR_PE_MASK; }
void uart_init(void) { /* Supply the clock for UART0 and PORTA */ SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Set PORTA1 as Rx and PORTA2 as Tx */ PORTA->PCR[1] &= ~PORT_PCR_MUX_MASK; // Make sure that MUX is clear PORTA->PCR[1] |= PORT_PCR_MUX(2); PORTA->PCR[2] &= ~PORT_PCR_MUX_MASK; // Make sure that MUX is clear PORTA->PCR[2] |= PORT_PCR_MUX(2); /* Choose external 8MHz crystal as a reference clock for UART0 */ /* Asynch Module Clock = 8 MHz */ SIM->SOPT2 |= SIM_SOPT2_UART0SRC(2); /* Disable the reciever and transmitter of UART0 */ UART0->C2 &= ~(UART0_C2_TE_MASK | UART0_C2_RE_MASK); // turn off the Tx and Rx /* Set the oversampling ratio to 4 */ UART0->C4 = UART0_C4_OSR(3); /* Set SBr to 139 in order to achieve Baud Rate euqal to 14400 */ UART0->BDH |= UART0_BDH_SBR(0); UART0->BDL &= ~UART0_BDL_SBR_MASK; // clear BDL first UART0->BDL |= UART0_BDL_SBR(139); /* Set 1 Stop Bit */ UART0->BDH &= ~UART0_BDH_SBNS_MASK; /* Choose 8-bits long data */ UART0->C1 &= ~UART0_C1_M_MASK; /* Disable hardware parity check */ UART0->C1 &= ~UART0_C1_PE_MASK; /* Initialize the queues for the interrupts-driven serial communication */ q_init(&TxQ); q_init(&RxQ); /* Configure the interrupts from the UART0 */ NVIC_ClearPendingIRQ(UART0_IRQn); NVIC_EnableIRQ(UART0_IRQn); /* Enable the interrupt when receiver buffer gets full */ UART0->C2 |= UART0_C2_RIE_MASK; /* Turn on the receiver and transmitter */ UART0->C2 |= UART0_C2_TE_MASK | UART0_C2_RE_MASK; // turn on the Tx and Rx }