/******************************************************************************* * Function Name: UART_1_UartStop ******************************************************************************** * * Summary: * Changes the HSIOM settings for the UART output pins (TX and/or RTS) to keep * them inactive after the block is disabled. The output pins are controlled by * the GPIO data register. Also, the function disables the skip start feature to * not cause it to trigger after the component is enabled. * * Parameters: * None * * Return: * None * *******************************************************************************/ void UART_1_UartStop(void) { #if(UART_1_SCB_MODE_UNCONFIG_CONST_CFG) #if (UART_1_TX_SDA_MISO_PIN) if (UART_1_CHECK_TX_SDA_MISO_PIN_USED) { /* Set GPIO to drive output pin */ UART_1_SET_HSIOM_SEL(UART_1_TX_SDA_MISO_HSIOM_REG, UART_1_TX_SDA_MISO_HSIOM_MASK, UART_1_TX_SDA_MISO_HSIOM_POS, UART_1_HSIOM_GPIO_SEL); } #endif /* (UART_1_TX_SDA_MISO_PIN_PIN) */ #if (UART_1_SS0_PIN) if (UART_1_CHECK_SS0_PIN_USED) { /* Set output pin state after block is disabled */ UART_1_spi_ss0_Write(UART_1_GET_UART_RTS_INACTIVE); /* Set GPIO to drive output pin */ UART_1_SET_HSIOM_SEL(UART_1_SS0_HSIOM_REG, UART_1_SS0_HSIOM_MASK, UART_1_SS0_HSIOM_POS, UART_1_HSIOM_GPIO_SEL); } #endif /* (UART_1_SS0_PIN) */ #else #if (UART_1_UART_TX_PIN) /* Set GPIO to drive output pin */ UART_1_SET_HSIOM_SEL(UART_1_TX_HSIOM_REG, UART_1_TX_HSIOM_MASK, UART_1_TX_HSIOM_POS, UART_1_HSIOM_GPIO_SEL); #endif /* (UART_1_UART_TX_PIN) */ #if (UART_1_UART_RTS_PIN) /* Set output pin state after block is disabled */ UART_1_rts_Write(UART_1_GET_UART_RTS_INACTIVE); /* Set GPIO to drive output pin */ UART_1_SET_HSIOM_SEL(UART_1_RTS_HSIOM_REG, UART_1_RTS_HSIOM_MASK, UART_1_RTS_HSIOM_POS, UART_1_HSIOM_GPIO_SEL); #endif /* (UART_1_UART_RTS_PIN) */ #endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ #if (UART_1_UART_WAKE_ENABLE_CONST) /* Disable skip start feature used for wakeup */ UART_1_UART_RX_CTRL_REG &= (uint32) ~UART_1_UART_RX_CTRL_SKIP_START; #endif /* (UART_1_UART_WAKE_ENABLE_CONST) */ }
/******************************************************************************* * Function Name: UART_1_UartPostEnable ******************************************************************************** * * Summary: * Restores HSIOM settings for the UART output pins (TX and/or RTS) to be * controlled by the SCB UART. * * Parameters: * None * * Return: * None * *******************************************************************************/ void UART_1_UartPostEnable(void) { #if (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) #if (UART_1_TX_SDA_MISO_PIN) if (UART_1_CHECK_TX_SDA_MISO_PIN_USED) { /* Set SCB UART to drive the output pin */ UART_1_SET_HSIOM_SEL(UART_1_TX_SDA_MISO_HSIOM_REG, UART_1_TX_SDA_MISO_HSIOM_MASK, UART_1_TX_SDA_MISO_HSIOM_POS, UART_1_HSIOM_UART_SEL); } #endif /* (UART_1_TX_SDA_MISO_PIN_PIN) */ #if (UART_1_SS0_PIN) if (UART_1_CHECK_SS0_PIN_USED) { /* Set SCB UART to drive the output pin */ UART_1_SET_HSIOM_SEL(UART_1_SS0_HSIOM_REG, UART_1_SS0_HSIOM_MASK, UART_1_SS0_HSIOM_POS, UART_1_HSIOM_UART_SEL); } #endif /* (UART_1_SS0_PIN) */ #else #if (UART_1_UART_TX_PIN) /* Set SCB UART to drive the output pin */ UART_1_SET_HSIOM_SEL(UART_1_TX_HSIOM_REG, UART_1_TX_HSIOM_MASK, UART_1_TX_HSIOM_POS, UART_1_HSIOM_UART_SEL); #endif /* (UART_1_UART_TX_PIN) */ #if (UART_1_UART_RTS_PIN) /* Set SCB UART to drive the output pin */ UART_1_SET_HSIOM_SEL(UART_1_RTS_HSIOM_REG, UART_1_RTS_HSIOM_MASK, UART_1_RTS_HSIOM_POS, UART_1_HSIOM_UART_SEL); #endif /* (UART_1_UART_RTS_PIN) */ #endif /* (UART_1_SCB_MODE_UNCONFIG_CONST_CFG) */ }
/******************************************************************************* * Function Name: UART_1_SetPins ******************************************************************************** * * Summary: * Sets the pins settings accordingly to the selected operation mode. * Only available in the Unconfigured operation mode. The mode specific * initialization function calls it. * Pins configuration is set by PSoC Creator when a specific mode of operation * is selected in design time. * * Parameters: * mode: Mode of SCB operation. * subMode: Sub-mode of SCB operation. It is only required for SPI and UART * modes. * uartEnableMask: enables TX or RX direction and RTS and CTS signals. * * Return: * None * *******************************************************************************/ void UART_1_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask) { uint32 hsiomSel [UART_1_SCB_PINS_NUMBER]; uint32 pinsDm [UART_1_SCB_PINS_NUMBER]; #if (!UART_1_CY_SCBIP_V1) uint32 pinsInBuf = 0u; #endif /* (!UART_1_CY_SCBIP_V1) */ uint32 i; /* Set default HSIOM to GPIO and Drive Mode to Analog Hi-Z */ for(i = 0u; i < UART_1_SCB_PINS_NUMBER; i++) { hsiomSel[i] = UART_1_HSIOM_DEF_SEL; pinsDm[i] = UART_1_PIN_DM_ALG_HIZ; } if((UART_1_SCB_MODE_I2C == mode) || (UART_1_SCB_MODE_EZI2C == mode)) { hsiomSel[UART_1_MOSI_SCL_RX_PIN_INDEX] = UART_1_HSIOM_I2C_SEL; hsiomSel[UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_HSIOM_I2C_SEL; pinsDm[UART_1_MOSI_SCL_RX_PIN_INDEX] = UART_1_PIN_DM_OD_LO; pinsDm[UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_PIN_DM_OD_LO; } #if (!UART_1_CY_SCBIP_V1) else if(UART_1_SCB_MODE_SPI == mode) { hsiomSel[UART_1_MOSI_SCL_RX_PIN_INDEX] = UART_1_HSIOM_SPI_SEL; hsiomSel[UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_HSIOM_SPI_SEL; hsiomSel[UART_1_SCLK_PIN_INDEX] = UART_1_HSIOM_SPI_SEL; if(UART_1_SPI_SLAVE == subMode) { /* Slave */ pinsDm[UART_1_MOSI_SCL_RX_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; pinsDm[UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_PIN_DM_STRONG; pinsDm[UART_1_SCLK_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; #if(UART_1_SS0_PIN) /* Only SS0 is valid choice for Slave */ hsiomSel[UART_1_SS0_PIN_INDEX] = UART_1_HSIOM_SPI_SEL; pinsDm [UART_1_SS0_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; #endif /* (UART_1_SS1_PIN) */ #if(UART_1_MISO_SDA_TX_PIN) /* Disable input buffer */ pinsInBuf |= UART_1_MISO_SDA_TX_PIN_MASK; #endif /* (UART_1_MISO_SDA_TX_PIN_PIN) */ } else /* (Master) */ { pinsDm[UART_1_MOSI_SCL_RX_PIN_INDEX] = UART_1_PIN_DM_STRONG; pinsDm[UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; pinsDm[UART_1_SCLK_PIN_INDEX] = UART_1_PIN_DM_STRONG; #if(UART_1_SS0_PIN) hsiomSel [UART_1_SS0_PIN_INDEX] = UART_1_HSIOM_SPI_SEL; pinsDm [UART_1_SS0_PIN_INDEX] = UART_1_PIN_DM_STRONG; pinsInBuf |= UART_1_SS0_PIN_MASK; #endif /* (UART_1_SS0_PIN) */ #if(UART_1_SS1_PIN) hsiomSel [UART_1_SS1_PIN_INDEX] = UART_1_HSIOM_SPI_SEL; pinsDm [UART_1_SS1_PIN_INDEX] = UART_1_PIN_DM_STRONG; pinsInBuf |= UART_1_SS1_PIN_MASK; #endif /* (UART_1_SS1_PIN) */ #if(UART_1_SS2_PIN) hsiomSel [UART_1_SS2_PIN_INDEX] = UART_1_HSIOM_SPI_SEL; pinsDm [UART_1_SS2_PIN_INDEX] = UART_1_PIN_DM_STRONG; pinsInBuf |= UART_1_SS2_PIN_MASK; #endif /* (UART_1_SS2_PIN) */ #if(UART_1_SS3_PIN) hsiomSel [UART_1_SS3_PIN_INDEX] = UART_1_HSIOM_SPI_SEL; pinsDm [UART_1_SS3_PIN_INDEX] = UART_1_PIN_DM_STRONG; pinsInBuf |= UART_1_SS3_PIN_MASK; #endif /* (UART_1_SS2_PIN) */ /* Disable input buffers */ #if(UART_1_MOSI_SCL_RX_PIN) pinsInBuf |= UART_1_MOSI_SCL_RX_PIN_MASK; #endif /* (UART_1_MOSI_SCL_RX_PIN) */ #if(UART_1_MOSI_SCL_RX_WAKE_PIN) pinsInBuf |= UART_1_MOSI_SCL_RX_WAKE_PIN_MASK; #endif /* (UART_1_MOSI_SCL_RX_WAKE_PIN) */ #if(UART_1_SCLK_PIN) pinsInBuf |= UART_1_SCLK_PIN_MASK; #endif /* (UART_1_SCLK_PIN) */ } } else /* UART */ { if(UART_1_UART_MODE_SMARTCARD == subMode) { /* SmartCard */ hsiomSel[UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_HSIOM_UART_SEL; pinsDm [UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_PIN_DM_OD_LO; } else /* Standard or IrDA */ { if(0u != (UART_1_UART_RX_PIN_ENABLE & uartEnableMask)) { hsiomSel[UART_1_MOSI_SCL_RX_PIN_INDEX] = UART_1_HSIOM_UART_SEL; pinsDm [UART_1_MOSI_SCL_RX_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; } if(0u != (UART_1_UART_TX_PIN_ENABLE & uartEnableMask)) { hsiomSel[UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_HSIOM_UART_SEL; pinsDm [UART_1_MISO_SDA_TX_PIN_INDEX] = UART_1_PIN_DM_STRONG; #if(UART_1_MISO_SDA_TX_PIN) pinsInBuf |= UART_1_MISO_SDA_TX_PIN_MASK; #endif /* (UART_1_MISO_SDA_TX_PIN_PIN) */ } #if !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) if(UART_1_UART_MODE_STD == subMode) { if(0u != (UART_1_UART_CTS_PIN_ENABLE & uartEnableMask)) { /* CTS input is multiplexed with SCLK */ hsiomSel[UART_1_SCLK_PIN_INDEX] = UART_1_HSIOM_UART_SEL; pinsDm [UART_1_SCLK_PIN_INDEX] = UART_1_PIN_DM_DIG_HIZ; } if(0u != (UART_1_UART_RTS_PIN_ENABLE & uartEnableMask)) { /* RTS output is multiplexed with SS0 */ hsiomSel[UART_1_SS0_PIN_INDEX] = UART_1_HSIOM_UART_SEL; pinsDm [UART_1_SS0_PIN_INDEX] = UART_1_PIN_DM_STRONG; #if(UART_1_SS0_PIN) /* Disable input buffer */ pinsInBuf |= UART_1_SS0_PIN_MASK; #endif /* (UART_1_SS0_PIN) */ } } #endif /* !(UART_1_CY_SCBIP_V0 || UART_1_CY_SCBIP_V1) */ } } #endif /* (!UART_1_CY_SCBIP_V1) */ /* Configure pins: set HSIOM, DM and InputBufEnable */ /* Note: the DR register settings do not effect the pin output if HSIOM is other than GPIO */ #if(UART_1_MOSI_SCL_RX_PIN) UART_1_SET_HSIOM_SEL(UART_1_MOSI_SCL_RX_HSIOM_REG, UART_1_MOSI_SCL_RX_HSIOM_MASK, UART_1_MOSI_SCL_RX_HSIOM_POS, hsiomSel[UART_1_MOSI_SCL_RX_PIN_INDEX]); UART_1_spi_mosi_i2c_scl_uart_rx_SetDriveMode((uint8) pinsDm[UART_1_MOSI_SCL_RX_PIN_INDEX]); #if (!UART_1_CY_SCBIP_V1) UART_1_SET_INP_DIS(UART_1_spi_mosi_i2c_scl_uart_rx_INP_DIS, UART_1_spi_mosi_i2c_scl_uart_rx_MASK, (0u != (pinsInBuf & UART_1_MOSI_SCL_RX_PIN_MASK))); #endif /* (!UART_1_CY_SCBIP_V1) */ #endif /* (UART_1_MOSI_SCL_RX_PIN) */ #if(UART_1_MOSI_SCL_RX_WAKE_PIN) UART_1_SET_HSIOM_SEL(UART_1_MOSI_SCL_RX_WAKE_HSIOM_REG, UART_1_MOSI_SCL_RX_WAKE_HSIOM_MASK, UART_1_MOSI_SCL_RX_WAKE_HSIOM_POS, hsiomSel[UART_1_MOSI_SCL_RX_WAKE_PIN_INDEX]); UART_1_spi_mosi_i2c_scl_uart_rx_wake_SetDriveMode((uint8) pinsDm[UART_1_MOSI_SCL_RX_WAKE_PIN_INDEX]); UART_1_SET_INP_DIS(UART_1_spi_mosi_i2c_scl_uart_rx_wake_INP_DIS, UART_1_spi_mosi_i2c_scl_uart_rx_wake_MASK, (0u != (pinsInBuf & UART_1_MOSI_SCL_RX_WAKE_PIN_MASK))); /* Set interrupt on falling edge */ UART_1_SET_INCFG_TYPE(UART_1_MOSI_SCL_RX_WAKE_INTCFG_REG, UART_1_MOSI_SCL_RX_WAKE_INTCFG_TYPE_MASK, UART_1_MOSI_SCL_RX_WAKE_INTCFG_TYPE_POS, UART_1_INTCFG_TYPE_FALLING_EDGE); #endif /* (UART_1_MOSI_SCL_RX_WAKE_PIN) */ #if(UART_1_MISO_SDA_TX_PIN) UART_1_SET_HSIOM_SEL(UART_1_MISO_SDA_TX_HSIOM_REG, UART_1_MISO_SDA_TX_HSIOM_MASK, UART_1_MISO_SDA_TX_HSIOM_POS, hsiomSel[UART_1_MISO_SDA_TX_PIN_INDEX]); UART_1_spi_miso_i2c_sda_uart_tx_SetDriveMode((uint8) pinsDm[UART_1_MISO_SDA_TX_PIN_INDEX]); #if (!UART_1_CY_SCBIP_V1) UART_1_SET_INP_DIS(UART_1_spi_miso_i2c_sda_uart_tx_INP_DIS, UART_1_spi_miso_i2c_sda_uart_tx_MASK, (0u != (pinsInBuf & UART_1_MISO_SDA_TX_PIN_MASK))); #endif /* (!UART_1_CY_SCBIP_V1) */ #endif /* (UART_1_MOSI_SCL_RX_PIN) */ #if(UART_1_SCLK_PIN) UART_1_SET_HSIOM_SEL(UART_1_SCLK_HSIOM_REG, UART_1_SCLK_HSIOM_MASK, UART_1_SCLK_HSIOM_POS, hsiomSel[UART_1_SCLK_PIN_INDEX]); UART_1_spi_sclk_SetDriveMode((uint8) pinsDm[UART_1_SCLK_PIN_INDEX]); UART_1_SET_INP_DIS(UART_1_spi_sclk_INP_DIS, UART_1_spi_sclk_MASK, (0u != (pinsInBuf & UART_1_SCLK_PIN_MASK))); #endif /* (UART_1_SCLK_PIN) */ #if(UART_1_SS0_PIN) UART_1_SET_HSIOM_SEL(UART_1_SS0_HSIOM_REG, UART_1_SS0_HSIOM_MASK, UART_1_SS0_HSIOM_POS, hsiomSel[UART_1_SS0_PIN_INDEX]); UART_1_spi_ss0_SetDriveMode((uint8) pinsDm[UART_1_SS0_PIN_INDEX]); UART_1_SET_INP_DIS(UART_1_spi_ss0_INP_DIS, UART_1_spi_ss0_MASK, (0u != (pinsInBuf & UART_1_SS0_PIN_MASK))); #endif /* (UART_1_SS1_PIN) */ #if(UART_1_SS1_PIN) UART_1_SET_HSIOM_SEL(UART_1_SS1_HSIOM_REG, UART_1_SS1_HSIOM_MASK, UART_1_SS1_HSIOM_POS, hsiomSel[UART_1_SS1_PIN_INDEX]); UART_1_spi_ss1_SetDriveMode((uint8) pinsDm[UART_1_SS1_PIN_INDEX]); UART_1_SET_INP_DIS(UART_1_spi_ss1_INP_DIS, UART_1_spi_ss1_MASK, (0u != (pinsInBuf & UART_1_SS1_PIN_MASK))); #endif /* (UART_1_SS1_PIN) */ #if(UART_1_SS2_PIN) UART_1_SET_HSIOM_SEL(UART_1_SS2_HSIOM_REG, UART_1_SS2_HSIOM_MASK, UART_1_SS2_HSIOM_POS, hsiomSel[UART_1_SS2_PIN_INDEX]); UART_1_spi_ss2_SetDriveMode((uint8) pinsDm[UART_1_SS2_PIN_INDEX]); UART_1_SET_INP_DIS(UART_1_spi_ss2_INP_DIS, UART_1_spi_ss2_MASK, (0u != (pinsInBuf & UART_1_SS2_PIN_MASK))); #endif /* (UART_1_SS2_PIN) */ #if(UART_1_SS3_PIN) UART_1_SET_HSIOM_SEL(UART_1_SS3_HSIOM_REG, UART_1_SS3_HSIOM_MASK, UART_1_SS3_HSIOM_POS, hsiomSel[UART_1_SS3_PIN_INDEX]); UART_1_spi_ss3_SetDriveMode((uint8) pinsDm[UART_1_SS3_PIN_INDEX]); UART_1_SET_INP_DIS(UART_1_spi_ss3_INP_DIS, UART_1_spi_ss3_MASK, (0u != (pinsInBuf & UART_1_SS3_PIN_MASK))); #endif /* (UART_1_SS3_PIN) */ }