// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
mpc8xxx_scc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
mpc8xxx_sxx_serial_info *scc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv;
unsigned int baud_divisor = select_baud[new_config->baud];
volatile struct scc_regs_8260 *regs = (volatile struct scc_regs_8260*)scc_chan->ctl;
if (baud_divisor == 0) return false;
// Set baud rate generator
*scc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
// Disable channel during setup
HAL_IO_BARRIER(); // Inforce I/O ordering
regs->gsmr_l = 0;
regs->psmr = MPC8XXX_SCC_PSMR_ASYNC |
scc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
scc_select_stop_bits[new_config->stop] |
scc_select_parity[new_config->parity];
// Enable channel with new configuration
regs->gsmr_h = 0x20; // 8bit FIFO
regs->gsmr_l = 0x00028004; // 16x TxCLK, 16x RxCLK, UART
/*
* Init Rx & Tx params for SCCX
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
IMM->cpm_cpcr = CPCR_INIT_TX_RX_PARAMS | scc_chan->channel | CPCR_FLG;
HAL_IO_BARRIER(); // Inforce I/O ordering
regs->gsmr_l |= GSMR_L1_ENT | GSMR_L1_ENR; // Enable Rx, Tx
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
mpc8xxx_smc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
mpc8xxx_sxx_serial_info *smc_chan = (mpc8xxx_sxx_serial_info *)chan->dev_priv;
unsigned int baud_divisor = select_baud[new_config->baud];
cyg_uint32 _lcr;
volatile struct smc_regs_8260 *ctl = (volatile struct smc_regs_8260*)smc_chan->ctl;
if (baud_divisor == 0) return false;
// Disable channel during setup
ctl->smc_smcmr = MPC8XXX_SMCMR_UART; // Disabled, UART mode
HAL_IO_BARRIER(); // Inforce I/O ordering
// Disable port interrupts while changing hardware
_lcr = smc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
smc_select_stop_bits[new_config->stop] |
smc_select_parity[new_config->parity];
// Stop transmitter while changing baud rate
IMM->cpm_cpcr = smc_chan->channel | CPCR_STOP_TX | CPCR_FLG;
HAL_IO_BARRIER(); // Inforce I/O ordering
// Set baud rate generator
*smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
// Enable channel with new configuration
ctl->smc_smcmr = MPC8XXX_SMCMR_UART|MPC8XXX_SMCMR_TEN|MPC8XXX_SMCMR_REN|_lcr;
HAL_IO_BARRIER(); // Inforce I/O ordering
IMM->cpm_cpcr = smc_chan->channel | CPCR_INIT_TX_RX_PARAMS | CPCR_FLG;
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
static void
cyg_hal_plf_serial_init_channel(channel_data_t* __ch_data)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
// Enable port
chan->base->ctrl |= SYSCON1_UART1EN;
// Configure
chan->base->blcr = UART_BITRATE(chan->baud_rate) |
UBLCR_FIFOEN | UBLCR_WRDLEN8;
}
// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
quicc_scc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
quicc_sxx_serial_info *scc_chan = (quicc_sxx_serial_info *)chan->dev_priv;
unsigned int baud_divisor = select_baud[new_config->baud];
EPPC *eppc = eppc_base();
volatile struct scc_regs *regs = (volatile struct scc_regs *)scc_chan->ctl;
if (baud_divisor == 0) return false;
// Set baud rate generator
*scc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
// Disable channel during setup
HAL_IO_BARRIER(); // Inforce I/O ordering
regs->scc_gsmr_l = 0;
regs->scc_psmr = QUICC_SCC_PSMR_ASYNC |
scc_select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
scc_select_stop_bits[new_config->stop] |
scc_select_parity[new_config->parity];
// Enable channel with new configuration
regs->scc_gsmr_h = 0x20; // 8bit FIFO
regs->scc_gsmr_l = 0x00028004; // 16x TxCLK, 16x RxCLK, UART
/*
* Init Rx & Tx params for SCCX
*/
HAL_IO_BARRIER(); // Inforce I/O ordering
eppc->cp_cr = QUICC_CPM_CR_INIT_TXRX | scc_chan->channel | QUICC_CPM_CR_BUSY;
while (eppc->cp_cr & QUICC_CPM_CR_BUSY )
continue;
HAL_IO_BARRIER(); // Inforce I/O ordering
regs->scc_gsmr_l |= (QUICC_SCC_GSMR_L_Tx | QUICC_SCC_GSMR_L_Rx); // Enable Rx, Tx
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
quicc_smc_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
quicc_sxx_serial_info *smc_chan = (quicc_sxx_serial_info *)chan->dev_priv;
unsigned int baud_divisor = select_baud[new_config->baud];
cyg_uint32 _lcr;
EPPC *eppc = eppc_base();
volatile struct smc_regs *ctl = (volatile struct smc_regs *)smc_chan->ctl;
if (baud_divisor == 0) return false;
// Stop transmitter while changing baud rate
eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_StopTx;
while (eppc->cp_cr & QUICC_SMC_CMD_Go )
continue;
HAL_IO_BARRIER(); // Inforce I/O ordering
// Disable channel during setup
ctl->smc_smcmr = QUICC_SMCMR_UART; // Disabled, UART mode
HAL_IO_BARRIER(); // Inforce I/O ordering
// Disable port interrupts while changing hardware
_lcr = QUICC_SMCMR_CLEN(new_config->word_length + ((new_config->parity == CYGNUM_SERIAL_PARITY_NONE)? 0: 1) + ((new_config->stop == CYGNUM_SERIAL_STOP_2)? 2: 1)) |
smc_select_stop_bits[new_config->stop] |
smc_select_parity[new_config->parity];
HAL_IO_BARRIER(); // Inforce I/O ordering
// Set baud rate generator
*smc_chan->brg = 0x10000 | (UART_BITRATE(baud_divisor)<<1);
// Enable channel with new configuration
ctl->smc_smcmr = QUICC_SMCMR_UART|QUICC_SMCMR_TEN|QUICC_SMCMR_REN|_lcr;
HAL_IO_BARRIER(); // Inforce I/O ordering
eppc->cp_cr = smc_chan->channel | QUICC_SMC_CMD_Go | QUICC_SMC_CMD_RestartTx;
while (eppc->cp_cr & QUICC_SMC_CMD_Go )
continue;
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
// Internal function to actually configure the hardware to desired baud rate, etc.
static bool
edb7xxx_serial_config_port(serial_channel *chan, cyg_serial_info_t *new_config, bool init)
{
edb7xxx_serial_info *edb7xxx_chan = (edb7xxx_serial_info *)chan->dev_priv;
volatile cyg_uint32 *syscon = (volatile cyg_uint32 *)edb7xxx_chan->syscon;
volatile cyg_uint32 *blcfg = (volatile cyg_uint32 *)edb7xxx_chan->control;
unsigned int baud_divisor = select_baud[new_config->baud];
cyg_uint32 _lcr;
if (baud_divisor == 0) return false;
// Disable port interrupts while changing hardware
_lcr = select_word_length[new_config->word_length - CYGNUM_SERIAL_WORD_LENGTH_5] |
select_stop_bits[new_config->stop] |
select_parity[new_config->parity] |
UBLCR_FIFOEN | UART_BITRATE(baud_divisor);
#ifdef CYGDBG_IO_INIT
diag_printf("Set CTL: %x = %x\n", blcfg, _lcr);
#endif
*blcfg = _lcr;
*syscon |= SYSCON1_UART1EN;
if (new_config != &chan->config) {
chan->config = *new_config;
}
return true;
}
