/** * @brief Open serial interface with specified baudrate * @param baudrate is the desired baudrate * * @return * SERIAL_FAIL -> interface is open, nothing to do\n * SERIAL_SUCCESS -> interface was opened and initialized */ static SerialResult_t Open(uint32_t baudrate) { if (IsOpenFlag) { return SERIAL_FAIL; } FIFO_Init_uint8_t(fifoContext, USART_MAX_BUFFER, buffer); RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN; GPIOD->MODER &= ~GPIO_MODER_MODER8 | GPIO_MODER_MODER9; GPIOD->MODER |= GPIO_MODER_MODER8_1 | GPIO_MODER_MODER9_1; GPIOD->AFR[1] &= ~(0x0F | (0x0F << 4)); GPIOD->AFR[1] |= (0x07 | (0x07 << 4)); RCC->APB1ENR |= RCC_APB1ENR_USART3EN; USART3->CR1 = 0; USART3->CR1 &= ~USART_CR1_M; // 8 bit data USART3->CR2 &= ~USART_CR2_STOP; // 1 stop bit #ifdef USART_OVER_SAMPLE_16 USART3->CR1 &= ~USART_CR1_OVER8; USART3->BRR = UART_BRR_SAMPLING16(SystemCoreClock, baudrate); #else USART3->CR1 |= USART_CR1_OVER8; USART3->BRR = UART_BRR_SAMPLING8(SystemCoreClock, baudrate); #endif USART3->CR1 |= USART_CR1_UE | USART_CR1_TE | USART_CR1_RE; EnableISR(); IsOpenFlag = TRUE; return SERIAL_SUCCESS; }
void USART_Configure(void) { RCC->APB2ENR |= RCC_APB2ENR_USART1EN; USART1->BRR = UART_BRR_SAMPLING16(APBCLK, BAUDRATE); USART1->CR3 |= USART_CR3_HDSEL; USART1->CR1 |= USART_CR1_TE; USART1->CR1 |= USART_CR1_UE; }
/** @brief: set registers acc to info in huart * @details: used in HAL_UART3Debug_Init, private ****************************************************************/ static void MyUARTSetConfig(UART_HandleTypeDef * huart) { uint32_t tmpreg = 0x00; /* Check the parameters */ assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); /*------- UART-associated USART registers setting : CR2 Configuration ------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); /*------- UART-associated USART registers setting : CR1 Configuration ------*/ /* Configure the UART Word Length, Parity and mode: Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value */ tmpreg = (uint32_t) huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode; MODIFY_REG(huart->Instance->CR1, (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), tmpreg); /*------- UART-associated USART registers setting : CR3 Configuration ------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); /*------- UART-associated USART registers setting : BRR Configuration ------*/ if ((huart->Instance == USART1)) { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate); } else { huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate); } }
int hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits, enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl) { struct hal_uart *u; const struct stm32f4_uart_cfg *cfg; uint32_t cr1, cr2, cr3; if (port >= UART_CNT) { return -1; } u = &uarts[port]; if (u->u_open) { return -1; } cfg = bsp_uart_config(port); assert(cfg); /* * RCC * pin config * UART config * nvic config * enable uart */ cr1 = cfg->suc_uart->CR1; cr2 = cfg->suc_uart->CR2; cr3 = cfg->suc_uart->CR3; cr1 &= ~(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_RE | USART_CR1_OVER8); cr2 &= ~(USART_CR2_STOP); cr3 &= ~(USART_CR3_RTSE | USART_CR3_CTSE); switch (databits) { case 8: cr1 |= UART_WORDLENGTH_8B; break; case 9: cr1 |= UART_WORDLENGTH_9B; break; default: assert(0); return -1; } switch (stopbits) { case 1: cr2 |= UART_STOPBITS_1; break; case 2: cr2 |= UART_STOPBITS_2; break; default: return -1; } switch (parity) { case HAL_UART_PARITY_NONE: cr1 |= UART_PARITY_NONE; break; case HAL_UART_PARITY_ODD: cr1 |= UART_PARITY_ODD; break; case HAL_UART_PARITY_EVEN: cr1 |= UART_PARITY_EVEN; break; } switch (flow_ctl) { case HAL_UART_FLOW_CTL_NONE: cr3 |= UART_HWCONTROL_NONE; break; case HAL_UART_FLOW_CTL_RTS_CTS: cr3 |= UART_HWCONTROL_RTS_CTS; if (cfg->suc_pin_rts < 0 || cfg->suc_pin_cts < 0) { /* * Can't turn on HW flow control if pins to do that are not * defined. */ assert(0); return -1; } break; } cr1 |= (UART_MODE_RX | UART_MODE_TX | UART_OVERSAMPLING_16); *cfg->suc_rcc_reg |= cfg->suc_rcc_dev; hal_gpio_init_af(cfg->suc_pin_tx, cfg->suc_pin_af, 0); hal_gpio_init_af(cfg->suc_pin_rx, cfg->suc_pin_af, 0); if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) { hal_gpio_init_af(cfg->suc_pin_rts, cfg->suc_pin_af, 0); hal_gpio_init_af(cfg->suc_pin_cts, cfg->suc_pin_af, 0); } u->u_regs = cfg->suc_uart; u->u_regs->CR3 = cr3; u->u_regs->CR2 = cr2; u->u_regs->CR1 = cr1; if (cfg->suc_uart == USART1 || cfg->suc_uart == USART6) { u->u_regs->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), baudrate); } else { u->u_regs->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), baudrate); } (void)u->u_regs->DR; (void)u->u_regs->SR; hal_uart_set_nvic(cfg->suc_irqn, u); u->u_regs->CR1 |= (USART_CR1_RXNEIE | USART_CR1_UE); u->u_open = 1; return 0; }
void USART_Configure(void) { RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN; //Enable all necessary clocks RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* USART1 */ RCC->APB2ENR |= RCC_APB2ENR_USART1EN; //Enable USART1 // USART1 to PA9/PA10 // AFIO->MAPR |= AFIO_MAPR_USART1_REMAP; //Remap pins GPIOA->CRH &= ~(GPIO_CRH_CNF9 | GPIO_CRH_CNF10 | GPIO_CRH_MODE10); //Clear all flags GPIOA->CRH |= GPIO_CRH_CNF9_1; //PB6 - TX, Output AF, PP GPIOA->CRH |= GPIO_CRH_MODE9; //Max. output speed 50 MHz GPIOA->CRH |= GPIO_CRH_CNF10_0; //PB7 - RX, Input floating USART1->CR1 |= USART_CR1_TE | USART_CR1_RE | USART_CR1_IDLEIE | USART_CR1_TCIE; //Enable IRQs USART1->BRR = UART_BRR_SAMPLING16(APB2CLK, BAUDRATE); //Set baudrate USART1->CR3 |= USART_CR3_DMAR; //Enable DMA Rx //Configure DMA Channel 5 for USART1_RX DMA1_Channel5->CPAR = (uint32_t)&USART1->DR; //Source (USART->DR Peripheral) DMA1_Channel5->CMAR = (uint32_t)&Usart1Buf; //Dest (memory) DMA1_Channel5->CNDTR = USART_BUF_LEN; //Max buf length DMA1_Channel5->CCR &= ~DMA_CCR1_DIR; //Read from peripheral DMA1_Channel5->CCR |= DMA_CCR1_MINC; //Increment memory DMA1_Channel5->CCR |= DMA_CCR1_CIRC; //Circular mode DMA1_Channel5->CCR |= DMA_CCR1_EN; //Enable Channel USART1->CR3 |= USART_CR3_DMAT; //Enable DMA Tx //Configure DMA Channel 4 for USART1_TX DMA1_Channel4->CPAR = (uint32_t)&USART1->DR; //Dest (USART->DR Peripheral) DMA1_Channel4->CCR |= DMA_CCR1_MINC; //Increment memory DMA1_Channel4->CCR |= DMA_CCR1_DIR; //Send to peripheral USART1->CR1 |= USART_CR1_UE; //Enable USART1 NVIC_SetPriority(USART1_IRQn, 5); //Set IRQ priorities NVIC_EnableIRQ(USART1_IRQn); //Enable IRQ /* USART2 */ /* RCC->APB1ENR |= RCC_APB1ENR_USART2EN; //Enable USART2 GPIOA->CRL &= ~(GPIO_CRL_CNF2 | GPIO_CRL_CNF3 | GPIO_CRL_MODE3); //Clear all flags GPIOA->CRL |= GPIO_CRL_CNF2_1; //PA2 - TX, Output AF, PP GPIOA->CRL |= GPIO_CRL_MODE2; //Max. output speed 50 MHz GPIOA->CRL |= GPIO_CRL_CNF3_0; //PA3 - RX, Input floating USART2->CR1 |= USART_CR1_RE | USART_CR1_TE | USART_CR1_IDLEIE | USART_CR1_TCIE; //Enable IRQs USART2->BRR = UART_BRR_SAMPLING16(APB1CLK, BAUDRATE); //Set baudrate USART2->CR3 |= USART_CR3_DMAR; //Enable DMA Rx //Configure DMA Channel 5 for USART2_RX DMA1_Channel6->CPAR = (uint32_t)&USART2->DR; //Source (USART->DR Peripheral) DMA1_Channel6->CMAR = (uint32_t)&Usart2Buf; //Dest (memory) DMA1_Channel6->CNDTR = USART_BUF_LEN; //Max buf length DMA1_Channel6->CCR &= ~DMA_CCR1_DIR; //Read from peripheral DMA1_Channel6->CCR |= DMA_CCR1_MINC; //Increment memory DMA1_Channel6->CCR |= DMA_CCR1_CIRC; //Circular mode DMA1_Channel6->CCR |= DMA_CCR1_EN; //Enable Channel USART2->CR3 |= USART_CR3_DMAT; //Enable DMA Tx //Configure DMA Channel 7 for USART2_TX DMA1_Channel7->CPAR = (uint32_t)&USART2->DR; //Dest (USART->DR Peripheral) DMA1_Channel7->CCR |= DMA_CCR1_MINC; //Increment memory DMA1_Channel7->CCR |= DMA_CCR1_DIR; //Send to peripheral USART2->CR1 |= USART_CR1_UE; //Enable USART2 NVIC_SetPriority(USART2_IRQn, 5); //Set IRQ priorities NVIC_EnableIRQ(USART2_IRQn); //Enable IRQ */ }