/******************************************************************************* * Function Name: UART_SetPins ****************************************************************************//** * * Sets the pins settings accordingly to the selected operation mode. * Only available in the Unconfigured operation mode. The mode specific * initialization function calls it. * Pins configuration is set by PSoC Creator when a specific mode of operation * is selected in design time. * * \param mode: Mode of SCB operation. * \param subMode: Sub-mode of SCB operation. It is only required for SPI and UART * modes. * \param uartEnableMask: enables TX or RX direction and RTS and CTS signals. * *******************************************************************************/ void UART_SetPins(uint32 mode, uint32 subMode, uint32 uartEnableMask) { uint32 pinsDm[UART_SCB_PINS_NUMBER]; uint32 i; #if (!UART_CY_SCBIP_V1) uint32 pinsInBuf = 0u; #endif /* (!UART_CY_SCBIP_V1) */ uint32 hsiomSel[UART_SCB_PINS_NUMBER] = { UART_RX_SCL_MOSI_HSIOM_SEL_GPIO, UART_TX_SDA_MISO_HSIOM_SEL_GPIO, 0u, 0u, 0u, 0u, 0u, }; #if (UART_CY_SCBIP_V1) /* Supress compiler warning. */ if ((0u == subMode) || (0u == uartEnableMask)) { } #endif /* (UART_CY_SCBIP_V1) */ /* Set default HSIOM to GPIO and Drive Mode to Analog Hi-Z */ for (i = 0u; i < UART_SCB_PINS_NUMBER; i++) { pinsDm[i] = UART_PIN_DM_ALG_HIZ; } if ((UART_SCB_MODE_I2C == mode) || (UART_SCB_MODE_EZI2C == mode)) { #if (UART_RX_SCL_MOSI_PIN) hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_I2C; pinsDm [UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_OD_LO; #elif (UART_RX_WAKE_SCL_MOSI_PIN) hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_I2C; pinsDm [UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_OD_LO; #else #endif /* (UART_RX_SCL_MOSI_PIN) */ #if (UART_TX_SDA_MISO_PIN) hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_I2C; pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_OD_LO; #endif /* (UART_TX_SDA_MISO_PIN) */ } #if (!UART_CY_SCBIP_V1) else if (UART_SCB_MODE_SPI == mode) { #if (UART_RX_SCL_MOSI_PIN) hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_SPI; #elif (UART_RX_WAKE_SCL_MOSI_PIN) hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_SPI; #else #endif /* (UART_RX_SCL_MOSI_PIN) */ #if (UART_TX_SDA_MISO_PIN) hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_SPI; #endif /* (UART_TX_SDA_MISO_PIN) */ #if (UART_CTS_SCLK_PIN) hsiomSel[UART_CTS_SCLK_PIN_INDEX] = UART_CTS_SCLK_HSIOM_SEL_SPI; #endif /* (UART_CTS_SCLK_PIN) */ if (UART_SPI_SLAVE == subMode) { /* Slave */ pinsDm[UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; pinsDm[UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_STRONG; pinsDm[UART_CTS_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; #if (UART_RTS_SS0_PIN) /* Only SS0 is valid choice for Slave */ hsiomSel[UART_RTS_SS0_PIN_INDEX] = UART_RTS_SS0_HSIOM_SEL_SPI; pinsDm [UART_RTS_SS0_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; #endif /* (UART_RTS_SS0_PIN) */ #if (UART_TX_SDA_MISO_PIN) /* Disable input buffer */ pinsInBuf |= UART_TX_SDA_MISO_PIN_MASK; #endif /* (UART_TX_SDA_MISO_PIN) */ } else { /* (Master) */ pinsDm[UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_STRONG; pinsDm[UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; pinsDm[UART_CTS_SCLK_PIN_INDEX] = UART_PIN_DM_STRONG; #if (UART_RTS_SS0_PIN) hsiomSel [UART_RTS_SS0_PIN_INDEX] = UART_RTS_SS0_HSIOM_SEL_SPI; pinsDm [UART_RTS_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; pinsInBuf |= UART_RTS_SS0_PIN_MASK; #endif /* (UART_RTS_SS0_PIN) */ #if (UART_SS1_PIN) hsiomSel [UART_SS1_PIN_INDEX] = UART_SS1_HSIOM_SEL_SPI; pinsDm [UART_SS1_PIN_INDEX] = UART_PIN_DM_STRONG; pinsInBuf |= UART_SS1_PIN_MASK; #endif /* (UART_SS1_PIN) */ #if (UART_SS2_PIN) hsiomSel [UART_SS2_PIN_INDEX] = UART_SS2_HSIOM_SEL_SPI; pinsDm [UART_SS2_PIN_INDEX] = UART_PIN_DM_STRONG; pinsInBuf |= UART_SS2_PIN_MASK; #endif /* (UART_SS2_PIN) */ #if (UART_SS3_PIN) hsiomSel [UART_SS3_PIN_INDEX] = UART_SS3_HSIOM_SEL_SPI; pinsDm [UART_SS3_PIN_INDEX] = UART_PIN_DM_STRONG; pinsInBuf |= UART_SS3_PIN_MASK; #endif /* (UART_SS3_PIN) */ /* Disable input buffers */ #if (UART_RX_SCL_MOSI_PIN) pinsInBuf |= UART_RX_SCL_MOSI_PIN_MASK; #elif (UART_RX_WAKE_SCL_MOSI_PIN) pinsInBuf |= UART_RX_WAKE_SCL_MOSI_PIN_MASK; #else #endif /* (UART_RX_SCL_MOSI_PIN) */ #if (UART_CTS_SCLK_PIN) pinsInBuf |= UART_CTS_SCLK_PIN_MASK; #endif /* (UART_CTS_SCLK_PIN) */ } } else /* UART */ { if (UART_UART_MODE_SMARTCARD == subMode) { /* SmartCard */ #if (UART_TX_SDA_MISO_PIN) hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_UART; pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_OD_LO; #endif /* (UART_TX_SDA_MISO_PIN) */ } else /* Standard or IrDA */ { if (0u != (UART_UART_RX_PIN_ENABLE & uartEnableMask)) { #if (UART_RX_SCL_MOSI_PIN) hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX] = UART_RX_SCL_MOSI_HSIOM_SEL_UART; pinsDm [UART_RX_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; #elif (UART_RX_WAKE_SCL_MOSI_PIN) hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_RX_WAKE_SCL_MOSI_HSIOM_SEL_UART; pinsDm [UART_RX_WAKE_SCL_MOSI_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; #else #endif /* (UART_RX_SCL_MOSI_PIN) */ } if (0u != (UART_UART_TX_PIN_ENABLE & uartEnableMask)) { #if (UART_TX_SDA_MISO_PIN) hsiomSel[UART_TX_SDA_MISO_PIN_INDEX] = UART_TX_SDA_MISO_HSIOM_SEL_UART; pinsDm [UART_TX_SDA_MISO_PIN_INDEX] = UART_PIN_DM_STRONG; /* Disable input buffer */ pinsInBuf |= UART_TX_SDA_MISO_PIN_MASK; #endif /* (UART_TX_SDA_MISO_PIN) */ } #if !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) if (UART_UART_MODE_STD == subMode) { if (0u != (UART_UART_CTS_PIN_ENABLE & uartEnableMask)) { /* CTS input is multiplexed with SCLK */ #if (UART_CTS_SCLK_PIN) hsiomSel[UART_CTS_SCLK_PIN_INDEX] = UART_CTS_SCLK_HSIOM_SEL_UART; pinsDm [UART_CTS_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; #endif /* (UART_CTS_SCLK_PIN) */ } if (0u != (UART_UART_RTS_PIN_ENABLE & uartEnableMask)) { /* RTS output is multiplexed with SS0 */ #if (UART_RTS_SS0_PIN) hsiomSel[UART_RTS_SS0_PIN_INDEX] = UART_RTS_SS0_HSIOM_SEL_UART; pinsDm [UART_RTS_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; /* Disable input buffer */ pinsInBuf |= UART_RTS_SS0_PIN_MASK; #endif /* (UART_RTS_SS0_PIN) */ } } #endif /* !(UART_CY_SCBIP_V0 || UART_CY_SCBIP_V1) */ } } #endif /* (!UART_CY_SCBIP_V1) */ /* Configure pins: set HSIOM, DM and InputBufEnable */ /* Note: the DR register settings do not effect the pin output if HSIOM is other than GPIO */ #if (UART_RX_SCL_MOSI_PIN) UART_SET_HSIOM_SEL(UART_RX_SCL_MOSI_HSIOM_REG, UART_RX_SCL_MOSI_HSIOM_MASK, UART_RX_SCL_MOSI_HSIOM_POS, hsiomSel[UART_RX_SCL_MOSI_PIN_INDEX]); UART_uart_rx_i2c_scl_spi_mosi_SetDriveMode((uint8) pinsDm[UART_RX_SCL_MOSI_PIN_INDEX]); #if (!UART_CY_SCBIP_V1) UART_SET_INP_DIS(UART_uart_rx_i2c_scl_spi_mosi_INP_DIS, UART_uart_rx_i2c_scl_spi_mosi_MASK, (0u != (pinsInBuf & UART_RX_SCL_MOSI_PIN_MASK))); #endif /* (!UART_CY_SCBIP_V1) */ #elif (UART_RX_WAKE_SCL_MOSI_PIN) UART_SET_HSIOM_SEL(UART_RX_WAKE_SCL_MOSI_HSIOM_REG, UART_RX_WAKE_SCL_MOSI_HSIOM_MASK, UART_RX_WAKE_SCL_MOSI_HSIOM_POS, hsiomSel[UART_RX_WAKE_SCL_MOSI_PIN_INDEX]); UART_uart_rx_wake_i2c_scl_spi_mosi_SetDriveMode((uint8) pinsDm[UART_RX_WAKE_SCL_MOSI_PIN_INDEX]); UART_SET_INP_DIS(UART_uart_rx_wake_i2c_scl_spi_mosi_INP_DIS, UART_uart_rx_wake_i2c_scl_spi_mosi_MASK, (0u != (pinsInBuf & UART_RX_WAKE_SCL_MOSI_PIN_MASK))); /* Set interrupt on falling edge */ UART_SET_INCFG_TYPE(UART_RX_WAKE_SCL_MOSI_INTCFG_REG, UART_RX_WAKE_SCL_MOSI_INTCFG_TYPE_MASK, UART_RX_WAKE_SCL_MOSI_INTCFG_TYPE_POS, UART_INTCFG_TYPE_FALLING_EDGE); #else #endif /* (UART_RX_WAKE_SCL_MOSI_PIN) */ #if (UART_TX_SDA_MISO_PIN) UART_SET_HSIOM_SEL(UART_TX_SDA_MISO_HSIOM_REG, UART_TX_SDA_MISO_HSIOM_MASK, UART_TX_SDA_MISO_HSIOM_POS, hsiomSel[UART_TX_SDA_MISO_PIN_INDEX]); UART_uart_tx_i2c_sda_spi_miso_SetDriveMode((uint8) pinsDm[UART_TX_SDA_MISO_PIN_INDEX]); #if (!UART_CY_SCBIP_V1) UART_SET_INP_DIS(UART_uart_tx_i2c_sda_spi_miso_INP_DIS, UART_uart_tx_i2c_sda_spi_miso_MASK, (0u != (pinsInBuf & UART_TX_SDA_MISO_PIN_MASK))); #endif /* (!UART_CY_SCBIP_V1) */ #endif /* (UART_RX_SCL_MOSI_PIN) */ #if (UART_CTS_SCLK_PIN) UART_SET_HSIOM_SEL(UART_CTS_SCLK_HSIOM_REG, UART_CTS_SCLK_HSIOM_MASK, UART_CTS_SCLK_HSIOM_POS, hsiomSel[UART_CTS_SCLK_PIN_INDEX]); UART_uart_cts_spi_sclk_SetDriveMode((uint8) pinsDm[UART_CTS_SCLK_PIN_INDEX]); UART_SET_INP_DIS(UART_uart_cts_spi_sclk_INP_DIS, UART_uart_cts_spi_sclk_MASK, (0u != (pinsInBuf & UART_CTS_SCLK_PIN_MASK))); #endif /* (UART_CTS_SCLK_PIN) */ #if (UART_RTS_SS0_PIN) UART_SET_HSIOM_SEL(UART_RTS_SS0_HSIOM_REG, UART_RTS_SS0_HSIOM_MASK, UART_RTS_SS0_HSIOM_POS, hsiomSel[UART_RTS_SS0_PIN_INDEX]); UART_uart_rts_spi_ss0_SetDriveMode((uint8) pinsDm[UART_RTS_SS0_PIN_INDEX]); UART_SET_INP_DIS(UART_uart_rts_spi_ss0_INP_DIS, UART_uart_rts_spi_ss0_MASK, (0u != (pinsInBuf & UART_RTS_SS0_PIN_MASK))); #endif /* (UART_RTS_SS0_PIN) */ #if (UART_SS1_PIN) UART_SET_HSIOM_SEL(UART_SS1_HSIOM_REG, UART_SS1_HSIOM_MASK, UART_SS1_HSIOM_POS, hsiomSel[UART_SS1_PIN_INDEX]); UART_spi_ss1_SetDriveMode((uint8) pinsDm[UART_SS1_PIN_INDEX]); UART_SET_INP_DIS(UART_spi_ss1_INP_DIS, UART_spi_ss1_MASK, (0u != (pinsInBuf & UART_SS1_PIN_MASK))); #endif /* (UART_SS1_PIN) */ #if (UART_SS2_PIN) UART_SET_HSIOM_SEL(UART_SS2_HSIOM_REG, UART_SS2_HSIOM_MASK, UART_SS2_HSIOM_POS, hsiomSel[UART_SS2_PIN_INDEX]); UART_spi_ss2_SetDriveMode((uint8) pinsDm[UART_SS2_PIN_INDEX]); UART_SET_INP_DIS(UART_spi_ss2_INP_DIS, UART_spi_ss2_MASK, (0u != (pinsInBuf & UART_SS2_PIN_MASK))); #endif /* (UART_SS2_PIN) */ #if (UART_SS3_PIN) UART_SET_HSIOM_SEL(UART_SS3_HSIOM_REG, UART_SS3_HSIOM_MASK, UART_SS3_HSIOM_POS, hsiomSel[UART_SS3_PIN_INDEX]); UART_spi_ss3_SetDriveMode((uint8) pinsDm[UART_SS3_PIN_INDEX]); UART_SET_INP_DIS(UART_spi_ss3_INP_DIS, UART_spi_ss3_MASK, (0u != (pinsInBuf & UART_SS3_PIN_MASK))); #endif /* (UART_SS3_PIN) */ }
/******************************************************************************* * Function Name: UART_SetPins ******************************************************************************** * * Summary: * Sets pins settings accordingly to selected operation mode. * Only available in Unconfigured operation mode. The mode specific * initialization function calls it. * Pins configuration is set by PSoC Creator when specific mode of operation * selected in design time. * * Parameters: * mode: Mode of SCB operation. * subMode: Submode of SCB operation. It is only required for SPI and UART * modes. * uartTxRx: Direction for UART. * * Return: * None * *******************************************************************************/ void UART_SetPins(uint32 mode, uint32 subMode, uint32 uartTxRx) { uint32 hsiomSel[UART_SCB_PINS_NUMBER]; uint32 pinsDm [UART_SCB_PINS_NUMBER]; uint32 i; /* Make all unused */ for(i = 0u; i < UART_SCB_PINS_NUMBER; i++) { hsiomSel[i] = UART_HSIOM_DEF_SEL; pinsDm[i] = UART_PIN_DM_ALG_HIZ; } /* Choice the Dm and HSIOM */ if(UART_SCB_MODE_I2C == mode) { hsiomSel[UART_MOSI_SCL_RX_PIN_INDEX] = UART_HSIOM_I2C_SEL; hsiomSel[UART_MISO_SDA_TX_PIN_INDEX] = UART_HSIOM_I2C_SEL; pinsDm[UART_MOSI_SCL_RX_PIN_INDEX] = UART_PIN_DM_OD_LO; pinsDm[UART_MISO_SDA_TX_PIN_INDEX] = UART_PIN_DM_OD_LO; } else if(UART_SCB_MODE_SPI == mode) { hsiomSel[UART_MOSI_SCL_RX_PIN_INDEX] = UART_HSIOM_SPI_SEL; hsiomSel[UART_MISO_SDA_TX_PIN_INDEX] = UART_HSIOM_SPI_SEL; hsiomSel[UART_SCLK_PIN_INDEX] = UART_HSIOM_SPI_SEL; if(UART_SPI_SLAVE == subMode) { /* Slave */ pinsDm[UART_MOSI_SCL_RX_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; pinsDm[UART_MISO_SDA_TX_PIN_INDEX] = UART_PIN_DM_STRONG; pinsDm[UART_SCLK_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; #if(UART_SS0_PIN) /* Only SS0 is valid choice for Slave */ hsiomSel[UART_SS0_PIN_INDEX] = UART_HSIOM_SPI_SEL; pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; #endif /* (UART_SS1_PIN) */ } else /* (Master) */ { pinsDm[UART_MOSI_SCL_RX_PIN_INDEX] = UART_PIN_DM_STRONG; pinsDm[UART_MISO_SDA_TX_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; pinsDm[UART_SCLK_PIN_INDEX] = UART_PIN_DM_STRONG; #if(UART_SS0_PIN) hsiomSel[UART_SS0_PIN_INDEX] = UART_HSIOM_SPI_SEL; pinsDm [UART_SS0_PIN_INDEX] = UART_PIN_DM_STRONG; #endif /* (UART_SS0_PIN) */ #if(UART_SS1_PIN) hsiomSel[UART_SS1_PIN_INDEX] = UART_HSIOM_SPI_SEL; pinsDm [UART_SS1_PIN_INDEX] = UART_PIN_DM_STRONG; #endif /* (UART_SS1_PIN) */ #if(UART_SS2_PIN) hsiomSel[UART_SS2_PIN_INDEX] = UART_HSIOM_SPI_SEL; pinsDm [UART_SS2_PIN_INDEX] = UART_PIN_DM_STRONG; #endif /* (UART_SS2_PIN) */ #if(UART_SS3_PIN) hsiomSel[UART_SS3_PIN_INDEX] = UART_HSIOM_SPI_SEL; pinsDm [UART_SS3_PIN_INDEX] = UART_PIN_DM_STRONG; #endif /* (UART_SS2_PIN) */ } } else /* UART */ { if(UART_UART_MODE_SMARTCARD == subMode) { /* SmartCard */ hsiomSel[UART_MISO_SDA_TX_PIN_INDEX] = UART_HSIOM_UART_SEL; pinsDm [UART_MISO_SDA_TX_PIN_INDEX] = UART_PIN_DM_OD_LO; } else /* Standard or IrDA */ { if(0u != (UART_UART_RX & uartTxRx)) { hsiomSel[UART_MOSI_SCL_RX_PIN_INDEX] = UART_HSIOM_UART_SEL; pinsDm [UART_MOSI_SCL_RX_PIN_INDEX] = UART_PIN_DM_DIG_HIZ; } if(0u != (UART_UART_TX & uartTxRx)) { hsiomSel[UART_MISO_SDA_TX_PIN_INDEX] = UART_HSIOM_UART_SEL; pinsDm [UART_MISO_SDA_TX_PIN_INDEX] = UART_PIN_DM_STRONG; } } } /* Condfigure pins: set HSIOM and DM */ /* Condfigure pins: DR registers configuration remains unchanged for cyfitter_cfg() */ #if(UART_MOSI_SCL_RX_PIN) UART_SET_HSIOM_SEL(UART_MOSI_SCL_RX_HSIOM_REG, UART_MOSI_SCL_RX_HSIOM_MASK, UART_MOSI_SCL_RX_HSIOM_POS, hsiomSel[UART_MOSI_SCL_RX_PIN_INDEX]); #endif /* (UART_MOSI_SCL_RX_PIN) */ #if(UART_MOSI_SCL_RX_WAKE_PIN) UART_SET_HSIOM_SEL(UART_MOSI_SCL_RX_WAKE_HSIOM_REG, UART_MOSI_SCL_RX_WAKE_HSIOM_MASK, UART_MOSI_SCL_RX_WAKE_HSIOM_POS, hsiomSel[UART_MOSI_SCL_RX_WAKE_PIN_INDEX]); #endif /* (UART_MOSI_SCL_RX_WAKE_PIN) */ #if(UART_MISO_SDA_TX_PIN) UART_SET_HSIOM_SEL(UART_MISO_SDA_TX_HSIOM_REG, UART_MISO_SDA_TX_HSIOM_MASK, UART_MISO_SDA_TX_HSIOM_POS, hsiomSel[UART_MISO_SDA_TX_PIN_INDEX]); #endif /* (UART_MOSI_SCL_RX_PIN) */ #if(UART_SCLK_PIN) UART_SET_HSIOM_SEL(UART_SCLK_HSIOM_REG, UART_SCLK_HSIOM_MASK, UART_SCLK_HSIOM_POS, hsiomSel[UART_SCLK_PIN_INDEX]); #endif /* (UART_SCLK_PIN) */ #if(UART_SS0_PIN) UART_SET_HSIOM_SEL(UART_SS0_HSIOM_REG, UART_SS0_HSIOM_MASK, UART_SS0_HSIOM_POS, hsiomSel[UART_SS0_PIN_INDEX]); #endif /* (UART_SS1_PIN) */ #if(UART_SS1_PIN) UART_SET_HSIOM_SEL(UART_SS1_HSIOM_REG, UART_SS1_HSIOM_MASK, UART_SS1_HSIOM_POS, hsiomSel[UART_SS1_PIN_INDEX]); #endif /* (UART_SS1_PIN) */ #if(UART_SS2_PIN) UART_SET_HSIOM_SEL(UART_SS2_HSIOM_REG, UART_SS2_HSIOM_MASK, UART_SS2_HSIOM_POS, hsiomSel[UART_SS2_PIN_INDEX]); #endif /* (UART_SS2_PIN) */ #if(UART_SS3_PIN) UART_SET_HSIOM_SEL(UART_SS3_HSIOM_REG, UART_SS3_HSIOM_MASK, UART_SS3_HSIOM_POS, hsiomSel[UART_SS3_PIN_INDEX]); #endif /* (UART_SS3_PIN) */ #if(UART_MOSI_SCL_RX_PIN) UART_spi_mosi_i2c_scl_uart_rx_SetDriveMode((uint8) pinsDm[UART_MOSI_SCL_RX_PIN_INDEX]); #endif /* (UART_MOSI_SCL_RX_PIN) */ #if(UART_MOSI_SCL_RX_WAKE_PIN) UART_spi_mosi_i2c_scl_uart_rx_wake_SetDriveMode((uint8) pinsDm[UART_MOSI_SCL_RX_WAKE_PIN_INDEX]); /* Set interrupt on rising edge */ UART_SET_INCFG_TYPE(UART_MOSI_SCL_RX_WAKE_INTCFG_REG, UART_MOSI_SCL_RX_WAKE_INTCFG_TYPE_MASK, UART_MOSI_SCL_RX_WAKE_INTCFG_TYPE_POS, UART_INTCFG_TYPE_FALLING_EDGE); #endif /* (UART_MOSI_SCL_RX_WAKE_PIN) */ #if(UART_MISO_SDA_TX_PIN) UART_spi_miso_i2c_sda_uart_tx_SetDriveMode((uint8) pinsDm[UART_MISO_SDA_TX_PIN_INDEX]); #endif /* (UART_MOSI_SCL_RX_PIN) */ #if(UART_SCLK_PIN) UART_spi_sclk_SetDriveMode((uint8) pinsDm[UART_SCLK_PIN_INDEX]); #endif /* (UART_SCLK_PIN) */ #if(UART_SS0_PIN) UART_spi_ss0_SetDriveMode((uint8) pinsDm[UART_SS0_PIN_INDEX]); #endif /* (UART_SS0_PIN) */ #if(UART_SS1_PIN) UART_spi_ss1_SetDriveMode((uint8) pinsDm[UART_SS1_PIN_INDEX]); #endif /* (UART_SS1_PIN) */ #if(UART_SS2_PIN) UART_spi_ss2_SetDriveMode((uint8) pinsDm[UART_SS2_PIN_INDEX]); #endif /* (UART_SS2_PIN) */ #if(UART_SS3_PIN) UART_spi_ss3_SetDriveMode((uint8) pinsDm[UART_SS3_PIN_INDEX]); #endif /* (UART_SS3_PIN) */ }