CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "ucg.h"
const ucg_pgm_uint8_t ucg_ili9163_set_pos_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11( 0x036, 0x008),
UCG_C10(0x02a), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), UCG_D2(0x000, 0x07f), /* set x position */
UCG_C10(0x02b), UCG_VARY(0,0x00, 0), UCG_VARY(0,0x0ff, 0), UCG_D2(0x000, 0x0a1), /* set y position */
UCG_C10(0x02c), /* write to RAM */
UCG_DATA(), /* change to data mode */
UCG_END()
};
const ucg_pgm_uint8_t ucg_ili9163_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip */
/* 0x008 horizontal increment (dir = 0) */
/* 0x008 vertical increment (dir = 1) */
/* 0x048 horizontal deccrement (dir = 2) */
/* 0x088 vertical deccrement (dir = 3) */
UCG_C11( 0x036, 0x008),
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "ucg.h"
const ucg_pgm_uint8_t ucg_st7735_set_pos_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11( 0x036, 0x000),
UCG_C10(0x02a), UCG_VARX(0,0x00, 0), UCG_VARX(0,0x0ff, 0), UCG_A2(0x000, 0x07f), /* set x position */
UCG_C10(0x02b), UCG_VARY(0,0x00, 0), UCG_VARY(0,0x0ff, 0), UCG_A2(0x000, 0x09f), /* set y position */
UCG_C10(0x02c), /* write to RAM */
UCG_DATA(), /* change to data mode */
UCG_END()
};
const ucg_pgm_uint8_t ucg_st7735_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip */
/* 0x000 horizontal increment (dir = 0) */
/* 0x000 vertical increment (dir = 1) */
/* 0x040 horizontal deccrement (dir = 2) */
/* 0x080 vertical deccrement (dir = 3) */
UCG_C11( 0x036, 0x000),
0x05, 0x00 dir 0
0x05, 0x05 dir 1
0x05, 0x03 dir 2
0x05, 0x06 dir 3
Data Reading/Writing Box: 0x0a
8 bytes as arguments: xs, ys, xe, ye
*/
const ucg_pgm_uint8_t ucg_ld50t6160_set_pos_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11(0x05, 0x00),
UCG_C10(0x0a), UCG_VARX(4,0x0f, 0), UCG_VARX(0,0x0f, 0), UCG_A2(0x007, 0x0f), /* set x position */
UCG_VARY(4,0x0f, 0), UCG_VARY(0,0x0f, 0), UCG_A2(0x09, 0x0f), /* set y position */
UCG_C10(0x0c), /* write to RAM */
UCG_DATA(), /* change to data mode */
UCG_END()
};
const ucg_pgm_uint8_t ucg_ld50t6160_set_pos_dir0_seq[] =
{
UCG_CS(0), /* enable chip */
UCG_C11(0x05, 0x00),
UCG_C10(0x0a),
UCG_VARX(4,0x0f, 0), UCG_VARX(0,0x0f, 0), UCG_A2(0x007, 0x0f), /* set x position */
UCG_VARY(4,0x0f, 0), UCG_VARY(0,0x0f, 0), UCG_A2(0x09, 0x0f), /* set y position */
UCG_C10(0x0c), /* write to RAM */
