static void atmel_serial_activate(atmel_usart3_t *usart)
{
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)),
&usart->mr);
writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
/* 100us is enough for the new settings to be settled */
__udelay(100);
}
int serial_init(void)
{
usart3_writel(CR, USART3_BIT(RSTRX) | USART3_BIT(RSTTX));
serial_setbrg();
usart3_writel(CR, USART3_BIT(RXEN) | USART3_BIT(TXEN));
usart3_writel(MR, (USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
| USART3_BF(USCLKS, USART3_USCLKS_MCK)
| USART3_BF(CHRL, USART3_CHRL_8)
| USART3_BF(PAR, USART3_PAR_NONE)
| USART3_BF(NBSTOP, USART3_NBSTOP_1)));
return 0;
}
void _atmel_serial_init(atmel_usart3_t *usart,
ulong usart_clk_rate, int baudrate)
{
writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);
writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
USART3_BF(USCLKS, USART3_USCLKS_MCK) |
USART3_BF(CHRL, USART3_CHRL_8) |
USART3_BF(PAR, USART3_PAR_NONE) |
USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
_atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
}
static void _atmel_serial_set_brg(atmel_usart3_t *usart,
ulong usart_clk_rate, int baudrate)
{
unsigned long divisor;
divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
writel(USART3_BF(CD, divisor), &usart->brgr);
}
void serial_setbrg(void)
{
unsigned long divisor;
unsigned long usart_hz;
/*
* Master Clock
* Baud Rate = --------------
* 16 * CD
*/
usart_hz = get_usart_clk_rate(USART_ID);
divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
usart3_writel(BRGR, USART3_BF(CD, divisor));
}
void serial_setbrg(void)
{
unsigned long divisor;
unsigned long usart_hz;
/*
* Master Clock
* Baud Rate = --------------
* 16 * CD
*/
usart_hz = pm_get_clock_freq(gd->console_uart->resource[0].u.clock.id);
divisor = (usart_hz / 16 + gd->baudrate / 2) / gd->baudrate;
usart3_writel(gd->console_uart, BRGR, USART3_BF(CD, divisor));
}
static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
int baudrate)
{
unsigned long divisor;
unsigned long usart_hz;
/*
* Master Clock
* Baud Rate = --------------
* 16 * CD
*/
usart_hz = get_usart_clk_rate(id);
divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
writel(USART3_BF(CD, divisor), &usart->brgr);
}
