/**
* Process raw-mode specific forced actions.
*
* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
*
* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
* EM statuses.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pCtx Pointer to the guest CPU context.
*/
static int emR3HwaccmForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
{
/*
* Sync page directory.
*/
if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
{
Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (RT_FAILURE(rc))
return rc;
Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
/* Prefetch pages for EIP and ESP. */
/** @todo This is rather expensive. Should investigate if it really helps at all. */
rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
if (rc == VINF_SUCCESS)
rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
if (rc != VINF_SUCCESS)
{
if (rc != VINF_PGM_SYNC_CR3)
{
AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
return rc;
}
rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (RT_FAILURE(rc))
return rc;
}
/** @todo maybe prefetch the supervisor stack page as well */
Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT));
}
/*
* Allocate handy pages (just in case the above actions have consumed some pages).
*/
if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
{
int rc = PGMR3PhysAllocateHandyPages(pVM);
if (RT_FAILURE(rc))
return rc;
}
/*
* Check whether we're out of memory now.
*
* This may stem from some of the above actions or operations that has been executed
* since we ran FFs. The allocate handy pages must for instance always be followed by
* this check.
*/
if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
return VINF_EM_NO_MEMORY;
return VINF_SUCCESS;
}
/**
* Default VMR3Wait() worker.
*
* @returns VBox status code.
* @param pUVMCPU Pointer to the user mode VMCPU structure.
*/
static DECLCALLBACK(int) vmR3DefaultWait(PUVMCPU pUVCpu)
{
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
PVM pVM = pUVCpu->pVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
int rc = VINF_SUCCESS;
for (;;)
{
/*
* Check Relevant FFs.
*/
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK))
break;
/*
* Wait for a while. Someone will wake us up or interrupt the call if
* anything needs our attention.
*/
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, 1000);
if (rc == VERR_TIMEOUT)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "RTSemEventWait->%Rrc", rc);
break;
}
}
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* The global 1 halt method - VMR3Wait() worker.
*
* @returns VBox status code.
* @param pUVCpu Pointer to the user mode VMCPU structure.
*/
static DECLCALLBACK(int) vmR3HaltGlobal1Wait(PUVMCPU pUVCpu)
{
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
PVM pVM = pUVCpu->pUVM->pVM;
PVMCPU pVCpu = VMMGetCpu(pVM);
Assert(pVCpu->idCpu == pUVCpu->idCpu);
int rc = VINF_SUCCESS;
for (;;)
{
/*
* Check Relevant FFs.
*/
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK))
break;
/*
* Wait for a while. Someone will wake us up or interrupt the call if
* anything needs our attention.
*/
rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, VMMR0_DO_GVMM_SCHED_HALT, RTTimeNanoTS() + 1000000000 /* +1s */, NULL);
if (rc == VERR_INTERRUPTED)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "VMMR0_DO_GVMM_SCHED_HALT->%Rrc\n", rc);
break;
}
}
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* Suspended VM Wait.
* Only a handful of forced actions will cause the function to
* return to the caller.
*
* @returns VINF_SUCCESS unless a fatal error occurred. In the latter
* case an appropriate status code is returned.
* @param pUVCpu Pointer to the user mode VMCPU structure.
* @thread The emulation thread.
*/
VMMR3DECL(int) VMR3WaitU(PUVMCPU pUVCpu)
{
LogFlow(("VMR3WaitU:\n"));
/*
* Check Relevant FFs.
*/
PVM pVM = pUVCpu->pVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
if ( pVM
&& ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_SUSPENDED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_EXTERNAL_SUSPENDED_MASK)
)
)
{
LogFlow(("VMR3Wait: returns VINF_SUCCESS (FF %#x)\n", pVM->fGlobalForcedActions));
return VINF_SUCCESS;
}
/*
* Do waiting according to the halt method (so VMR3NotifyFF
* doesn't have to special case anything).
*/
PUVM pUVM = pUVCpu->pUVM;
int rc = g_aHaltMethods[pUVM->vm.s.iHaltMethod].pfnWait(pUVCpu);
LogFlow(("VMR3WaitU: returns %Rrc (FF %#x)\n", rc, pUVM->pVM ? pUVM->pVM->fGlobalForcedActions : 0));
return rc;
}
/**
* Steps hardware accelerated mode.
*
* @returns VBox status code.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
*/
static int emR3HwAccStep(PVM pVM, PVMCPU pVCpu)
{
Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_HWACC);
int rc;
PCPUMCTX pCtx = pVCpu->em.s.pCtx;
VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
/*
* Check vital forced actions, but ignore pending interrupts and timers.
*/
if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
{
rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
if (rc != VINF_SUCCESS)
return rc;
}
/*
* Set flags for single stepping.
*/
CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
/*
* Single step.
* We do not start time or anything, if anything we should just do a few nanoseconds.
*/
do
{
rc = VMMR3HwAccRunGC(pVM, pVCpu);
} while ( rc == VINF_SUCCESS
|| rc == VINF_EM_RAW_INTERRUPT);
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
/*
* Make sure the trap flag is cleared.
* (Too bad if the guest is trying to single step too.)
*/
CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
/*
* Deal with the return codes.
*/
rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
return rc;
}
/**
* Bootstrap VMR3Wait() worker.
*
* @returns VBox status code.
* @param pUVMCPU Pointer to the user mode VMCPU structure.
*/
static DECLCALLBACK(int) vmR3BootstrapWait(PUVMCPU pUVCpu)
{
PUVM pUVM = pUVCpu->pUVM;
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
int rc = VINF_SUCCESS;
for (;;)
{
/*
* Check Relevant FFs.
*/
if (pUVM->vm.s.pNormalReqs || pUVM->vm.s.pPriorityReqs) /* global requests pending? */
break;
if (pUVCpu->vm.s.pNormalReqs || pUVCpu->vm.s.pPriorityReqs) /* local requests pending? */
break;
if ( pUVCpu->pVM
&& ( VM_FF_ISPENDING(pUVCpu->pVM, VM_FF_EXTERNAL_SUSPENDED_MASK)
|| VMCPU_FF_ISPENDING(VMMGetCpu(pUVCpu->pVM), VMCPU_FF_EXTERNAL_SUSPENDED_MASK)
)
)
break;
if (pUVM->vm.s.fTerminateEMT)
break;
/*
* Wait for a while. Someone will wake us up or interrupt the call if
* anything needs our attention.
*/
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, 1000);
if (rc == VERR_TIMEOUT)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "RTSemEventWait->%Rrc\n", rc);
break;
}
}
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* The global 1 halt method - Block in GMM (ring-0) and let it
* try take care of the global scheduling of EMT threads.
*/
static DECLCALLBACK(int) vmR3HaltGlobal1Halt(PUVMCPU pUVCpu, const uint32_t fMask, uint64_t u64Now)
{
PUVM pUVM = pUVCpu->pUVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
PVM pVM = pUVCpu->pVM;
Assert(VMMGetCpu(pVM) == pVCpu);
NOREF(u64Now);
/*
* Halt loop.
*/
//uint64_t u64NowLog, u64Start;
//u64Start = u64NowLog = RTTimeNanoTS();
int rc = VINF_SUCCESS;
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
unsigned cLoops = 0;
for (;; cLoops++)
{
/*
* Work the timers and check if we can exit.
*/
uint64_t const u64StartTimers = RTTimeNanoTS();
TMR3TimerQueuesDo(pVM);
uint64_t const cNsElapsedTimers = RTTimeNanoTS() - u64StartTimers;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers);
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, fMask))
break;
/*
* Estimate time left to the next event.
*/
//u64NowLog = RTTimeNanoTS();
uint64_t u64Delta;
uint64_t u64GipTime = TMTimerPollGIP(pVM, pVCpu, &u64Delta);
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, fMask))
break;
/*
* Block if we're not spinning and the interval isn't all that small.
*/
if (u64Delta >= pUVM->vm.s.Halt.Global1.cNsSpinBlockThresholdCfg)
{
VMMR3YieldStop(pVM);
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, fMask))
break;
//RTLogPrintf("loop=%-3d u64GipTime=%'llu / %'llu now=%'llu / %'llu\n", cLoops, u64GipTime, u64Delta, u64NowLog, u64GipTime - u64NowLog);
uint64_t const u64StartSchedHalt = RTTimeNanoTS();
rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, VMMR0_DO_GVMM_SCHED_HALT, u64GipTime, NULL);
uint64_t const u64EndSchedHalt = RTTimeNanoTS();
uint64_t const cNsElapsedSchedHalt = u64EndSchedHalt - u64StartSchedHalt;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlock, cNsElapsedSchedHalt);
if (rc == VERR_INTERRUPTED)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "VMMR0_DO_GVMM_SCHED_HALT->%Rrc\n", rc);
break;
}
else
{
int64_t const cNsOverslept = u64EndSchedHalt - u64GipTime;
if (cNsOverslept > 50000)
STAM_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlockOverslept, cNsOverslept);
else if (cNsOverslept < -50000)
STAM_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlockInsomnia, cNsElapsedSchedHalt);
else
STAM_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlockOnTime, cNsElapsedSchedHalt);
}
}
/*
* When spinning call upon the GVMM and do some wakups once
* in a while, it's not like we're actually busy or anything.
*/
else if (!(cLoops & 0x1fff))
{
uint64_t const u64StartSchedYield = RTTimeNanoTS();
rc = SUPR3CallVMMR0Ex(pVM->pVMR0, pVCpu->idCpu, VMMR0_DO_GVMM_SCHED_POLL, false /* don't yield */, NULL);
uint64_t const cNsElapsedSchedYield = RTTimeNanoTS() - u64StartSchedYield;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltYield, cNsElapsedSchedYield);
}
}
//RTLogPrintf("*** %u loops %'llu; lag=%RU64\n", cLoops, u64NowLog - u64Start, TMVirtualSyncGetLag(pVM));
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* Method 1 - Block whenever possible, and when lagging behind
* switch to spinning for 10-30ms with occasional blocking until
* the lag has been eliminated.
*/
static DECLCALLBACK(int) vmR3HaltMethod1Halt(PUVMCPU pUVCpu, const uint32_t fMask, uint64_t u64Now)
{
PUVM pUVM = pUVCpu->pUVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
PVM pVM = pUVCpu->pVM;
/*
* To simplify things, we decide up-front whether we should switch to spinning or
* not. This makes some ASSUMPTIONS about the cause of the spinning (PIT/RTC/PCNet)
* and that it will generate interrupts or other events that will cause us to exit
* the halt loop.
*/
bool fBlockOnce = false;
bool fSpinning = false;
uint32_t u32CatchUpPct = TMVirtualSyncGetCatchUpPct(pVM);
if (u32CatchUpPct /* non-zero if catching up */)
{
if (pUVCpu->vm.s.Halt.Method12.u64StartSpinTS)
{
fSpinning = TMVirtualSyncGetLag(pVM) >= pUVM->vm.s.Halt.Method12.u32StopSpinningCfg;
if (fSpinning)
{
uint64_t u64Lag = TMVirtualSyncGetLag(pVM);
fBlockOnce = u64Now - pUVCpu->vm.s.Halt.Method12.u64LastBlockTS
> RT_MAX(pUVM->vm.s.Halt.Method12.u32MinBlockIntervalCfg,
RT_MIN(u64Lag / pUVM->vm.s.Halt.Method12.u32LagBlockIntervalDivisorCfg,
pUVM->vm.s.Halt.Method12.u32MaxBlockIntervalCfg));
}
else
{
//RTLogRelPrintf("Stopped spinning (%u ms)\n", (u64Now - pUVCpu->vm.s.Halt.Method12.u64StartSpinTS) / 1000000);
pUVCpu->vm.s.Halt.Method12.u64StartSpinTS = 0;
}
}
else
{
fSpinning = TMVirtualSyncGetLag(pVM) >= pUVM->vm.s.Halt.Method12.u32StartSpinningCfg;
if (fSpinning)
pUVCpu->vm.s.Halt.Method12.u64StartSpinTS = u64Now;
}
}
else if (pUVCpu->vm.s.Halt.Method12.u64StartSpinTS)
{
//RTLogRelPrintf("Stopped spinning (%u ms)\n", (u64Now - pUVCpu->vm.s.Halt.Method12.u64StartSpinTS) / 1000000);
pUVCpu->vm.s.Halt.Method12.u64StartSpinTS = 0;
}
/*
* Halt loop.
*/
int rc = VINF_SUCCESS;
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
unsigned cLoops = 0;
for (;; cLoops++)
{
/*
* Work the timers and check if we can exit.
*/
uint64_t const u64StartTimers = RTTimeNanoTS();
TMR3TimerQueuesDo(pVM);
uint64_t const cNsElapsedTimers = RTTimeNanoTS() - u64StartTimers;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers);
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, fMask))
break;
/*
* Estimate time left to the next event.
*/
uint64_t u64NanoTS;
TMTimerPollGIP(pVM, pVCpu, &u64NanoTS);
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, fMask))
break;
/*
* Block if we're not spinning and the interval isn't all that small.
*/
if ( ( !fSpinning
|| fBlockOnce)
#if 1 /* DEBUGGING STUFF - REMOVE LATER */
&& u64NanoTS >= 100000) /* 0.100 ms */
#else
&& u64NanoTS >= 250000) /* 0.250 ms */
#endif
{
const uint64_t Start = pUVCpu->vm.s.Halt.Method12.u64LastBlockTS = RTTimeNanoTS();
VMMR3YieldStop(pVM);
uint32_t cMilliSecs = RT_MIN(u64NanoTS / 1000000, 15);
if (cMilliSecs <= pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLongAvg)
cMilliSecs = 1;
else
cMilliSecs -= pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLongAvg;
//RTLogRelPrintf("u64NanoTS=%RI64 cLoops=%3d sleep %02dms (%7RU64) ", u64NanoTS, cLoops, cMilliSecs, u64NanoTS);
uint64_t const u64StartSchedHalt = RTTimeNanoTS();
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, cMilliSecs);
uint64_t const cNsElapsedSchedHalt = RTTimeNanoTS() - u64StartSchedHalt;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlock, cNsElapsedSchedHalt);
if (rc == VERR_TIMEOUT)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "RTSemEventWait->%Rrc\n", rc);
break;
}
/*
* Calc the statistics.
* Update averages every 16th time, and flush parts of the history every 64th time.
*/
const uint64_t Elapsed = RTTimeNanoTS() - Start;
pUVCpu->vm.s.Halt.Method12.cNSBlocked += Elapsed;
if (Elapsed > u64NanoTS)
pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLong += Elapsed - u64NanoTS;
pUVCpu->vm.s.Halt.Method12.cBlocks++;
if (!(pUVCpu->vm.s.Halt.Method12.cBlocks & 0xf))
{
pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLongAvg = pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLong / pUVCpu->vm.s.Halt.Method12.cBlocks;
if (!(pUVCpu->vm.s.Halt.Method12.cBlocks & 0x3f))
{
pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLong = pUVCpu->vm.s.Halt.Method12.cNSBlockedTooLongAvg * 0x40;
pUVCpu->vm.s.Halt.Method12.cBlocks = 0x40;
}
}
//RTLogRelPrintf(" -> %7RU64 ns / %7RI64 ns delta%s\n", Elapsed, Elapsed - u64NanoTS, fBlockOnce ? " (block once)" : "");
/*
* Clear the block once flag if we actually blocked.
*/
if ( fBlockOnce
&& Elapsed > 100000 /* 0.1 ms */)
fBlockOnce = false;
}
}
//if (fSpinning) RTLogRelPrintf("spun for %RU64 ns %u loops; lag=%RU64 pct=%d\n", RTTimeNanoTS() - u64Now, cLoops, TMVirtualSyncGetLag(pVM), u32CatchUpPct);
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* The old halt loop.
*/
static DECLCALLBACK(int) vmR3HaltOldDoHalt(PUVMCPU pUVCpu, const uint32_t fMask, uint64_t /* u64Now*/)
{
/*
* Halt loop.
*/
PVM pVM = pUVCpu->pVM;
PVMCPU pVCpu = pUVCpu->pVCpu;
int rc = VINF_SUCCESS;
ASMAtomicWriteBool(&pUVCpu->vm.s.fWait, true);
//unsigned cLoops = 0;
for (;;)
{
/*
* Work the timers and check if we can exit.
* The poll call gives us the ticks left to the next event in
* addition to perhaps set an FF.
*/
uint64_t const u64StartTimers = RTTimeNanoTS();
TMR3TimerQueuesDo(pVM);
uint64_t const cNsElapsedTimers = RTTimeNanoTS() - u64StartTimers;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltTimers, cNsElapsedTimers);
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, fMask))
break;
uint64_t u64NanoTS;
TMTimerPollGIP(pVM, pVCpu, &u64NanoTS);
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, fMask))
break;
/*
* Wait for a while. Someone will wake us up or interrupt the call if
* anything needs our attention.
*/
if (u64NanoTS < 50000)
{
//RTLogPrintf("u64NanoTS=%RI64 cLoops=%d spin\n", u64NanoTS, cLoops++);
/* spin */;
}
else
{
VMMR3YieldStop(pVM);
//uint64_t u64Start = RTTimeNanoTS();
if (u64NanoTS < 870000) /* this is a bit speculative... works fine on linux. */
{
//RTLogPrintf("u64NanoTS=%RI64 cLoops=%d yield", u64NanoTS, cLoops++);
uint64_t const u64StartSchedYield = RTTimeNanoTS();
RTThreadYield(); /* this is the best we can do here */
uint64_t const cNsElapsedSchedYield = RTTimeNanoTS() - u64StartSchedYield;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltYield, cNsElapsedSchedYield);
}
else if (u64NanoTS < 2000000)
{
//RTLogPrintf("u64NanoTS=%RI64 cLoops=%d sleep 1ms", u64NanoTS, cLoops++);
uint64_t const u64StartSchedHalt = RTTimeNanoTS();
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, 1);
uint64_t const cNsElapsedSchedHalt = RTTimeNanoTS() - u64StartSchedHalt;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlock, cNsElapsedSchedHalt);
}
else
{
//RTLogPrintf("u64NanoTS=%RI64 cLoops=%d sleep %dms", u64NanoTS, cLoops++, (uint32_t)RT_MIN((u64NanoTS - 500000) / 1000000, 15));
uint64_t const u64StartSchedHalt = RTTimeNanoTS();
rc = RTSemEventWait(pUVCpu->vm.s.EventSemWait, RT_MIN((u64NanoTS - 1000000) / 1000000, 15));
uint64_t const cNsElapsedSchedHalt = RTTimeNanoTS() - u64StartSchedHalt;
STAM_REL_PROFILE_ADD_PERIOD(&pUVCpu->vm.s.StatHaltBlock, cNsElapsedSchedHalt);
}
//uint64_t u64Slept = RTTimeNanoTS() - u64Start;
//RTLogPrintf(" -> rc=%Rrc in %RU64 ns / %RI64 ns delta\n", rc, u64Slept, u64NanoTS - u64Slept);
}
if (rc == VERR_TIMEOUT)
rc = VINF_SUCCESS;
else if (RT_FAILURE(rc))
{
rc = vmR3FatalWaitError(pUVCpu, "RTSemEventWait->%Rrc\n", rc);
break;
}
}
ASMAtomicUoWriteBool(&pUVCpu->vm.s.fWait, false);
return rc;
}
/**
* Halted VM Wait.
* Any external event will unblock the thread.
*
* @returns VINF_SUCCESS unless a fatal error occurred. In the latter
* case an appropriate status code is returned.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param fIgnoreInterrupts If set the VM_FF_INTERRUPT flags is ignored.
* @thread The emulation thread.
*/
VMMR3DECL(int) VMR3WaitHalted(PVM pVM, PVMCPU pVCpu, bool fIgnoreInterrupts)
{
LogFlow(("VMR3WaitHalted: fIgnoreInterrupts=%d\n", fIgnoreInterrupts));
/*
* Check Relevant FFs.
*/
const uint32_t fMask = !fIgnoreInterrupts
? VMCPU_FF_EXTERNAL_HALTED_MASK
: VMCPU_FF_EXTERNAL_HALTED_MASK & ~(VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC);
if ( VM_FF_ISPENDING(pVM, VM_FF_EXTERNAL_HALTED_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, fMask))
{
LogFlow(("VMR3WaitHalted: returns VINF_SUCCESS (FF %#x FFCPU %#x)\n", pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions));
return VINF_SUCCESS;
}
/*
* The yielder is suspended while we're halting, while TM might have clock(s) running
* only at certain times and need to be notified..
*/
if (pVCpu->idCpu == 0)
VMMR3YieldSuspend(pVM);
TMNotifyStartOfHalt(pVCpu);
/*
* Record halt averages for the last second.
*/
PUVMCPU pUVCpu = pVCpu->pUVCpu;
uint64_t u64Now = RTTimeNanoTS();
int64_t off = u64Now - pUVCpu->vm.s.u64HaltsStartTS;
if (off > 1000000000)
{
if (off > _4G || !pUVCpu->vm.s.cHalts)
{
pUVCpu->vm.s.HaltInterval = 1000000000 /* 1 sec */;
pUVCpu->vm.s.HaltFrequency = 1;
}
else
{
pUVCpu->vm.s.HaltInterval = (uint32_t)off / pUVCpu->vm.s.cHalts;
pUVCpu->vm.s.HaltFrequency = ASMMultU64ByU32DivByU32(pUVCpu->vm.s.cHalts, 1000000000, (uint32_t)off);
}
pUVCpu->vm.s.u64HaltsStartTS = u64Now;
pUVCpu->vm.s.cHalts = 0;
}
pUVCpu->vm.s.cHalts++;
/*
* Do the halt.
*/
Assert(VMCPU_GET_STATE(pVCpu) == VMCPUSTATE_STARTED);
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED_HALTED);
PUVM pUVM = pUVCpu->pUVM;
int rc = g_aHaltMethods[pUVM->vm.s.iHaltMethod].pfnHalt(pUVCpu, fMask, u64Now);
VMCPU_SET_STATE(pVCpu, VMCPUSTATE_STARTED);
/*
* Notify TM and resume the yielder
*/
TMNotifyEndOfHalt(pVCpu);
if (pVCpu->idCpu == 0)
VMMR3YieldResume(pVM);
LogFlow(("VMR3WaitHalted: returns %Rrc (FF %#x)\n", rc, pVM->fGlobalForcedActions));
return rc;
}
/**
* Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
*
* This function contains the raw-mode version of the inner
* execution loop (the outer loop being in EMR3ExecuteVM()).
*
* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
*
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param pfFFDone Where to store an indicator telling whether or not
* FFs were done before returning.
*/
int emR3HwAccExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
{
int rc = VERR_IPE_UNINITIALIZED_STATUS;
PCPUMCTX pCtx = pVCpu->em.s.pCtx;
LogFlow(("emR3HwAccExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
*pfFFDone = false;
STAM_COUNTER_INC(&pVCpu->em.s.StatHwAccExecuteEntry);
#ifdef EM_NOTIFY_HWACCM
HWACCMR3NotifyScheduled(pVCpu);
#endif
/*
* Spin till we get a forced action which returns anything but VINF_SUCCESS.
*/
for (;;)
{
STAM_PROFILE_ADV_START(&pVCpu->em.s.StatHwAccEntry, a);
/* Check if a forced reschedule is pending. */
if (HWACCMR3IsRescheduleRequired(pVM, pCtx))
{
rc = VINF_EM_RESCHEDULE;
break;
}
/*
* Process high priority pre-execution raw-mode FFs.
*/
VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
{
rc = emR3HwaccmForcedActions(pVM, pVCpu, pCtx);
if (rc != VINF_SUCCESS)
break;
}
#ifdef LOG_ENABLED
/*
* Log important stuff before entering GC.
*/
if (TRPMHasTrap(pVCpu))
Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs.Sel, (RTGCPTR)pCtx->rip));
uint32_t cpl = CPUMGetGuestCPL(pVCpu);
if (pVM->cCpus == 1)
{
if (pCtx->eflags.Bits.u1VM)
Log(("HWV86: %08X IF=%d\n", pCtx->eip, pCtx->eflags.Bits.u1IF));
else if (CPUMIsGuestIn64BitCodeEx(pCtx))
Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
else
Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
}
else
{
if (pCtx->eflags.Bits.u1VM)
Log(("HWV86-CPU%d: %08X IF=%d\n", pVCpu->idCpu, pCtx->eip, pCtx->eflags.Bits.u1IF));
else if (CPUMIsGuestIn64BitCodeEx(pCtx))
Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
else
Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
}
#endif /* LOG_ENABLED */
/*
* Execute the code.
*/
STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatHwAccEntry, a);
if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
{
STAM_PROFILE_START(&pVCpu->em.s.StatHwAccExec, x);
rc = VMMR3HwAccRunGC(pVM, pVCpu);
STAM_PROFILE_STOP(&pVCpu->em.s.StatHwAccExec, x);
}
else
{
/* Give up this time slice; virtual time continues */
STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
RTThreadSleep(5);
STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
rc = VINF_SUCCESS;
}
/*
* Deal with high priority post execution FFs before doing anything else.
*/
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
/*
* Process the returned status code.
*/
if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
break;
rc = emR3HwaccmHandleRC(pVM, pVCpu, pCtx, rc);
if (rc != VINF_SUCCESS)
break;
/*
* Check and execute forced actions.
*/
#ifdef VBOX_HIGH_RES_TIMERS_HACK
TMTimerPollVoid(pVM, pVCpu);
#endif
if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_MASK)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_MASK))
{
rc = emR3ForcedActions(pVM, pVCpu, rc);
VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
if ( rc != VINF_SUCCESS
&& rc != VINF_EM_RESCHEDULE_HWACC)
{
*pfFFDone = true;
break;
}
}
}
/*
* Return to outer loop.
*/
#if defined(LOG_ENABLED) && defined(DEBUG)
RTLogFlush(NULL);
#endif
return rc;
}
RT_C_DECLS_END
/**
* Exits the trap, called when exiting a trap handler.
*
* Will reset the trap if it's not a guest trap or the trap
* is already handled. Will process resume guest FFs.
*
* @returns rc, can be adjusted if its VINF_SUCCESS or something really bad
* happened.
* @param pVM Pointer to the VM.
* @param pVCpu Pointer to the VMCPU.
* @param rc The VBox status code to return.
* @param pRegFrame Pointer to the register frame for the trap.
*
* @remarks This must not be used for hypervisor traps, only guest traps.
*/
static int trpmGCExitTrap(PVM pVM, PVMCPU pVCpu, int rc, PCPUMCTXCORE pRegFrame)
{
uint32_t uOldActiveVector = pVCpu->trpm.s.uActiveVector;
NOREF(uOldActiveVector);
/* Reset trap? */
if ( rc != VINF_EM_RAW_GUEST_TRAP
&& rc != VINF_EM_RAW_RING_SWITCH_INT)
pVCpu->trpm.s.uActiveVector = UINT32_MAX;
#ifdef VBOX_HIGH_RES_TIMERS_HACK
/*
* We should poll the timers occasionally.
* We must *NOT* do this too frequently as it adds a significant overhead
* and it'll kill us if the trap load is high. (See @bugref{1354}.)
* (The heuristic is not very intelligent, we should really check trap
* frequency etc. here, but alas, we lack any such information atm.)
*/
static unsigned s_iTimerPoll = 0;
if (rc == VINF_SUCCESS)
{
if (!(++s_iTimerPoll & 0xf))
{
TMTimerPollVoid(pVM, pVCpu);
Log2(("TMTimerPoll at %08RX32 - VM_FF_TM_VIRTUAL_SYNC=%d VM_FF_TM_VIRTUAL_SYNC=%d\n", pRegFrame->eip,
VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC), VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)));
}
}
else
s_iTimerPoll = 0;
#endif
/* Clear pending inhibit interrupt state if required. (necessary for dispatching interrupts later on) */
if (VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
{
Log2(("VM_FF_INHIBIT_INTERRUPTS at %08RX32 successor %RGv\n", pRegFrame->eip, EMGetInhibitInterruptsPC(pVCpu)));
if (pRegFrame->eip != EMGetInhibitInterruptsPC(pVCpu))
{
/** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
*/
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
}
}
/*
* Pending resume-guest-FF?
* Or pending (A)PIC interrupt? Windows XP will crash if we delay APIC interrupts.
*/
if ( rc == VINF_SUCCESS
&& ( VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC | VM_FF_REQUEST | VM_FF_PGM_NO_MEMORY | VM_FF_PDM_DMA)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_TO_R3 | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
| VMCPU_FF_REQUEST | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL
| VMCPU_FF_PDM_CRITSECT)
)
)
{
/* The out of memory condition naturally outranks the others. */
if (RT_UNLIKELY(VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)))
rc = VINF_EM_NO_MEMORY;
/* Pending Ring-3 action. */
else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TO_R3 | VMCPU_FF_PDM_CRITSECT))
{
VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
rc = VINF_EM_RAW_TO_R3;
}
/* Pending timer action. */
else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER))
rc = VINF_EM_RAW_TIMER_PENDING;
/* The Virtual Sync clock has stopped. */
else if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
rc = VINF_EM_RAW_TO_R3;
/* DMA work pending? */
else if (VM_FF_ISPENDING(pVM, VM_FF_PDM_DMA))
rc = VINF_EM_RAW_TO_R3;
/* Pending request packets might contain actions that need immediate
attention, such as pending hardware interrupts. */
else if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
rc = VINF_EM_PENDING_REQUEST;
/* Pending interrupt: dispatch it. */
else if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC)
&& !VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
&& PATMAreInterruptsEnabledByCtxCore(pVM, pRegFrame)
)
{
uint8_t u8Interrupt;
rc = PDMGetInterrupt(pVCpu, &u8Interrupt);
Log(("trpmGCExitTrap: u8Interrupt=%d (%#x) rc=%Rrc\n", u8Interrupt, u8Interrupt, rc));
AssertFatalMsgRC(rc, ("PDMGetInterrupt failed with %Rrc\n", rc));
rc = TRPMForwardTrap(pVCpu, pRegFrame, (uint32_t)u8Interrupt, 0, TRPM_TRAP_NO_ERRORCODE, TRPM_HARDWARE_INT, uOldActiveVector);
/* can't return if successful */
Assert(rc != VINF_SUCCESS);
/* Stop the profile counter that was started in TRPMGCHandlersA.asm */
Assert(uOldActiveVector <= 16);
STAM_PROFILE_ADV_STOP(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
/* Assert the trap and go to the recompiler to dispatch it. */
TRPMAssertTrap(pVCpu, u8Interrupt, TRPM_HARDWARE_INT);
STAM_PROFILE_ADV_START(&pVM->trpm.s.aStatGCTraps[uOldActiveVector], a);
rc = VINF_EM_RAW_INTERRUPT_PENDING;
}
/*
* Try sync CR3?
*/
else if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
{
#if 1
PGMRZDynMapReleaseAutoSet(pVCpu);
PGMRZDynMapStartAutoSet(pVCpu);
rc = PGMSyncCR3(pVCpu, CPUMGetGuestCR0(pVCpu), CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu), VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
#else
rc = VINF_PGM_SYNC_CR3;
#endif
}
}
AssertMsg( rc != VINF_SUCCESS
|| ( pRegFrame->eflags.Bits.u1IF
&& ( pRegFrame->eflags.Bits.u2IOPL < (unsigned)(pRegFrame->ss.Sel & X86_SEL_RPL) || pRegFrame->eflags.Bits.u1VM))
, ("rc=%Rrc\neflags=%RX32 ss=%RTsel IOPL=%d\n", rc, pRegFrame->eflags.u32, pRegFrame->ss.Sel, pRegFrame->eflags.Bits.u2IOPL));
PGMRZDynMapReleaseAutoSet(pVCpu);
return rc;
}
/**
* Waits for the debugger to respond.
*
* @returns VBox status. (clearify)
* @param pVM Pointer to the VM.
*/
static int dbgfR3VMMWait(PVM pVM)
{
PVMCPU pVCpu = VMMGetCpu(pVM);
LogFlow(("dbgfR3VMMWait:\n"));
/** @todo stupid GDT/LDT sync hack. go away! */
SELMR3UpdateFromCPUM(pVM, pVCpu);
int rcRet = VINF_SUCCESS;
/*
* Waits for the debugger to reply (i.e. issue an command).
*/
for (;;)
{
/*
* Wait.
*/
uint32_t cPollHack = 1; /** @todo this interface is horrible now that we're using lots of VMR3ReqCall stuff all over DBGF. */
for (;;)
{
int rc;
if ( !VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_REQUEST)
&& !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
{
rc = RTSemPingWait(&pVM->dbgf.s.PingPong, cPollHack);
if (RT_SUCCESS(rc))
break;
if (rc != VERR_TIMEOUT)
{
LogFlow(("dbgfR3VMMWait: returns %Rrc\n", rc));
return rc;
}
}
if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
{
rc = VMMR3EmtRendezvousFF(pVM, pVCpu);
cPollHack = 1;
}
else if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST)
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
{
LogFlow(("dbgfR3VMMWait: Processes requests...\n"));
rc = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
if (rc == VINF_SUCCESS)
rc = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
LogFlow(("dbgfR3VMMWait: VMR3ReqProcess -> %Rrc rcRet=%Rrc\n", rc, rcRet));
cPollHack = 1;
}
else
{
rc = VINF_SUCCESS;
if (cPollHack < 120)
cPollHack++;
}
if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
{
switch (rc)
{
case VINF_EM_DBG_BREAKPOINT:
case VINF_EM_DBG_STEPPED:
case VINF_EM_DBG_STEP:
case VINF_EM_DBG_STOP:
AssertMsgFailed(("rc=%Rrc\n", rc));
break;
/* return straight away */
case VINF_EM_TERMINATE:
case VINF_EM_OFF:
LogFlow(("dbgfR3VMMWait: returns %Rrc\n", rc));
return rc;
/* remember return code. */
default:
AssertReleaseMsgFailed(("rc=%Rrc is not in the switch!\n", rc));
case VINF_EM_RESET:
case VINF_EM_SUSPEND:
case VINF_EM_HALT:
case VINF_EM_RESUME:
case VINF_EM_RESCHEDULE:
case VINF_EM_RESCHEDULE_REM:
case VINF_EM_RESCHEDULE_RAW:
if (rc < rcRet || rcRet == VINF_SUCCESS)
rcRet = rc;
break;
}
}
else if (RT_FAILURE(rc))
{
LogFlow(("dbgfR3VMMWait: returns %Rrc\n", rc));
return rc;
}
}
/*
* Process the command.
*/
bool fResumeExecution;
DBGFCMDDATA CmdData = pVM->dbgf.s.VMMCmdData;
DBGFCMD enmCmd = dbgfR3SetCmd(pVM, DBGFCMD_NO_COMMAND);
int rc = dbgfR3VMMCmd(pVM, enmCmd, &CmdData, &fResumeExecution);
if (fResumeExecution)
{
if (RT_FAILURE(rc))
rcRet = rc;
else if ( rc >= VINF_EM_FIRST
&& rc <= VINF_EM_LAST
&& (rc < rcRet || rcRet == VINF_SUCCESS))
rcRet = rc;
LogFlow(("dbgfR3VMMWait: returns %Rrc\n", rcRet));
return rcRet;
}
}
}