}
}
static const MemoryRegionOps bcm2835_aux_ops = {
.read = bcm2835_aux_read,
.write = bcm2835_aux_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription vmstate_bcm2835_aux = {
.name = "bcm2835_aux",
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(read_fifo, BCM2835AuxState, 8),
VMSTATE_INT32(read_pos, BCM2835AuxState),
VMSTATE_INT32(read_count, BCM2835AuxState),
VMSTATE_END_OF_LIST()
}
};
static void bcm2835_aux_init(Object *obj)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
BCM2835AuxState *s = BCM2835_AUX(obj);
memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_aux_ops, s,
"bcm2835_aux", 0x100);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
char *name = (char *)"goldfish-battery";
dev = qdev_create(&gbus->bus, name);
qdev_prop_set_string(dev, "name", name);
qdev_init_nofail(dev);
return dev;
}
static const VMStateDescription vmstate_goldfish_battery = {
.name = "goldfish_battery",
.version_id = 1,
.fields = (VMStateField []) {
VMSTATE_UINT32(int_status, GoldfishBatteryDevice),
VMSTATE_UINT32(int_enable, GoldfishBatteryDevice),
VMSTATE_INT32(ac_online, GoldfishBatteryDevice),
VMSTATE_INT32(status, GoldfishBatteryDevice),
VMSTATE_INT32(health, GoldfishBatteryDevice),
VMSTATE_INT32(present, GoldfishBatteryDevice),
VMSTATE_INT32(capacity, GoldfishBatteryDevice),
VMSTATE_END_OF_LIST()
}
};
static GoldfishDeviceInfo goldfish_battery_info = {
.init = goldfish_battery_init,
.readfn = goldfish_battery_readfn,
.writefn = goldfish_battery_writefn,
.qdev.name = "goldfish-battery",
.qdev.size = sizeof(GoldfishBatteryDevice),
.qdev.vmsd = &vmstate_goldfish_battery,
};
static const VMStateDescription vmstate_pl022 = {
.name = "pl022_ssp",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cr0, pl022_state),
VMSTATE_UINT32(cr1, pl022_state),
VMSTATE_UINT32(bitmask, pl022_state),
VMSTATE_UINT32(sr, pl022_state),
VMSTATE_UINT32(cpsr, pl022_state),
VMSTATE_UINT32(is, pl022_state),
VMSTATE_UINT32(im, pl022_state),
VMSTATE_INT32(tx_fifo_head, pl022_state),
VMSTATE_INT32(rx_fifo_head, pl022_state),
VMSTATE_INT32(tx_fifo_len, pl022_state),
VMSTATE_INT32(rx_fifo_len, pl022_state),
VMSTATE_UINT16(tx_fifo[0], pl022_state),
VMSTATE_UINT16(rx_fifo[0], pl022_state),
VMSTATE_UINT16(tx_fifo[1], pl022_state),
VMSTATE_UINT16(rx_fifo[1], pl022_state),
VMSTATE_UINT16(tx_fifo[2], pl022_state),
VMSTATE_UINT16(rx_fifo[2], pl022_state),
VMSTATE_UINT16(tx_fifo[3], pl022_state),
VMSTATE_UINT16(rx_fifo[3], pl022_state),
VMSTATE_UINT16(tx_fifo[4], pl022_state),
VMSTATE_UINT16(rx_fifo[4], pl022_state),
VMSTATE_UINT16(tx_fifo[5], pl022_state),
VMSTATE_UINT16(rx_fifo[5], pl022_state),
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(clock, pl181_state),
VMSTATE_UINT32(power, pl181_state),
VMSTATE_UINT32(cmdarg, pl181_state),
VMSTATE_UINT32(cmd, pl181_state),
VMSTATE_UINT32(datatimer, pl181_state),
VMSTATE_UINT32(datalength, pl181_state),
VMSTATE_UINT32(respcmd, pl181_state),
VMSTATE_UINT32_ARRAY(response, pl181_state, 4),
VMSTATE_UINT32(datactrl, pl181_state),
VMSTATE_UINT32(datacnt, pl181_state),
VMSTATE_UINT32(status, pl181_state),
VMSTATE_UINT32_ARRAY(mask, pl181_state, 2),
VMSTATE_INT32(fifo_pos, pl181_state),
VMSTATE_INT32(fifo_len, pl181_state),
VMSTATE_INT32(linux_hack, pl181_state),
VMSTATE_UINT32_ARRAY(fifo, pl181_state, PL181_FIFO_LEN),
VMSTATE_END_OF_LIST()
}
};
#define PL181_CMD_INDEX 0x3f
#define PL181_CMD_RESPONSE (1 << 6)
#define PL181_CMD_LONGRESP (1 << 7)
#define PL181_CMD_INTERRUPT (1 << 8)
#define PL181_CMD_PENDING (1 << 9)
#define PL181_CMD_ENABLE (1 << 10)
#define PL181_DATA_ENABLE (1 << 0)
s->enabled = dinfo ? bdrv_is_inserted(dinfo->bdrv) : 0;
memory_region_init_io(&s->regs_region, &memcard_mmio_ops, s,
"milkymist-memcard", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);
return 0;
}
static const VMStateDescription vmstate_milkymist_memcard = {
.name = "milkymist-memcard",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
VMSTATE_INT32(response_len, MilkymistMemcardState),
VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
VMSTATE_INT32(enabled, MilkymistMemcardState),
VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
VMSTATE_END_OF_LIST()
}
};
static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
return 0;
}
static bool apic_common_sipi_needed(void *opaque)
{
APICCommonState *s = APIC_COMMON(opaque);
return s->wait_for_sipi != 0;
}
static const VMStateDescription vmstate_apic_common_sipi = {
.name = "apic_sipi",
.version_id = 1,
.minimum_version_id = 1,
.needed = apic_common_sipi_needed,
.fields = (VMStateField[]) {
VMSTATE_INT32(sipi_vector, APICCommonState),
VMSTATE_INT32(wait_for_sipi, APICCommonState),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_apic_common = {
.name = "apic",
.version_id = 3,
.minimum_version_id = 3,
.minimum_version_id_old = 1,
.load_state_old = apic_load_old,
.pre_load = apic_pre_load,
.pre_save = apic_dispatch_pre_save,
.post_load = apic_dispatch_post_load,
.fields = (VMStateField[]) {
we need to initialize replay data fields. */
replay_fetch_data_kind();
return 0;
}
static const VMStateDescription vmstate_replay = {
.name = "replay",
.version_id = 1,
.minimum_version_id = 1,
.pre_save = replay_pre_save,
.post_load = replay_post_load,
.fields = (VMStateField[]) {
VMSTATE_INT64_ARRAY(cached_clock, ReplayState, REPLAY_CLOCK_COUNT),
VMSTATE_UINT64(current_step, ReplayState),
VMSTATE_INT32(instructions_count, ReplayState),
VMSTATE_UINT32(data_kind, ReplayState),
VMSTATE_UINT32(has_unread_data, ReplayState),
VMSTATE_UINT64(file_offset, ReplayState),
VMSTATE_UINT64(block_request_id, ReplayState),
VMSTATE_END_OF_LIST()
},
};
void replay_vmstate_register(void)
{
vmstate_register(NULL, 0, &vmstate_replay, &replay_state);
}
void replay_vmstate_init(void)
{
.fields = (VMStateField[]) {
VMSTATE_UINT32(apicbase, APICCommonState),
VMSTATE_UINT8(id, APICCommonState),
VMSTATE_UINT8(arb_id, APICCommonState),
VMSTATE_UINT8(tpr, APICCommonState),
VMSTATE_UINT32(spurious_vec, APICCommonState),
VMSTATE_UINT8(log_dest, APICCommonState),
VMSTATE_UINT8(dest_mode, APICCommonState),
VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
VMSTATE_UINT32(esr, APICCommonState),
VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
VMSTATE_UINT32(divide_conf, APICCommonState),
VMSTATE_INT32(count_shift, APICCommonState),
VMSTATE_UINT32(initial_count, APICCommonState),
VMSTATE_INT64(initial_count_load_time, APICCommonState),
VMSTATE_INT64(next_time, APICCommonState),
VMSTATE_INT64(timer_expiry,
APICCommonState), /* open-coded timer state */
VMSTATE_END_OF_LIST()
}
};
static Property apic_properties_common[] = {
DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
true),
DEFINE_PROP_END_OF_LIST(),
};
MemoryRegion mmio;
} smc91c111_state;
static const VMStateDescription vmstate_smc91c111 = {
.name = "smc91c111",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField []) {
VMSTATE_UINT16(tcr, smc91c111_state),
VMSTATE_UINT16(rcr, smc91c111_state),
VMSTATE_UINT16(cr, smc91c111_state),
VMSTATE_UINT16(ctr, smc91c111_state),
VMSTATE_UINT16(gpr, smc91c111_state),
VMSTATE_UINT16(ptr, smc91c111_state),
VMSTATE_UINT16(ercv, smc91c111_state),
VMSTATE_INT32(bank, smc91c111_state),
VMSTATE_INT32(packet_num, smc91c111_state),
VMSTATE_INT32(tx_alloc, smc91c111_state),
VMSTATE_INT32(allocated, smc91c111_state),
VMSTATE_INT32(tx_fifo_len, smc91c111_state),
VMSTATE_INT32_ARRAY(tx_fifo, smc91c111_state, NUM_PACKETS),
VMSTATE_INT32(rx_fifo_len, smc91c111_state),
VMSTATE_INT32_ARRAY(rx_fifo, smc91c111_state, NUM_PACKETS),
VMSTATE_INT32(tx_fifo_done_len, smc91c111_state),
VMSTATE_INT32_ARRAY(tx_fifo_done, smc91c111_state, NUM_PACKETS),
VMSTATE_BUFFER_UNSAFE(data, smc91c111_state, 0, NUM_PACKETS * 2048),
VMSTATE_UINT8(int_level, smc91c111_state),
VMSTATE_UINT8(int_mask, smc91c111_state),
VMSTATE_END_OF_LIST()
}
};
else if (addr == 4)
d->timer2_preload = val & 0xfffff;
d->unlock_state = 0;
}
}
}
static const VMStateDescription vmstate_i6300esb = {
.name = "i6300esb_wdt",
.version_id = sizeof(I6300State),
.minimum_version_id = sizeof(I6300State),
.minimum_version_id_old = sizeof(I6300State),
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(dev, I6300State),
VMSTATE_INT32(reboot_enabled, I6300State),
VMSTATE_INT32(clock_scale, I6300State),
VMSTATE_INT32(int_type, I6300State),
VMSTATE_INT32(free_run, I6300State),
VMSTATE_INT32(locked, I6300State),
VMSTATE_INT32(enabled, I6300State),
VMSTATE_TIMER(timer, I6300State),
VMSTATE_UINT32(timer1_preload, I6300State),
VMSTATE_UINT32(timer2_preload, I6300State),
VMSTATE_INT32(stage, I6300State),
VMSTATE_INT32(unlock_state, I6300State),
VMSTATE_INT32(previous_reboot_flag, I6300State),
VMSTATE_END_OF_LIST()
}
};
uint32_t ufcr;
uint32_t ubmr;
uint32_t ubrc;
uint32_t ucr3;
qemu_irq irq;
CharDriverState *chr;
} IMXSerialState;
static const VMStateDescription vmstate_imx_serial = {
.name = "imx-serial",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_INT32(readbuff, IMXSerialState),
VMSTATE_UINT32(usr1, IMXSerialState),
VMSTATE_UINT32(usr2, IMXSerialState),
VMSTATE_UINT32(ucr1, IMXSerialState),
VMSTATE_UINT32(uts1, IMXSerialState),
VMSTATE_UINT32(onems, IMXSerialState),
VMSTATE_UINT32(ufcr, IMXSerialState),
VMSTATE_UINT32(ubmr, IMXSerialState),
VMSTATE_UINT32(ubrc, IMXSerialState),
VMSTATE_UINT32(ucr3, IMXSerialState),
VMSTATE_END_OF_LIST()
},
};
#define URXD_CHARRDY (1<<15) /* character read is valid */
ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
z->selected = 0;
z->enabled = 0;
z->pos = 0;
return 0;
}
static VMStateDescription vmstate_zipit_lcd_state = {
.name = "zipit-lcd",
.version_id = 2,
.minimum_version_id = 2,
.minimum_version_id_old = 2,
.fields = (VMStateField[]) {
VMSTATE_SSI_SLAVE(ssidev, ZipitLCD),
VMSTATE_INT32(selected, ZipitLCD),
VMSTATE_INT32(enabled, ZipitLCD),
VMSTATE_BUFFER(buf, ZipitLCD),
VMSTATE_UINT32(cur_reg, ZipitLCD),
VMSTATE_INT32(pos, ZipitLCD),
VMSTATE_END_OF_LIST(),
}
};
static void zipit_lcd_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
k->init = zipit_lcd_init;
k->transfer = zipit_lcd_transfer;
}
return olen;
}
static const TypeInfo adb_bus_type_info = {
.name = TYPE_ADB_BUS,
.parent = TYPE_BUS,
.instance_size = sizeof(ADBBusState),
};
const VMStateDescription vmstate_adb_device = {
.name = "adb_device",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_INT32(devaddr, ADBDevice),
VMSTATE_INT32(handler, ADBDevice),
VMSTATE_END_OF_LIST()
}
};
static void adb_device_realizefn(DeviceState *dev, Error **errp)
{
ADBDevice *d = ADB_DEVICE(dev);
ADBBusState *bus = ADB_BUS(qdev_get_parent_bus(dev));
if (bus->nb_devices >= MAX_ADB_DEVICES) {
return;
}
bus->devices[bus->nb_devices++] = d;
};
static bool spapr_vlan_rx_buffer_pools_needed(void *opaque)
{
VIOsPAPRVLANDevice *dev = opaque;
return (dev->compat_flags & SPAPRVLAN_FLAG_RX_BUF_POOLS) != 0;
}
static const VMStateDescription vmstate_rx_buffer_pool = {
.name = "spapr_llan/rx_buffer_pool",
.version_id = 1,
.minimum_version_id = 1,
.needed = spapr_vlan_rx_buffer_pools_needed,
.fields = (VMStateField[]) {
VMSTATE_INT32(bufsize, RxBufPool),
VMSTATE_INT32(count, RxBufPool),
VMSTATE_UINT64_ARRAY(bds, RxBufPool, RX_POOL_MAX_BDS),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_rx_pools = {
.name = "spapr_llan/rx_pools",
.version_id = 1,
.minimum_version_id = 1,
.needed = spapr_vlan_rx_buffer_pools_needed,
.fields = (VMStateField[]) {
VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(rx_pool, VIOsPAPRVLANDevice,
RX_MAX_POOLS, 1,
vmstate_rx_buffer_pool, RxBufPool),
.minimum_version_id_old = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(value, PXA2xxTimer0),
VMSTATE_END_OF_LIST(),
},
};
static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
.name = "pxa2xx_timer4",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
VMSTATE_INT32(oldclock, PXA2xxTimer4),
VMSTATE_INT32(clock, PXA2xxTimer4),
VMSTATE_UINT64(lastload, PXA2xxTimer4),
VMSTATE_UINT32(freq, PXA2xxTimer4),
VMSTATE_UINT32(control, PXA2xxTimer4),
VMSTATE_END_OF_LIST(),
},
};
static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
{
return pxa2xx_timer_has_tm4(opaque);
}
static const VMStateDescription vmstate_pxa2xx_timer_regs = {
.name = "pxa2xx_timer",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT8(pressed, gamepad_button),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_stellaris_gamepad = {
.name = "stellaris_gamepad",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_INT32(extension, gamepad_state),
VMSTATE_STRUCT_VARRAY_INT32(buttons, gamepad_state, num_buttons, 0,
vmstate_stellaris_button, gamepad_button),
VMSTATE_END_OF_LIST()
}
};
/* Returns an array 5 ouput slots. */
void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode)
{
gamepad_state *s;
int i;
s = (gamepad_state *)g_malloc0(sizeof (gamepad_state));
s->buttons = (gamepad_button *)g_malloc0(n * sizeof (gamepad_button));
for (i = 0; i < n; i++) {
}
}
#endif
return 0;
}
static const VMStateDescription vmstate_rtc = {
.name = "mc146818rtc",
.version_id = 2,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.post_load = rtc_post_load,
.fields = (VMStateField []) {
VMSTATE_BUFFER(cmos_data, RTCState),
VMSTATE_UINT8(cmos_index, RTCState),
VMSTATE_INT32(current_tm.tm_sec, RTCState),
VMSTATE_INT32(current_tm.tm_min, RTCState),
VMSTATE_INT32(current_tm.tm_hour, RTCState),
VMSTATE_INT32(current_tm.tm_wday, RTCState),
VMSTATE_INT32(current_tm.tm_mday, RTCState),
VMSTATE_INT32(current_tm.tm_mon, RTCState),
VMSTATE_INT32(current_tm.tm_year, RTCState),
VMSTATE_TIMER(periodic_timer, RTCState),
VMSTATE_INT64(next_periodic_time, RTCState),
VMSTATE_INT64(next_second_time, RTCState),
VMSTATE_TIMER(second_timer, RTCState),
VMSTATE_TIMER(second_timer2, RTCState),
VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
VMSTATE_UINT32_V(period, RTCState, 2),
VMSTATE_END_OF_LIST()
}
}
return olen;
}
static const TypeInfo adb_bus_type_info = {
.name = TYPE_ADB_BUS,
.parent = TYPE_BUS,
.instance_size = sizeof(ADBBusState),
};
static const VMStateDescription vmstate_adb_device = {
.name = "adb_device",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_INT32(devaddr, ADBDevice),
VMSTATE_INT32(handler, ADBDevice),
VMSTATE_END_OF_LIST()
}
};
static void adb_device_realizefn(DeviceState *dev, Error **errp)
{
ADBDevice *d = ADB_DEVICE(dev);
ADBBusState *bus = ADB_BUS(qdev_get_parent_bus(dev));
if (bus->nb_devices >= MAX_ADB_DEVICES) {
return;
}
bus->devices[bus->nb_devices++] = d;
olen = 2;
break;
}
break;
}
return olen;
}
static const VMStateDescription vmstate_adb_kbd = {
.name = "adb_kbd",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_BUFFER(data, KBDState),
VMSTATE_INT32(rptr, KBDState),
VMSTATE_INT32(wptr, KBDState),
VMSTATE_INT32(count, KBDState),
VMSTATE_END_OF_LIST()
}
};
static int adb_kbd_reset(ADBDevice *d)
{
KBDState *s = d->opaque;
d->handler = 1;
d->devaddr = ADB_KEYBOARD;
memset(s, 0, sizeof(KBDState));
return 0;
.read = parallel_ioport_read_sw,
.write = parallel_ioport_write_sw },
PORTIO_END_OF_LIST(),
};
static const VMStateDescription vmstate_parallel_isa = {
.name = "parallel_isa",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(state.dataw, ISAParallelState),
VMSTATE_UINT8(state.datar, ISAParallelState),
VMSTATE_UINT8(state.status, ISAParallelState),
VMSTATE_UINT8(state.control, ISAParallelState),
VMSTATE_INT32(state.irq_pending, ISAParallelState),
VMSTATE_INT32(state.epp_timeout, ISAParallelState),
VMSTATE_END_OF_LIST()
}
};
static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
{
static int index;
ISADevice *isadev = ISA_DEVICE(dev);
ISAParallelState *isa = ISA_PARALLEL(dev);
ParallelState *s = &isa->state;
int base;
uint8_t dummy;
static void arm_timer_tick(void *opaque)
{
arm_timer_state *s = (arm_timer_state *)opaque;
s->int_level = 1;
arm_timer_update(s);
}
static const VMStateDescription vmstate_arm_timer = {
.name = "arm_timer",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(control, arm_timer_state),
VMSTATE_UINT32(limit, arm_timer_state),
VMSTATE_INT32(int_level, arm_timer_state),
VMSTATE_PTIMER(timer, arm_timer_state),
VMSTATE_END_OF_LIST()
}
};
static arm_timer_state *arm_timer_init(uint32_t freq)
{
arm_timer_state *s;
QEMUBH *bh;
s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
s->freq = freq;
s->control = TIMER_CTRL_IE;
bh = qemu_bh_new(arm_timer_tick, s);
}
static const VMStateDescription vmstate_pl022 = {
.name = "pl022_ssp",
.version_id = 1,
.minimum_version_id = 1,
.post_load = pl022_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cr0, PL022State),
VMSTATE_UINT32(cr1, PL022State),
VMSTATE_UINT32(bitmask, PL022State),
VMSTATE_UINT32(sr, PL022State),
VMSTATE_UINT32(cpsr, PL022State),
VMSTATE_UINT32(is, PL022State),
VMSTATE_UINT32(im, PL022State),
VMSTATE_INT32(tx_fifo_head, PL022State),
VMSTATE_INT32(rx_fifo_head, PL022State),
VMSTATE_INT32(tx_fifo_len, PL022State),
VMSTATE_INT32(rx_fifo_len, PL022State),
VMSTATE_UINT16(tx_fifo[0], PL022State),
VMSTATE_UINT16(rx_fifo[0], PL022State),
VMSTATE_UINT16(tx_fifo[1], PL022State),
VMSTATE_UINT16(rx_fifo[1], PL022State),
VMSTATE_UINT16(tx_fifo[2], PL022State),
VMSTATE_UINT16(rx_fifo[2], PL022State),
VMSTATE_UINT16(tx_fifo[3], PL022State),
VMSTATE_UINT16(rx_fifo[3], PL022State),
VMSTATE_UINT16(tx_fifo[4], PL022State),
VMSTATE_UINT16(rx_fifo[4], PL022State),
VMSTATE_UINT16(tx_fifo[5], PL022State),
VMSTATE_UINT16(rx_fifo[5], PL022State),
static bool esp_mem_accepts(void *opaque, target_phys_addr_t addr,
unsigned size, bool is_write)
{
return (size == 1) || (is_write && size == 4);
}
const VMStateDescription vmstate_esp = {
.name ="esp",
.version_id = 3,
.minimum_version_id = 3,
.minimum_version_id_old = 3,
.fields = (VMStateField []) {
VMSTATE_BUFFER(rregs, ESPState),
VMSTATE_BUFFER(wregs, ESPState),
VMSTATE_INT32(ti_size, ESPState),
VMSTATE_UINT32(ti_rptr, ESPState),
VMSTATE_UINT32(ti_wptr, ESPState),
VMSTATE_BUFFER(ti_buf, ESPState),
VMSTATE_UINT32(status, ESPState),
VMSTATE_UINT32(dma, ESPState),
VMSTATE_BUFFER(cmdbuf, ESPState),
VMSTATE_UINT32(cmdlen, ESPState),
VMSTATE_UINT32(do_cmd, ESPState),
VMSTATE_UINT32(dma_left, ESPState),
VMSTATE_END_OF_LIST()
}
};
typedef struct {
SysBusDevice busdev;
.name = "cpu/inactive_fpu",
.version_id = 1,
.minimum_version_id = 1,
.fields = vmstate_fpu_fields
};
/* TC state */
static VMStateField vmstate_tc_fields[] = {
VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
VMSTATE_UINTTL(PC, TCState),
VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
VMSTATE_UINTTL(DSPControl, TCState),
VMSTATE_INT32(CP0_TCStatus, TCState),
VMSTATE_INT32(CP0_TCBind, TCState),
VMSTATE_UINTTL(CP0_TCHalt, TCState),
VMSTATE_UINTTL(CP0_TCContext, TCState),
VMSTATE_UINTTL(CP0_TCSchedule, TCState),
VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
VMSTATE_UINTTL(CP0_UserLocal, TCState),
VMSTATE_INT32(msacsr, TCState),
VMSTATE_END_OF_LIST()
};
const VMStateDescription vmstate_tc = {
.name = "cpu/tc",
.version_id = 1,
.minimum_version_id = 1,
int32_t offset;
int32_t pad;
int32_t fifo_used;
int32_t len;
uint8_t data[2048];
} LAN9118Packet;
static const VMStateDescription vmstate_lan9118_packet = {
.name = "lan9118_packet",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(state, LAN9118Packet),
VMSTATE_UINT32(cmd_a, LAN9118Packet),
VMSTATE_UINT32(cmd_b, LAN9118Packet),
VMSTATE_INT32(buffer_size, LAN9118Packet),
VMSTATE_INT32(offset, LAN9118Packet),
VMSTATE_INT32(pad, LAN9118Packet),
VMSTATE_INT32(fifo_used, LAN9118Packet),
VMSTATE_INT32(len, LAN9118Packet),
VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048),
VMSTATE_END_OF_LIST()
}
};
typedef struct {
SysBusDevice busdev;
NICState *nic;
NICConf conf;
qemu_irq irq;
MemoryRegion mmio;
static const VMStateDescription vmstate_nand = {
.name = "nand",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.pre_save = nand_pre_save,
.post_load = nand_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT8(cle, NANDFlashState),
VMSTATE_UINT8(ale, NANDFlashState),
VMSTATE_UINT8(ce, NANDFlashState),
VMSTATE_UINT8(wp, NANDFlashState),
VMSTATE_UINT8(gnd, NANDFlashState),
VMSTATE_BUFFER(io, NANDFlashState),
VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
VMSTATE_INT32(iolen, NANDFlashState),
VMSTATE_UINT32(cmd, NANDFlashState),
VMSTATE_UINT64(addr, NANDFlashState),
VMSTATE_INT32(addrlen, NANDFlashState),
VMSTATE_INT32(status, NANDFlashState),
VMSTATE_INT32(offset, NANDFlashState),
/* XXX: do we want to save s->storage too? */
VMSTATE_END_OF_LIST()
}
};
static int nand_device_init(SysBusDevice *dev)
{
int pagesize;
NANDFlashState *s = FROM_SYSBUS(NANDFlashState, dev);
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
return arm_feature(env, ARM_FEATURE_M);
}
static const VMStateDescription vmstate_m = {
.name = "cpu/m",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.v7m.other_sp, ARMCPU),
VMSTATE_UINT32(env.v7m.vecbase, ARMCPU),
VMSTATE_UINT32(env.v7m.basepri, ARMCPU),
VMSTATE_UINT32(env.v7m.control, ARMCPU),
VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
VMSTATE_INT32(env.v7m.exception, ARMCPU),
VMSTATE_END_OF_LIST()
}
};
static bool thumb2ee_needed(void *opaque)
{
ARMCPU *cpu = opaque;
CPUARMState *env = &cpu->env;
return arm_feature(env, ARM_FEATURE_THUMB2EE);
}
static const VMStateDescription vmstate_thumb2ee = {
.name = "cpu/thumb2ee",
&& s->resp_len <= ARRAY_SIZE(s->resp_fifo);
}
static const VMStateDescription vmstate_pxa2xx_mmci = {
.name = "pxa2xx-mmci",
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(status, PXA2xxMMCIState),
VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
VMSTATE_UINT32(spi, PXA2xxMMCIState),
VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
VMSTATE_INT32(blklen, PXA2xxMMCIState),
VMSTATE_INT32(numblk, PXA2xxMMCIState),
VMSTATE_UINT32(intmask, PXA2xxMMCIState),
VMSTATE_UINT32(intreq, PXA2xxMMCIState),
VMSTATE_INT32(cmd, PXA2xxMMCIState),
VMSTATE_UINT32(arg, PXA2xxMMCIState),
VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
VMSTATE_INT32(active, PXA2xxMMCIState),
VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
sc->recv = smbus_i2c_recv;
sc->send = smbus_i2c_send;
}
bool smbus_vmstate_needed(SMBusDevice *dev)
{
return dev->mode != SMBUS_IDLE;
}
const VMStateDescription vmstate_smbus_device = {
.name = TYPE_SMBUS_DEVICE,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_I2C_SLAVE(i2c, SMBusDevice),
VMSTATE_INT32(mode, SMBusDevice),
VMSTATE_INT32(data_len, SMBusDevice),
VMSTATE_UINT8_ARRAY(data_buf, SMBusDevice, SMBUS_DATA_MAX_LEN),
VMSTATE_END_OF_LIST()
}
};
static const TypeInfo smbus_device_type_info = {
.name = TYPE_SMBUS_DEVICE,
.parent = TYPE_I2C_SLAVE,
.instance_size = sizeof(SMBusDevice),
.abstract = true,
.class_size = sizeof(SMBusDeviceClass),
.class_init = smbus_device_class_init,
};
s->mouse_wrap = 0;
s->mouse_type = 0;
s->mouse_detect_state = 0;
s->mouse_dx = 0;
s->mouse_dy = 0;
s->mouse_dz = 0;
s->mouse_buttons = 0;
}
static const VMStateDescription vmstate_ps2_common = {
.name = "PS2 Common State",
.version_id = 3,
.minimum_version_id = 2,
.minimum_version_id_old = 2,
.fields = (VMStateField []) {
VMSTATE_INT32(write_cmd, PS2State),
VMSTATE_INT32(queue.rptr, PS2State),
VMSTATE_INT32(queue.wptr, PS2State),
VMSTATE_INT32(queue.count, PS2State),
VMSTATE_BUFFER(queue.data, PS2State),
VMSTATE_END_OF_LIST()
}
};
static bool ps2_keyboard_ledstate_needed(void *opaque)
{
PS2KbdState *s = opaque;
return s->ledstate != 0; /* 0 is default state */
}
