.minimum_version_id = OLD_EEPROM_VERSION,
.fields = (VMStateField[]) {
VMSTATE_UINT8(tick, eeprom_t),
VMSTATE_UINT8(address, eeprom_t),
VMSTATE_UINT8(command, eeprom_t),
VMSTATE_UINT8(writable, eeprom_t),
VMSTATE_UINT8(eecs, eeprom_t),
VMSTATE_UINT8(eesk, eeprom_t),
VMSTATE_UINT8(eedo, eeprom_t),
VMSTATE_UINT8(addrbits, eeprom_t),
VMSTATE_UINT16_HACK_TEST(size, eeprom_t, is_old_eeprom_version),
VMSTATE_UNUSED_TEST(is_old_eeprom_version, 1),
VMSTATE_UINT16_EQUAL_V(size, eeprom_t, EEPROM_VERSION),
VMSTATE_UINT16(data, eeprom_t),
VMSTATE_VARRAY_UINT16_UNSAFE(contents, eeprom_t, size, 0,
vmstate_info_uint16, uint16_t),
VMSTATE_END_OF_LIST()
}
};
void eeprom93xx_write(eeprom_t *eeprom, int eecs, int eesk, int eedi)
{
uint8_t tick = eeprom->tick;
uint8_t eedo = eeprom->eedo;
uint16_t address = eeprom->address;
uint8_t command = eeprom->command;
logout("CS=%u SK=%u DI=%u DO=%u, tick = %u\n",
eecs, eesk, eedi, eedo, tick);
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cr0, pl022_state),
VMSTATE_UINT32(cr1, pl022_state),
VMSTATE_UINT32(bitmask, pl022_state),
VMSTATE_UINT32(sr, pl022_state),
VMSTATE_UINT32(cpsr, pl022_state),
VMSTATE_UINT32(is, pl022_state),
VMSTATE_UINT32(im, pl022_state),
VMSTATE_INT32(tx_fifo_head, pl022_state),
VMSTATE_INT32(rx_fifo_head, pl022_state),
VMSTATE_INT32(tx_fifo_len, pl022_state),
VMSTATE_INT32(rx_fifo_len, pl022_state),
VMSTATE_UINT16(tx_fifo[0], pl022_state),
VMSTATE_UINT16(rx_fifo[0], pl022_state),
VMSTATE_UINT16(tx_fifo[1], pl022_state),
VMSTATE_UINT16(rx_fifo[1], pl022_state),
VMSTATE_UINT16(tx_fifo[2], pl022_state),
VMSTATE_UINT16(rx_fifo[2], pl022_state),
VMSTATE_UINT16(tx_fifo[3], pl022_state),
VMSTATE_UINT16(rx_fifo[3], pl022_state),
VMSTATE_UINT16(tx_fifo[4], pl022_state),
VMSTATE_UINT16(rx_fifo[4], pl022_state),
VMSTATE_UINT16(tx_fifo[5], pl022_state),
VMSTATE_UINT16(rx_fifo[5], pl022_state),
VMSTATE_UINT16(tx_fifo[6], pl022_state),
VMSTATE_UINT16(rx_fifo[6], pl022_state),
VMSTATE_UINT16(tx_fifo[7], pl022_state),
VMSTATE_UINT16(rx_fifo[7], pl022_state),
static int vmstate_cg3_post_load(void *opaque, int version_id)
{
CG3State *s = opaque;
cg3_invalidate_display(s);
return 0;
}
static const VMStateDescription vmstate_cg3 = {
.name = "cg3",
.version_id = 1,
.minimum_version_id = 1,
.post_load = vmstate_cg3_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT16(height, CG3State),
VMSTATE_UINT16(width, CG3State),
VMSTATE_UINT16(depth, CG3State),
VMSTATE_BUFFER(r, CG3State),
VMSTATE_BUFFER(g, CG3State),
VMSTATE_BUFFER(b, CG3State),
VMSTATE_UINT8(dac_index, CG3State),
VMSTATE_UINT8(dac_state, CG3State),
VMSTATE_END_OF_LIST()
}
};
static void cg3_reset(DeviceState *d)
{
CG3State *s = CG3(d);
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, ICH9LPCPMRegs),
VMSTATE_END_OF_LIST()
}
};
const VMStateDescription vmstate_ich9_pm = {
.name = "ich9_pm",
.version_id = 1,
.minimum_version_id = 1,
.post_load = ich9_pm_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9LPCPMRegs),
VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9LPCPMRegs),
VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs),
VMSTATE_TIMER_PTR(acpi_regs.tmr.timer, ICH9LPCPMRegs),
VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9LPCPMRegs),
VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9LPCPMRegs),
VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9LPCPMRegs),
VMSTATE_UINT32(smi_en, ICH9LPCPMRegs),
VMSTATE_UINT32(smi_sts, ICH9LPCPMRegs),
VMSTATE_END_OF_LIST()
},
.subsections = (VMStateSubsection[]) {
{
.vmsd = &vmstate_memhp_state,
.needed = vmstate_test_use_memhp,
},
tcx24_set_dirty(s);
} else {
tcx_set_dirty(s);
}
return 0;
}
static const VMStateDescription vmstate_tcx = {
.name ="tcx",
.version_id = 4,
.minimum_version_id = 4,
.minimum_version_id_old = 4,
.post_load = vmstate_tcx_post_load,
.fields = (VMStateField []) {
VMSTATE_UINT16(height, TCXState),
VMSTATE_UINT16(width, TCXState),
VMSTATE_UINT16(depth, TCXState),
VMSTATE_BUFFER(r, TCXState),
VMSTATE_BUFFER(g, TCXState),
VMSTATE_BUFFER(b, TCXState),
VMSTATE_UINT8(dac_index, TCXState),
VMSTATE_UINT8(dac_state, TCXState),
VMSTATE_END_OF_LIST()
}
};
static void tcx_reset(DeviceState *d)
{
TCXState *s = container_of(d, TCXState, busdev.qdev);
uint32_t sys_clcd;
uint32_t mb_clock[6];
uint32_t *db_clock;
uint32_t db_num_vsensors;
uint32_t *db_voltage;
uint32_t db_num_clocks;
uint32_t *db_clock_reset;
} arm_sysctl_state;
static const VMStateDescription vmstate_arm_sysctl = {
.name = "realview_sysctl",
.version_id = 4,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(leds, arm_sysctl_state),
VMSTATE_UINT16(lockval, arm_sysctl_state),
VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
VMSTATE_UINT32(flags, arm_sysctl_state),
VMSTATE_UINT32(nvflags, arm_sysctl_state),
VMSTATE_UINT32(resetlevel, arm_sysctl_state),
VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
VMSTATE_UINT32_ARRAY_V(mb_clock, arm_sysctl_state, 6, 4),
VMSTATE_VARRAY_UINT32(db_clock, arm_sysctl_state, db_num_clocks,
4, vmstate_info_uint32, uint32_t),
VMSTATE_END_OF_LIST()
}
.version_id = 0,
.minimum_version_id = 0,
.needed = iplb_extended_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(reserved_ext, IplParameterBlock, 4096 - 200),
VMSTATE_END_OF_LIST()
}
};
static const VMStateDescription vmstate_iplb = {
.name = "ipl/iplb",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT8_ARRAY(reserved1, IplParameterBlock, 110),
VMSTATE_UINT16(devno, IplParameterBlock),
VMSTATE_UINT8_ARRAY(reserved2, IplParameterBlock, 88),
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription*[]) {
&vmstate_iplb_extended,
NULL
}
};
static const VMStateDescription vmstate_ipl = {
.name = "ipl",
.version_id = 0,
.minimum_version_id = 0,
.fields = (VMStateField[]) {
VMSTATE_UINT64(compat_start_addr, S390IPLState),
.version_id = 1,
.minimum_version_id = 1,
.post_load = pl022_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cr0, PL022State),
VMSTATE_UINT32(cr1, PL022State),
VMSTATE_UINT32(bitmask, PL022State),
VMSTATE_UINT32(sr, PL022State),
VMSTATE_UINT32(cpsr, PL022State),
VMSTATE_UINT32(is, PL022State),
VMSTATE_UINT32(im, PL022State),
VMSTATE_INT32(tx_fifo_head, PL022State),
VMSTATE_INT32(rx_fifo_head, PL022State),
VMSTATE_INT32(tx_fifo_len, PL022State),
VMSTATE_INT32(rx_fifo_len, PL022State),
VMSTATE_UINT16(tx_fifo[0], PL022State),
VMSTATE_UINT16(rx_fifo[0], PL022State),
VMSTATE_UINT16(tx_fifo[1], PL022State),
VMSTATE_UINT16(rx_fifo[1], PL022State),
VMSTATE_UINT16(tx_fifo[2], PL022State),
VMSTATE_UINT16(rx_fifo[2], PL022State),
VMSTATE_UINT16(tx_fifo[3], PL022State),
VMSTATE_UINT16(rx_fifo[3], PL022State),
VMSTATE_UINT16(tx_fifo[4], PL022State),
VMSTATE_UINT16(rx_fifo[4], PL022State),
VMSTATE_UINT16(tx_fifo[5], PL022State),
VMSTATE_UINT16(rx_fifo[5], PL022State),
VMSTATE_UINT16(tx_fifo[6], PL022State),
VMSTATE_UINT16(rx_fifo[6], PL022State),
VMSTATE_UINT16(tx_fifo[7], PL022State),
VMSTATE_UINT16(rx_fifo[7], PL022State),
#define VMSTATE_UINT16_HACK(_f, _s, _t) \
VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
static bool is_version_1(void *opaque, int version_id)
{
return version_id == 1;
}
static const VMStateDescription vmstate_fw_cfg = {
.name = "fw_cfg",
.version_id = 2,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT16(cur_entry, FWCfgState),
VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
VMSTATE_END_OF_LIST()
}
};
static void fw_cfg_add_bytes_read_callback(FWCfgState *s, uint16_t key,
FWCfgReadCallback callback,
void *callback_opaque,
void *data, size_t len)
{
int arch = !!(key & FW_CFG_ARCH_LOCAL);
key &= FW_CFG_ENTRY_MASK;
int rx_fifo[NUM_PACKETS];
int tx_fifo_done_len;
int tx_fifo_done[NUM_PACKETS];
/* Packet buffer memory. */
uint8_t data[NUM_PACKETS][2048];
uint8_t int_level;
uint8_t int_mask;
MemoryRegion mmio;
} smc91c111_state;
static const VMStateDescription vmstate_smc91c111 = {
.name = "smc91c111",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField []) {
VMSTATE_UINT16(tcr, smc91c111_state),
VMSTATE_UINT16(rcr, smc91c111_state),
VMSTATE_UINT16(cr, smc91c111_state),
VMSTATE_UINT16(ctr, smc91c111_state),
VMSTATE_UINT16(gpr, smc91c111_state),
VMSTATE_UINT16(ptr, smc91c111_state),
VMSTATE_UINT16(ercv, smc91c111_state),
VMSTATE_INT32(bank, smc91c111_state),
VMSTATE_INT32(packet_num, smc91c111_state),
VMSTATE_INT32(tx_alloc, smc91c111_state),
VMSTATE_INT32(allocated, smc91c111_state),
VMSTATE_INT32(tx_fifo_len, smc91c111_state),
VMSTATE_INT32_ARRAY(tx_fifo, smc91c111_state, NUM_PACKETS),
VMSTATE_INT32(rx_fifo_len, smc91c111_state),
VMSTATE_INT32_ARRAY(rx_fifo, smc91c111_state, NUM_PACKETS),
VMSTATE_INT32(tx_fifo_done_len, smc91c111_state),
vmmouse_remove_handler(s);
vmmouse_update_handler(s, s->absolute);
return 0;
}
static const VMStateDescription vmstate_vmmouse = {
.name = "vmmouse",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.post_load = vmmouse_post_load,
.fields = (VMStateField []) {
VMSTATE_INT32_EQUAL(queue_size, VMMouseState),
VMSTATE_UINT32_ARRAY(queue, VMMouseState, VMMOUSE_QUEUE_SIZE),
VMSTATE_UINT16(nb_queue, VMMouseState),
VMSTATE_UINT16(status, VMMouseState),
VMSTATE_UINT8(absolute, VMMouseState),
VMSTATE_END_OF_LIST()
}
};
static void vmmouse_reset(void *opaque)
{
VMMouseState *s = opaque;
s->status = 0xffff;
s->queue_size = VMMOUSE_QUEUE_SIZE;
vmmouse_disable(s);
}
}
static const MemoryRegionOps imx_i2c_ops = {
.read = imx_i2c_read,
.write = imx_i2c_write,
.valid.min_access_size = 1,
.valid.max_access_size = 2,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static const VMStateDescription imx_i2c_vmstate = {
.name = TYPE_IMX_I2C,
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT16(address, IMXI2CState),
VMSTATE_UINT16(iadr, IMXI2CState),
VMSTATE_UINT16(ifdr, IMXI2CState),
VMSTATE_UINT16(i2cr, IMXI2CState),
VMSTATE_UINT16(i2sr, IMXI2CState),
VMSTATE_UINT16(i2dr_read, IMXI2CState),
VMSTATE_UINT16(i2dr_write, IMXI2CState),
VMSTATE_END_OF_LIST()
}
};
static void imx_i2c_realize(DeviceState *dev, Error **errp)
{
IMXI2CState *s = IMX_I2C(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &imx_i2c_ops, s, TYPE_IMX_I2C,
ZYNQ_XADC_MMIO_SIZE);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->qemu_irq);
}
static const VMStateDescription vmstate_zynq_xadc = {
.name = "zynq-xadc",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, ZynqXADCState, ZYNQ_XADC_NUM_IO_REGS),
VMSTATE_UINT16_ARRAY(xadc_regs, ZynqXADCState,
ZYNQ_XADC_NUM_ADC_REGS),
VMSTATE_UINT16_ARRAY(xadc_dfifo, ZynqXADCState,
ZYNQ_XADC_FIFO_DEPTH),
VMSTATE_UINT16(xadc_read_reg_previous, ZynqXADCState),
VMSTATE_UINT16(xadc_dfifo_entries, ZynqXADCState),
VMSTATE_END_OF_LIST()
}
};
static void zynq_xadc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->vmsd = &vmstate_zynq_xadc;
dc->reset = zynq_xadc_reset;
}
static const TypeInfo zynq_xadc_info = {
.class_init = zynq_xadc_class_init,
s->lp[0] ^= ~s->count;
s->lp[1] ^= s->count;
}
s->count ++;
return sample;
}
/* Reinitialise the counters. */
void ecc_reset(ECCState *s)
{
s->lp[0] = 0x0000;
s->lp[1] = 0x0000;
s->cp = 0x00;
s->count = 0;
}
/* Save/restore */
VMStateDescription vmstate_ecc_state = {
.name = "ecc-state",
.version_id = 0,
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField []) {
VMSTATE_UINT8(cp, ECCState),
VMSTATE_UINT16_ARRAY(lp, ECCState, 2),
VMSTATE_UINT16(count, ECCState),
VMSTATE_END_OF_LIST(),
},
};