return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion; } static const VMStateDescription vmstate_pmsav7 = { .name = "cpu/pmsav7", .version_id = 1, .minimum_version_id = 1, .needed = pmsav7_needed, .fields = (VMStateField[]) { VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, vmstate_info_uint32, uint32_t), VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), VMSTATE_END_OF_LIST() } }; static int get_cpsr(QEMUFile *f, void *opaque, size_t size) { ARMCPU *cpu = opaque; CPUARMState *env = &cpu->env; uint32_t val = qemu_get_be32(f); env->aarch64 = ((val & PSTATE_nRW) == 0); if (is_a64(env)) { pstate_write(env, val); return 0;
VMSTATE_UINT32(read_tout, PXA2xxMMCIState), VMSTATE_INT32(blklen, PXA2xxMMCIState), VMSTATE_INT32(numblk, PXA2xxMMCIState), VMSTATE_UINT32(intmask, PXA2xxMMCIState), VMSTATE_UINT32(intreq, PXA2xxMMCIState), VMSTATE_INT32(cmd, PXA2xxMMCIState), VMSTATE_UINT32(arg, PXA2xxMMCIState), VMSTATE_INT32(cmdreq, PXA2xxMMCIState), VMSTATE_INT32(active, PXA2xxMMCIState), VMSTATE_INT32(bytesleft, PXA2xxMMCIState), VMSTATE_UINT32(tx_start, PXA2xxMMCIState), VMSTATE_UINT32(tx_len, PXA2xxMMCIState), VMSTATE_UINT32(rx_start, PXA2xxMMCIState), VMSTATE_UINT32(rx_len, PXA2xxMMCIState), VMSTATE_UINT32(resp_len, PXA2xxMMCIState), VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate), VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64), VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32), VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9), VMSTATE_END_OF_LIST() } }; #define MMC_STRPCL 0x00 /* MMC Clock Start/Stop register */ #define MMC_STAT 0x04 /* MMC Status register */ #define MMC_CLKRT 0x08 /* MMC Clock Rate register */ #define MMC_SPI 0x0c /* MMC SPI Mode register */ #define MMC_CMDAT 0x10 /* MMC Command/Data register */ #define MMC_RESTO 0x14 /* MMC Response Time-Out register */ #define MMC_RDTO 0x18 /* MMC Read Time-Out register */ #define MMC_BLKLEN 0x1c /* MMC Block Length register */