static void cvtMMms16K(const ACMDRVSTREAMINSTANCE *adsi,
const unsigned char* src, LPDWORD nsrc,
unsigned char* dst, LPDWORD ndst)
{
int idelta;
int sample1, sample2;
ADPCMCOEFSET coeff;
int nsamp;
int nsamp_blk = ((ADPCMWAVEFORMAT*)adsi->pwfxSrc)->wSamplesPerBlock;
DWORD nblock = min(*nsrc / adsi->pwfxSrc->nBlockAlign,
*ndst / (nsamp_blk * 2));
*nsrc = nblock * adsi->pwfxSrc->nBlockAlign;
*ndst = nblock * nsamp_blk * 2;
nsamp_blk -= 2; /* see below for samples from block head */
for (; nblock > 0; nblock--)
{
const unsigned char* in_src = src;
assert(*src <= 6);
coeff = MSADPCM_CoeffSet[*src++];
idelta = R16(src); src += 2;
sample1 = R16(src); src += 2;
sample2 = R16(src); src += 2;
/* store samples from block head */
W16(dst, sample2); dst += 2;
W16(dst, sample1); dst += 2;
for (nsamp = nsamp_blk; nsamp > 0; nsamp -= 2)
{
process_nibble(*src >> 4, &idelta, &sample1, &sample2, &coeff);
W16(dst, sample1); dst += 2;
process_nibble(*src++ & 0x0F, &idelta, &sample1, &sample2, &coeff);
W16(dst, sample1); dst += 2;
}
src = in_src + adsi->pwfxSrc->nBlockAlign;
}
}
static void cvtSM816K(const unsigned char* src, int ns, unsigned char* dst)
{
short v;
TRACE("(%p, %d, %p)\n", src, ns, dst);
while (ns--) {
v = M16(C816(src[0]), C816(src[1]));
src += 2;
W16(dst, v);
dst += 2;
}
}
static void cvtMS1616C(DWORD srcRate, const unsigned char* src, LPDWORD nsrc,
DWORD dstRate, unsigned char* dst, LPDWORD ndst)
{
DWORD error = dstRate / 2;
TRACE("(%d, %p, %p, %d, %p, %p)\n", srcRate, src, nsrc, dstRate, dst, ndst);
while((*ndst)--) {
W16(dst, R16(src));
dst += 2;
W16(dst, R16(src));
dst += 2;
error = error + srcRate;
while (error > dstRate) {
src += 2;
(*nsrc)--;
if (*nsrc == 0)
return;
error = error - dstRate;
}
}
}
void TRIReset()
{
//Reset GCAM status
GCAMInit();
//F-Zero AX uses Clean CARD after 150 uses
if(TRIGame == TRI_AX && TRI_BackupAvailable == 1)
{
//if we dont set it to 150 it'll beep a lot
sync_before_read(OUR_SETTINGS_LOC, 0x20);
W16((u32)OUR_SETTINGS_LOC+0x16,150);
sync_after_write(OUR_SETTINGS_LOC, 0x20);
}
}
static void stop(struct net_device *dev)
{
struct fs_enet_private *fep = netdev_priv(dev);
scc_t __iomem *sccp = fep->scc.sccp;
int i;
for (i = 0; (R16(sccp, scc_sccm) == 0) && i < SCC_RESET_DELAY; i++)
udelay(1);
if (i == SCC_RESET_DELAY)
printk(KERN_WARNING DRV_MODULE_NAME
": %s SCC timeout on graceful transmit stop\n",
dev->name);
W16(sccp, scc_sccm, 0);
C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
fs_cleanup_bds(dev);
}
void Io::Reset ()
{
std::memset(m_iomem, 0, IO_SIZE);
// TODO use clears intead
// TODO DISPCNT should be 0x80 by default
// TODO do it also for clears
// TODO lcd should draw white lines when hblank forced
// TODO when passing disabling hblank forced, lcd should start drawing from
// first line
W16(SOUNDBIAS, 0x0200); // default value
W16(KEYINPUT, 0x03FF); // all keys released
W8(HALTCNT, 0xFF); // normal mode (internal)
W16(DISPSTAT, 0x0004); // vcount match (since default vcount is 0)
W16(BG2PA, 0x0100);
W16(BG2PD, 0x0100);
W16(BG3PA, 0x0100);
W16(BG3PD, 0x0100);
W16(RCNT, 0x8000); // we start in general purpose mode
}
void Io::ClearOthers ()
{
// FIXME !! shouldn't we call Write*() ?
// lcd
for (uint8_t i = 0x0; i < 0x56; i += 2)
Write16(i, 0x0000);
// dma
for (uint8_t i = 0xB0; i < 0xE0; i += 4)
Write32(i, 0x0000);
// FIXME : should timers be set to 0 too ? (vba does not)
W8(HALTCNT, 0xFF); // normal mode (internal)
W16(IE, 0x0000);
W16(IF, 0x0000);
W16(IME, 0x0000);
Write16(WAITCNT, 0x0000);
W16(BG2PA, 0x0100);
W16(BG2PD, 0x0100);
W16(BG3PA, 0x0100);
W16(BG3PD, 0x0100);
}
static void restart(struct net_device *dev)
{
struct fs_enet_private *fep = netdev_priv(dev);
const struct fs_platform_info *fpi = fep->fpi;
fcc_t __iomem *fccp = fep->fcc.fccp;
fcc_c_t __iomem *fcccp = fep->fcc.fcccp;
fcc_enet_t __iomem *ep = fep->fcc.ep;
dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
u16 paddrh, paddrm, paddrl;
const unsigned char *mac;
int i;
C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
/* clear everything (slow & steady does it) */
for (i = 0; i < sizeof(*ep); i++)
out_8((u8 __iomem *)ep + i, 0);
/* get physical address */
rx_bd_base_phys = fep->ring_mem_addr;
tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
/* point to bds */
W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
/* Set maximum bytes per receive buffer.
* It must be a multiple of 32.
*/
W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
/* Allocate space in the reserved FCC area of DPRAM for the
* internal buffers. No one uses this space (yet), so we
* can do this. Later, we will add resource management for
* this area.
*/
W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset);
W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32);
W16(ep, fen_padptr, fpi->dpram_offset + 64);
/* fill with special symbol... */
memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
W32(ep, fen_genfcc.fcc_rbptr, 0);
W32(ep, fen_genfcc.fcc_tbptr, 0);
W32(ep, fen_genfcc.fcc_rcrc, 0);
W32(ep, fen_genfcc.fcc_tcrc, 0);
W16(ep, fen_genfcc.fcc_res1, 0);
W32(ep, fen_genfcc.fcc_res2, 0);
/* no CAM */
W32(ep, fen_camptr, 0);
/* Set CRC preset and mask */
W32(ep, fen_cmask, 0xdebb20e3);
W32(ep, fen_cpres, 0xffffffff);
W32(ep, fen_crcec, 0); /* CRC Error counter */
W32(ep, fen_alec, 0); /* alignment error counter */
W32(ep, fen_disfc, 0); /* discard frame counter */
W16(ep, fen_retlim, 15); /* Retry limit threshold */
W16(ep, fen_pper, 0); /* Normal persistence */
/* set group address */
W32(ep, fen_gaddrh, fep->fcc.gaddrh);
W32(ep, fen_gaddrl, fep->fcc.gaddrh);
/* Clear hash filter tables */
W32(ep, fen_iaddrh, 0);
W32(ep, fen_iaddrl, 0);
/* Clear the Out-of-sequence TxBD */
W16(ep, fen_tfcstat, 0);
W16(ep, fen_tfclen, 0);
W32(ep, fen_tfcptr, 0);
W16(ep, fen_mflr, PKT_MAXBUF_SIZE); /* maximum frame length register */
W16(ep, fen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
/* set address */
mac = dev->dev_addr;
paddrh = ((u16)mac[5] << 8) | mac[4];
paddrm = ((u16)mac[3] << 8) | mac[2];
paddrl = ((u16)mac[1] << 8) | mac[0];
W16(ep, fen_paddrh, paddrh);
W16(ep, fen_paddrm, paddrm);
W16(ep, fen_paddrl, paddrl);
W16(ep, fen_taddrh, 0);
W16(ep, fen_taddrm, 0);
W16(ep, fen_taddrl, 0);
W16(ep, fen_maxd1, 1520); /* maximum DMA1 length */
W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */
/* Clear stat counters, in case we ever enable RMON */
W32(ep, fen_octc, 0);
W32(ep, fen_colc, 0);
W32(ep, fen_broc, 0);
W32(ep, fen_mulc, 0);
W32(ep, fen_uspc, 0);
W32(ep, fen_frgc, 0);
W32(ep, fen_ospc, 0);
W32(ep, fen_jbrc, 0);
W32(ep, fen_p64c, 0);
W32(ep, fen_p65c, 0);
W32(ep, fen_p128c, 0);
W32(ep, fen_p256c, 0);
W32(ep, fen_p512c, 0);
W32(ep, fen_p1024c, 0);
W16(ep, fen_rfthr, 0); /* Suggested by manual */
W16(ep, fen_rfcnt, 0);
W16(ep, fen_cftype, 0);
fs_init_bds(dev);
/* adjust to speed (for RMII mode) */
if (fpi->use_rmii) {
if (fep->phydev->speed == 100)
C8(fcccp, fcc_gfemr, 0x20);
else
S8(fcccp, fcc_gfemr, 0x20);
}
fcc_cr_cmd(fep, CPM_CR_INIT_TRX);
/* clear events */
W16(fccp, fcc_fcce, 0xffff);
/* Enable interrupts we wish to service */
W16(fccp, fcc_fccm, FCC_ENET_TXE | FCC_ENET_RXF | FCC_ENET_TXB);
/* Set GFMR to enable Ethernet operating mode */
W32(fccp, fcc_gfmr, FCC_GFMR_TCI | FCC_GFMR_MODE_ENET);
/* set sync/delimiters */
W16(fccp, fcc_fdsr, 0xd555);
W32(fccp, fcc_fpsmr, FCC_PSMR_ENCRC);
if (fpi->use_rmii)
S32(fccp, fcc_fpsmr, FCC_PSMR_RMII);
/* adjust to duplex mode */
if (fep->phydev->duplex)
S32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
else
C32(fccp, fcc_fpsmr, FCC_PSMR_FDE | FCC_PSMR_LPB);
/* Restore multicast and promiscuous settings */
set_multicast_list(dev);
S32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
}
ASSERT_EQ(pads, 8);
/* Check default value is -1 */
foreach(i, size) {
W16 val = tags[i];
ASSERT_EQ(val, (W16(-1)));
ASSERT_FALSE(tags.isvalid(i));
}
/* Test insert */
foreach(i, 8) {
tags.insert(i);
}
foreach(i, 8) {
W16 val = tags[i];
ASSERT_EQ(val, (W16(i)));
}
/* now we remove 3rd entry */
tags.collapse(2);
for(int i=2; i < 7; i++) {
W16 val = tags[i];
ASSERT_EQ((W16(i+1)), val) << "Tags: " << tags;
}
}
/* Test simulation freq related functions */
TEST(Sim, SimFreq)
{
#define TEST_NS_TO_CYCLE(freq, ns, expected) \
config.core_freq_hz = freq; \
bool PatchTimers(u32 FirstVal, u32 Buffer)
{
/* The floats in the data sections */
if( FirstVal == FLT_TIMER_CLOCK_BUS_GC )
{
write32(Buffer, FLT_TIMER_CLOCK_BUS_WII);
dbgprintf("PatchTimers:[Timer Clock float Bus] applied (0x%08X)\r\n", Buffer );
return true;
}
if( FirstVal == FLT_TIMER_CLOCK_CPU_GC )
{
write32(Buffer, FLT_TIMER_CLOCK_CPU_WII);
dbgprintf("PatchTimers:[Timer Clock float CPU] applied (0x%08X)\r\n", Buffer );
return true;
}
if( FirstVal == FLT_TIMER_CLOCK_SECS_GC )
{
write32(Buffer, FLT_TIMER_CLOCK_SECS_WII);
dbgprintf("PatchTimers:[Timer Clock float s] applied (0x%08X)\r\n", Buffer );
return true;
}
if( FirstVal == FLT_TIMER_CLOCK_MSECS_GC )
{
write32(Buffer, FLT_TIMER_CLOCK_MSECS_WII);
dbgprintf("PatchTimers:[Timer Clock float ms] applied (0x%08X)\r\n", Buffer );
return true;
}
if( FirstVal == FLT_ONE_DIV_CLOCK_SECS_GC )
{
write32(Buffer, FLT_ONE_DIV_CLOCK_SECS_WII);
dbgprintf("PatchTimers:[Timer Clock float 1/s] applied (0x%08X)\r\n", Buffer );
return true;
}
if( FirstVal == FLT_ONE_DIV_CLOCK_MSECS_GC )
{
write32(Buffer, FLT_ONE_DIV_CLOCK_MSECS_WII);
dbgprintf("PatchTimers:[Timer Clock float 1/ms] applied (0x%08X)\r\n", Buffer );
return true;
}
if( FirstVal == FLT_ONE_DIV_CLOCK_1200_GC )
{
write32(Buffer, FLT_ONE_DIV_CLOCK_1200_WII);
dbgprintf("PatchTimers:[Timer Clock float 1/1200] applied (0x%08X)\r\n", Buffer );
return true;
}
/* For Nintendo Puzzle Collection */
if( FirstVal == 0x38C00BB8 && (u32)Buffer == 0x770528 )
{ //it IS a smooth 1.5 BUT the game is actually not properly timed, good job devs
write32(Buffer, 0x38C01194);
dbgprintf("PatchTimers:[Timer Clock Panel de Pon] applied (0x%08X)\r\n", Buffer );
return true;
}
/* Coded in values */
FirstVal &= 0xFC00FFFF;
if( FirstVal == 0x3C0009A7 )
{
u32 NextP = CheckFor(Buffer, 0x6000EC80);
if(NextP > 0)
{
W16(Buffer + 2, U32_TIMER_CLOCK_BUS_WII >> 16);
W16(NextP + 2, U32_TIMER_CLOCK_BUS_WII & 0xFFFF);
dbgprintf("PatchTimers:[Timer Clock ori Bus] applied (0x%08X)\r\n", Buffer );
return true;
}
#define PIPE_6_SZ_IN 0
#define PIPE_6_SZ_OUT 0
#define PIPE_7_SZ_IN 0
#define PIPE_7_SZ_OUT 0
#define PIPE_8_SZ_IN 0
#define PIPE_8_SZ_OUT 0
static const __code uint8_t deviceDescriptor[] =
{
sizeof(deviceDescriptor), // bLength
DEVICE_DESCRIPTOR, // bDescriptorType
W16(0x110), // bcdUSB
0x02, // bDeviceClass
0x00, // bDeviceSubClass
0x00, // bDeviceProtocl
PIPE_0_SZ_OUT, // bMaxPacketSize
W16(0x0482), // idVendor
W16(0x0203), // idProduct
W16(0x0100), // bcdDevice
0x01, // iManufacturer
0x02, // iProduct
0x03, // iSerialNumber
0x01 // bNumConfigurations
};
CTASSERT(sizeof deviceDescriptor == 0x12);
/*
* This function is called to start or restart the FEC during a link
* change. This only happens when switching between half and full
* duplex.
*/
static void restart(struct net_device *dev)
{
struct fs_enet_private *fep = netdev_priv(dev);
scc_t __iomem *sccp = fep->scc.sccp;
scc_enet_t __iomem *ep = fep->scc.ep;
const struct fs_platform_info *fpi = fep->fpi;
u16 paddrh, paddrm, paddrl;
const unsigned char *mac;
int i;
C32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
/* clear everything (slow & steady does it) */
for (i = 0; i < sizeof(*ep); i++)
__fs_out8((u8 __iomem *)ep + i, 0);
/* point to bds */
W16(ep, sen_genscc.scc_rbase, fep->ring_mem_addr);
W16(ep, sen_genscc.scc_tbase,
fep->ring_mem_addr + sizeof(cbd_t) * fpi->rx_ring);
/* Initialize function code registers for big-endian.
*/
#ifndef CONFIG_NOT_COHERENT_CACHE
W8(ep, sen_genscc.scc_rfcr, SCC_EB | SCC_GBL);
W8(ep, sen_genscc.scc_tfcr, SCC_EB | SCC_GBL);
#else
W8(ep, sen_genscc.scc_rfcr, SCC_EB);
W8(ep, sen_genscc.scc_tfcr, SCC_EB);
#endif
/* Set maximum bytes per receive buffer.
* This appears to be an Ethernet frame size, not the buffer
* fragment size. It must be a multiple of four.
*/
W16(ep, sen_genscc.scc_mrblr, 0x5f0);
/* Set CRC preset and mask.
*/
W32(ep, sen_cpres, 0xffffffff);
W32(ep, sen_cmask, 0xdebb20e3);
W32(ep, sen_crcec, 0); /* CRC Error counter */
W32(ep, sen_alec, 0); /* alignment error counter */
W32(ep, sen_disfc, 0); /* discard frame counter */
W16(ep, sen_pads, 0x8888); /* Tx short frame pad character */
W16(ep, sen_retlim, 15); /* Retry limit threshold */
W16(ep, sen_maxflr, 0x5ee); /* maximum frame length register */
W16(ep, sen_minflr, PKT_MINBUF_SIZE); /* minimum frame length register */
W16(ep, sen_maxd1, 0x000005f0); /* maximum DMA1 length */
W16(ep, sen_maxd2, 0x000005f0); /* maximum DMA2 length */
/* Clear hash tables.
*/
W16(ep, sen_gaddr1, 0);
W16(ep, sen_gaddr2, 0);
W16(ep, sen_gaddr3, 0);
W16(ep, sen_gaddr4, 0);
W16(ep, sen_iaddr1, 0);
W16(ep, sen_iaddr2, 0);
W16(ep, sen_iaddr3, 0);
W16(ep, sen_iaddr4, 0);
/* set address
*/
mac = dev->dev_addr;
paddrh = ((u16) mac[5] << 8) | mac[4];
paddrm = ((u16) mac[3] << 8) | mac[2];
paddrl = ((u16) mac[1] << 8) | mac[0];
W16(ep, sen_paddrh, paddrh);
W16(ep, sen_paddrm, paddrm);
W16(ep, sen_paddrl, paddrl);
W16(ep, sen_pper, 0);
W16(ep, sen_taddrl, 0);
W16(ep, sen_taddrm, 0);
W16(ep, sen_taddrh, 0);
fs_init_bds(dev);
scc_cr_cmd(fep, CPM_CR_INIT_TRX);
W16(sccp, scc_scce, 0xffff);
/* Enable interrupts we wish to service.
*/
W16(sccp, scc_sccm, SCCE_ENET_TXE | SCCE_ENET_RXF | SCCE_ENET_TXB);
/* Set GSMR_H to enable all normal operating modes.
* Set GSMR_L to enable Ethernet to MC68160.
*/
W32(sccp, scc_gsmrh, 0);
W32(sccp, scc_gsmrl,
SCC_GSMRL_TCI | SCC_GSMRL_TPL_48 | SCC_GSMRL_TPP_10 |
SCC_GSMRL_MODE_ENET);
/* Set sync/delimiters.
*/
W16(sccp, scc_dsr, 0xd555);
/* Set processing mode. Use Ethernet CRC, catch broadcast, and
* start frame search 22 bit times after RENA.
*/
W16(sccp, scc_psmr, SCC_PSMR_ENCRC | SCC_PSMR_NIB22);
/* Set full duplex mode if needed */
if (fep->phydev->duplex)
S16(sccp, scc_psmr, SCC_PSMR_LPB | SCC_PSMR_FDE);
S32(sccp, scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT);
}
void Io::ClearSio ()
{
// TODO
W16(RCNT, 0x8000);
}
void Io::Write16 (uint32_t add, uint16_t val)
{
//debug ("IO Write16 at " << IOS_ADD << add << " of " << IOS_ADD << val);
//*(uint16_t*)(m_iomem + (add & 0xFFF)) = val;
switch (add & 0xFFF)
{
case KEYINPUT:
case VCOUNT:
break;
case DMA0CNT_L:
case DMA1CNT_L:
case DMA2CNT_L:
case DMA3CNT_L:
//W16(add, val);
DMA.SetReload(((add & 0xFFF) - DMA0CNT_L) / DMA_CHANSIZE, val);
break;
case KEYCNT:
W16(add, val & 0xC3FF);
break;
case IME:
W16(add, val & 0x0001);
CPU.CheckInterrupt();
break;
case IE:
W16(add, val & 0x3FFF);
CPU.CheckInterrupt();
break;
case IF:
*((uint16_t*)(m_iomem+IF)) ^= (val & (*((uint16_t*)(m_iomem+IF))));
CPU.CheckInterrupt();
break;
case BG0CNT:
W16(add, val & 0xFFCF);
LCD.UpdateBg0Cnt(val & 0xFFCF);
break;
case BG1CNT:
W16(add, val & 0xFFCF);
LCD.UpdateBg1Cnt(val & 0xFFCF);
break;
case BG2CNT:
W16(add, val & 0xFFCF);
LCD.UpdateBg2Cnt(val & 0xFFCF);
break;
case BG3CNT:
W16(add, val & 0xFFCF);
LCD.UpdateBg3Cnt(val & 0xFFCF);
break;
case DISPSTAT:
// the first 3 bits are read only and they are used by the lcd
// NOTE : we are in LITTLE ENDIAN
// FIXME : if vcount setting has changed to current vcount, we should
// update the vcounter flag and eventually trigger an interrupt
W16(add, (val & 0xFFF8) | (m_iomem[add & 0xFFF] & 0x07));
break;
// The BG*OFS are write-only, we don't need to W16()
// You do if you're ever going to load them from a savestate...
case BG0HOFS:
W16(add, val & 0x1FF);
LCD.UpdateBg0XOff(val & 0x1FF);
break;
case BG0VOFS:
W16(add, val & 0x1FF);
LCD.UpdateBg0YOff(val & 0x1FF);
break;
case BG1HOFS:
W16(add, val & 0x1FF);
LCD.UpdateBg1XOff(val & 0x1FF);
break;
case BG1VOFS:
W16(add, val & 0x1FF);
LCD.UpdateBg1YOff(val & 0x1FF);
break;
case BG2HOFS:
W16(add, val & 0x1FF);
LCD.UpdateBg2XOff(val & 0x1FF);
break;
case BG2VOFS:
W16(add, val & 0x1FF);
LCD.UpdateBg2YOff(val & 0x1FF);
break;
case BG3HOFS:
W16(add, val & 0x1FF);
LCD.UpdateBg3XOff(val & 0x1FF);
break;
case BG3VOFS:
W16(add, val & 0x1FF);
LCD.UpdateBg3YOff(val & 0x1FF);
break;
case BG2X_H:
val &= 0x0FFF;
case BG2X_L:
W16(add, val);
LCD.UpdateBg2RefX(IO.DRead32(Io::BG2X_L));
break;
case BG2Y_H:
val &= 0x0FFF;
case BG2Y_L:
W16(add, val);
LCD.UpdateBg2RefY(IO.DRead32(Io::BG2Y_L));
break;
case BG3X_H:
val &= 0x0FFF;
case BG3X_L:
W16(add, val);
LCD.UpdateBg3RefX(IO.DRead32(Io::BG3X_L));
break;
case BG3Y_H:
val &= 0x0FFF;
case BG3Y_L:
W16(add, val);
LCD.UpdateBg3RefY(IO.DRead32(Io::BG3Y_L));
break;
case WIN0H:
case WIN1H:
case WIN0V:
case WIN1V:
case WININ:
case WINOUT:
W16(add, val);
break;
case BLDCNT:
W16(add, val);
break;
case MOSAIC:
W16(add, val);
break;
case DISPCNT:
W16(add, val);
LCD.UpdateDispCnt(val);
break;
case DMA0CNT_H:
case DMA1CNT_H:
case DMA2CNT_H:
case DMA3CNT_H:
W16(add, val & 0xFFE0);
DMA.UpdateCnt(((add & 0xFFF) - DMA0CNT_H) / DMA_CHANSIZE);
break;
case WAITCNT:
W16(add, val & 0xDFFF);
MEM.UpdateWaitStates (val & 0xDFFF);
break;
case SOUND1CNT_L:
case SOUND1CNT_H:
case SOUND1CNT_X:
case SOUND2CNT_L:
case SOUND2CNT_H:
case SOUND4CNT_L:
case SOUND4CNT_H:
case SOUNDCNT_L:
case SOUNDCNT_H:
case SOUNDCNT_X:
case POSTFLG:
Write8(add, val & 0xFF);
Write8(add + 1, val >> 8);
break;
case TM0CNT_L:
TIMER0.SetReload(val);
break;
case TM1CNT_L:
TIMER1.SetReload(val);
break;
case TM2CNT_L:
TIMER2.SetReload(val);
break;
case TM3CNT_L:
TIMER3.SetReload(val);
break;
case TM0CNT_H:
W16(add, val & 0x00C7);
TIMER0.Reload();
break;
case TM1CNT_H:
W16(add, val & 0x00C7);
TIMER1.Reload();
break;
case TM2CNT_H:
W16(add, val & 0x00C7);
TIMER2.Reload();
break;
case TM3CNT_H:
W16(add, val & 0x00C7);
TIMER3.Reload();
break;
default:
//met_abort("Unknown IO at " << IOS_ADD << add);
W16(add, val);
break;
}
}
static void restart(struct net_device *dev)
{
struct fs_enet_private *fep = netdev_priv(dev);
const struct fs_platform_info *fpi = fep->fpi;
fcc_t __iomem *fccp = fep->fcc.fccp;
fcc_c_t __iomem *fcccp = fep->fcc.fcccp;
fcc_enet_t __iomem *ep = fep->fcc.ep;
dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
u16 paddrh, paddrm, paddrl;
const unsigned char *mac;
int i;
C32(fccp, fcc_gfmr, FCC_GFMR_ENR | FCC_GFMR_ENT);
/* clear everything (slow & steady does it) */
for (i = 0; i < sizeof(*ep); i++)
out_8((u8 __iomem *)ep + i, 0);
/* get physical address */
rx_bd_base_phys = fep->ring_mem_addr;
tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
/* point to bds */
W32(ep, fen_genfcc.fcc_rbase, rx_bd_base_phys);
W32(ep, fen_genfcc.fcc_tbase, tx_bd_base_phys);
/* Set maximum bytes per receive buffer.
* It must be a multiple of 32.
*/
W16(ep, fen_genfcc.fcc_mrblr, PKT_MAXBLR_SIZE);
W32(ep, fen_genfcc.fcc_rstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
W32(ep, fen_genfcc.fcc_tstate, (CPMFCR_GBL | CPMFCR_EB) << 24);
/* Allocate space in the reserved FCC area of DPRAM for the
* internal buffers. No one uses this space (yet), so we
* can do this. Later, we will add resource management for
* this area.
*/
W16(ep, fen_genfcc.fcc_riptr, fpi->dpram_offset);
W16(ep, fen_genfcc.fcc_tiptr, fpi->dpram_offset + 32);
W16(ep, fen_padptr, fpi->dpram_offset + 64);
/* fill with special symbol... */
memset_io(fep->fcc.mem + fpi->dpram_offset + 64, 0x88, 32);
W32(ep, fen_genfcc.fcc_rbptr, 0);
W32(ep, fen_genfcc.fcc_tbptr, 0);
W32(ep, fen_genfcc.fcc_rcrc, 0);
W32(ep, fen_genfcc.fcc_tcrc, 0);
W16(ep, fen_genfcc.fcc_res1, 0);
W32(ep, fen_genfcc.fcc_res2, 0);
/* no CAM */
W32(ep, fen_camptr, 0);
/* Set CRC preset and mask */
W32(ep, fen_cmask, 0xdebb20e3);
W32(ep, fen_cpres, 0xffffffff);
W32(ep, fen_crcec, 0); /* CRC Error counter */
W32(ep, fen_alec, 0); /* alignment error counte
