PHY_SPACE (0, 0, D0F0xE4_PHY_6880_ADDRESS),
D0F0xE4_PHY_6880_RxInCalForce_MASK,
0x1 << D0F0xE4_PHY_6880_RxInCalForce_OFFSET
},
{
PHY_SPACE (0, 0, D0F0xE4_PHY_6900_ADDRESS),
D0F0xE4_PHY_6900_RxInCalForce_MASK,
0x1 << D0F0xE4_PHY_6900_RxInCalForce_OFFSET
},
{
PHY_SPACE (0, 0, D0F0xE4_PHY_6A00_ADDRESS),
D0F0xE4_PHY_6A00_RxInCalForce_MASK,
0x1 << D0F0xE4_PHY_6A00_RxInCalForce_OFFSET
},
{
WRAP_SPACE (0, D0F0xE4_WRAP_8016_ADDRESS),
D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
0
},
{
PHY_SPACE (0, 0, D0F0xE4_PHY_4004_ADDRESS),
D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_MASK | D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_MASK,
(0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_OFFSET) | (0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_OFFSET)
},
{
D0F0xE4_x0108_8071_ADDRESS,
D0F0xE4_x0108_8071_RxAdjust_MASK,
0x3 << D0F0xE4_x0108_8071_RxAdjust_OFFSET
},
{
D0F0xE4_x0108_8072_ADDRESS,
VOID
PcieTopologySelectMasterPllML (
IN PCIe_WRAPPER_CONFIG *Wrapper,
OUT BOOLEAN *ConfigChanged,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT16 MasterLane;
UINT16 MasterHotplugLane;
UINT16 EngineMasterLane;
D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013;
D0F0xE4_WRAP_8013_STRUCT D0F0xE4_WRAP_8013_BASE;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPllML Enter\n");
MasterLane = 0xFFFF;
MasterHotplugLane = 0xFFFF;
EngineList = PcieConfigGetChildEngine (Wrapper);
while (EngineList != NULL) {
if (PcieConfigIsEngineAllocated (EngineList) && EngineList->Type.Port.PortData.PortPresent != PortDisabled && PcieConfigIsPcieEngine (EngineList)) {
EngineMasterLane = PcieConfigGetPcieEngineMasterLane (EngineList);
if (EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
MasterHotplugLane = (EngineMasterLane < MasterHotplugLane) ? EngineMasterLane : MasterHotplugLane;
} else {
MasterLane = (EngineMasterLane < MasterLane) ? EngineMasterLane : MasterLane;
if (PcieConfigIsSbPcieEngine (EngineList)) {
break;
}
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
if (MasterLane == 0xffff) {
if (MasterHotplugLane != 0xffff) {
MasterLane = MasterHotplugLane;
} else {
MasterLane = 0x0;
}
}
D0F0xE4_WRAP_8013.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8013_BASE.Value = D0F0xE4_WRAP_8013.Value;
if (MasterLane <= 3 ) {
Wrapper->MasterPll = GNB_PCIE_MASTERPLL_A;
} else {
Wrapper->MasterPll = GNB_PCIE_MASTERPLL_B;
}
IDS_OPTION_HOOK (IDS_GNB_PCIE_MASTERPLL_SELECTION, &(Wrapper->MasterPll), GnbLibGetHeader (Pcie));
if (Wrapper->MasterPll == GNB_PCIE_MASTERPLL_A) {
D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x1;
D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x0;
} else {
D0F0xE4_WRAP_8013.Field.MasterPciePllA = 0x0;
D0F0xE4_WRAP_8013.Field.MasterPciePllB = 0x1;
}
if (ConfigChanged != NULL) {
*ConfigChanged = (D0F0xE4_WRAP_8013.Value == D0F0xE4_WRAP_8013_BASE.Value) ? FALSE : TRUE;
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
D0F0xE4_WRAP_8013.Value,
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologySelectMasterPllML Exit\n");
}
VOID
PciePwrClockGating (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
ex501_STRUCT ex501 ;
D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012;
D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014;
D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015;
ex688_STRUCT ex688 ;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n");
D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
Pcie
);
ex501.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, 0x8011 ),
Pcie
);
if (Wrapper->Features.ClkGating == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1;
ex501.Field.TxclkDynGateEnable = 0x1;
ex501.Field.TxclkRegsGateEnable = 0x1;
ex501.Field.TxclkLcntGateEnable = 0x1;
ex501.Field.RcvrDetClkEnable = 0x1;
ex501.Field.TxclkPermGateEven = 0x1;
ex501.Field.TxclkDynGateLatency = 0x3f;
ex501.Field.TxclkRegsGateLatency = 0x3f;
ex501.Field.TxclkPermGateLatency = 0x3f;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f;
D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1;
}
if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
D0F0xE4_WRAP_8014.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
D0F0xE4_WRAP_8015.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
D0F0xE4_WRAP_8012.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, 0x8011 ),
ex501.Value,
TRUE,
Pcie
);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, 0x11 ),
0 ,
4 ,
0xf,
TRUE,
Pcie
);
}
if (Wrapper->Features.LclkGating == 0x1) {
ex688.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, 0x8016 ),
Pcie
);
ex688.Field.LclkDynGateEnable = 0x1;
ex688.Field.LclkGateFree = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, 0x8016 ),
ex688.Value,
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
}
/**
* Set current link speed
*
*
* @param[in] LinkSpeedCapability Link Speed Capability
* @param[in] Engine Pointer to engine configuration descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
PcieSetLinkSpeedCapV4 (
IN PCIE_LINK_SPEED_CAP LinkSpeedCapability,
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxF0xE4_xA4_STRUCT DxF0xE4_xA4;
DxF0xE4_xC0_STRUCT DxF0xE4_xC0;
DxF0x88_STRUCT DxF0x88;
GnbLibPciRead (
Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
AccessWidth32,
&DxF0x88.Value,
GnbLibGetHeader (Pcie)
);
DxF0xE4_xA4.Value = PciePortRegisterRead (
Engine,
DxF0xE4_xA4_ADDRESS,
Pcie
);
DxF0xE4_xC0.Value = PciePortRegisterRead (
Engine,
DxF0xE4_xC0_ADDRESS,
Pcie
);
switch (LinkSpeedCapability) {
case PcieGen3:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
DxF0xE4_xA4.Field.LcGen3EnStrap = 0x1;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
DxF0x88.Field.TargetLinkSpeed = 0x3;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
break;
case PcieGen2:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x1;
DxF0xE4_xA4.Field.LcGen3EnStrap = 0x0;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x1;
DxF0x88.Field.TargetLinkSpeed = 0x2;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x0;
break;
case PcieGen1:
DxF0xE4_xA4.Field.LcGen2EnStrap = 0x0;
DxF0xE4_xA4.Field.LcGen3EnStrap = 0x0;
DxF0xE4_xA4.Field.LcMultUpstreamAutoSpdChngEn = 0x0;
DxF0x88.Field.TargetLinkSpeed = 0x1;
DxF0x88.Field.HwAutonomousSpeedDisable = 0x1;
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_0803_ADDRESS + 0x100 * Engine->Type.Port.PortId),
D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_OFFSET,
D0F0xE4_WRAP_0803_StrapBifDeemphasisSel_WIDTH,
0,
FALSE,
Pcie
);
break;
default:
ASSERT (FALSE);
break;
}
if ((Pcie->PsppPolicy == PsppDisabled) || (PcieConfigIsSbPcieEngine (Engine))) {
DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x0;
} else {
DxF0xE4_xC0.Field.StrapAutoRcSpeedNegotiationDis = 0x1;
}
PciePortRegisterWrite (
Engine,
DxF0xE4_xA4_ADDRESS,
DxF0xE4_xA4.Value,
FALSE,
Pcie
);
PciePortRegisterWrite (
Engine,
DxF0xE4_xC0_ADDRESS,
DxF0xE4_xC0.Value,
FALSE,
Pcie
);
GnbLibPciWrite (
Engine->Type.Port.Address.AddressValue | DxF0x88_ADDRESS,
AccessWidth32,
&DxF0x88.Value,
GnbLibGetHeader (Pcie)
);
}
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T A B L E S
*----------------------------------------------------------------------------------------
*/
STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
{
WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS),
D0F0xE4_WRAP_8016_CalibAckLatency_MASK,
0
},
{
PHY_SPACE (GPP_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
D0F0xE4_PHY_2008_VdDetectEn_MASK,
0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
},
{
PHY_SPACE (GFX_WRAP_ID, 0, D0F0xE4_PHY_2008_ADDRESS),
D0F0xE4_PHY_2008_VdDetectEn_MASK,
0x1 << D0F0xE4_PHY_2008_VdDetectEn_OFFSET
},
{
PHY_SPACE (GFX_WRAP_ID, 1, D0F0xE4_PHY_2008_ADDRESS),
VOID
PciePwrClockGating (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011;
D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012;
D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014;
D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Enter\n");
D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8011.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
Pcie
);
if (Wrapper->Features.ClkGating == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.RcvrDetClkEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f;
D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
}
if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
D0F0xE4_WRAP_8014.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
D0F0xE4_WRAP_8012.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011.Value,
TRUE,
Pcie
);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
0xf,
TRUE,
Pcie
);
}
if (Wrapper->Features.LclkGating == 0x1) {
D0F0xE4_WRAP_8016.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
D0F0xE4_WRAP_8016.Value,
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGating Exit\n");
}
/**
* Execute/clean up reconfiguration
*
*
* @param[in] Wrapper Pointer to wrapper config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieTopologyExecuteReconfig (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8062_STRUCT D0F0xE4_WRAP_8062;
D0F0xE4_WRAP_8060_STRUCT D0F0xE4_WRAP_8060;
if (PcieLibIsPcieWrapper (Wrapper)) {
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Enter\n");
PcieTopologyInitSrbmReset (FALSE, Wrapper, Pcie);
D0F0xE4_WRAP_8062.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
D0F0xE4_WRAP_8060.Field.Reconfigure = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
D0F0xE4_WRAP_8060.Value,
FALSE,
Pcie
);
do {
D0F0xE4_WRAP_8060.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8060_ADDRESS),
Pcie
);
} while (D0F0xE4_WRAP_8060.Field.Reconfigure == 1);
D0F0xE4_WRAP_8062.Field.ConfigXferMode = 0x1;
D0F0xE4_WRAP_8062.Field.ReconfigureEn = 0x0;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8062_ADDRESS),
D0F0xE4_WRAP_8062.Value,
FALSE,
Pcie
);
PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyExecuteReconfig Exit\n");
}
}
VOID
PcieTopologyApplyLaneMux (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
UINT8 CurrentPhyLane;
UINT8 CurrentCoreLane;
UINT8 CoreLaneIndex;
UINT8 PhyLaneIndex;
UINT8 NumberOfPhyLane;
UINT8 TxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
UINT8 RxLaneMuxSelectorArray [sizeof (LaneMuxSelectorTable)];
UINT8 Index;
UINT32 TxMaxSelectorValue;
UINT32 RxMaxSelectorValue;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Enter\n");
if (PcieLibIsPcieWrapper (Wrapper)) {
EngineList = PcieConfigGetChildEngine (Wrapper);
LibAmdMemCopy (
&TxLaneMuxSelectorArray[0],
&LaneMuxSelectorTable[0],
sizeof (LaneMuxSelectorTable),
GnbLibGetHeader (Pcie)
);
LibAmdMemCopy (
&RxLaneMuxSelectorArray[0],
&LaneMuxSelectorTable[0],
sizeof (LaneMuxSelectorTable),
GnbLibGetHeader (Pcie)
);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
CurrentPhyLane = (UINT8) PcieLibGetLoPhyLane (EngineList) - Wrapper->StartPhyLane;
NumberOfPhyLane = (UINT8) PcieConfigGetNumberOfPhyLane (EngineList);
CurrentCoreLane = (UINT8) EngineList->Type.Port.StartCoreLane;
if (PcieUtilIsLinkReversed (FALSE, EngineList, Pcie)) {
CurrentCoreLane = CurrentCoreLane + PcieConfigGetNumberOfCoreLane (EngineList) - NumberOfPhyLane;
}
for (Index = 0; Index < NumberOfPhyLane; Index = Index + 2 ) {
CoreLaneIndex = (CurrentCoreLane + Index) / 2;
PhyLaneIndex = (CurrentPhyLane + Index) / 2;
if (RxLaneMuxSelectorArray [CoreLaneIndex] != PhyLaneIndex) {
RxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (RxLaneMuxSelectorArray, PhyLaneIndex)] = RxLaneMuxSelectorArray [CoreLaneIndex];
RxLaneMuxSelectorArray [CoreLaneIndex] = PhyLaneIndex;
}
if (TxLaneMuxSelectorArray [PhyLaneIndex] != CoreLaneIndex) {
TxLaneMuxSelectorArray [PcieTopologyLocateMuxIndex (TxLaneMuxSelectorArray, CoreLaneIndex)] = TxLaneMuxSelectorArray [PhyLaneIndex];
TxLaneMuxSelectorArray [PhyLaneIndex] = CoreLaneIndex;
}
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
RxMaxSelectorValue = 0;
TxMaxSelectorValue = 0;
for (Index = 0; Index < sizeof (LaneMuxSelectorTable); Index++) {
RxMaxSelectorValue |= (RxLaneMuxSelectorArray[Index] << (Index * 4));
TxMaxSelectorValue |= (TxLaneMuxSelectorArray[Index] << (Index * 4));
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8021_ADDRESS),
TxMaxSelectorValue,
FALSE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8022_ADDRESS),
RxMaxSelectorValue,
FALSE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTopologyApplyLaneMux Exit\n");
}
VOID
PciePwrClockGatingV5 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011;
D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012;
D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014;
D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015;
D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV5 Enter\n");
D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8011.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
Pcie
);
if (Wrapper->Features.ClkGating == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiDigaGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiDigbGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiDigcGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiDigdGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiPifa1xGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiPifb1xGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiPifc1xGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiPifd1xGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.EnableD0StateReport = 0x0;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x0;
D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x0;
D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x0;
D0F0xE4_WRAP_8011.Field.Bitfield_16_16 = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x0;
D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x0;
}
if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
D0F0xE4_WRAP_8014.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
D0F0xE4_WRAP_8015.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
D0F0xE4_WRAP_8012.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011.Value,
TRUE,
Pcie
);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
0xf,
TRUE,
Pcie
);
}
if (Wrapper->Features.LclkGating == 0x1) {
D0F0xE4_WRAP_8016.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
D0F0xE4_WRAP_8016.Value,
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV5 Exit\n");
}
VOID
PcieLinkInitHotplug (
IN PCIe_ENGINE_CONFIG *Engine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxF0xE4_xB5_STRUCT DxF0xE4_xB5;
if ((Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced) || (Engine->Type.Port.PortData.LinkHotplug == HotplugInboard)) {
DxF0xE4_xB5.Value = PciePortRegisterRead (Engine, DxF0xE4_xB5_ADDRESS, Pcie);
DxF0xE4_xB5.Field.LcEhpRxPhyCmd = 0x3;
DxF0xE4_xB5.Field.LcEhpTxPhyCmd = 0x3;
DxF0xE4_xB5.Field.LcEnhancedHotPlugEn = 0x1;
PciePortRegisterWrite (
Engine,
DxF0xE4_xB5_ADDRESS,
DxF0xE4_xB5.Value,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
CORE_SPACE (Engine->Type.Port.CoreId, D0F0xE4_CORE_0010_ADDRESS),
D0F0xE4_CORE_0010_LcHotPlugDelSel_OFFSET,
D0F0xE4_CORE_0010_LcHotPlugDelSel_WIDTH,
0x5,
TRUE,
Pcie
);
PcieRegisterWriteField (
PcieConfigGetParentWrapper (Engine),
WRAP_SPACE (PcieConfigGetParentWrapper (Engine)->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011_RcvrDetClkEnable_OFFSET,
D0F0xE4_WRAP_8011_RcvrDetClkEnable_WIDTH,
0x1,
TRUE,
Pcie
);
}
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
GnbLibPciRMW (
Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS,
AccessS3SaveWidth32,
0xffffffff,
1 << DxF0x6C_HotplugCapable_OFFSET,
GnbLibGetHeader (Pcie)
);
PciePortRegisterWriteField (
Engine,
DxF0xE4_x20_ADDRESS,
DxF0xE4_x20_TxFlushTlpDis_OFFSET,
DxF0xE4_x20_TxFlushTlpDis_WIDTH,
0x0,
TRUE,
Pcie
);
PciePortRegisterWriteField (
Engine,
DxF0xE4_x70_ADDRESS,
DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET,
DxF0xE4_x70_RxRcbCplTimeoutMode_WIDTH,
0x1,
FALSE,
Pcie
);
}
}
VOID
PciePwrClockGatingV4 (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0xE4_WRAP_8011_STRUCT D0F0xE4_WRAP_8011;
D0F0xE4_WRAP_8012_STRUCT D0F0xE4_WRAP_8012;
D0F0xE4_WRAP_8014_STRUCT D0F0xE4_WRAP_8014;
D0F0xE4_WRAP_8015_STRUCT D0F0xE4_WRAP_8015;
D0F0xE4_WRAP_8016_STRUCT D0F0xE4_WRAP_8016;
UINT8 CoreId;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV4 Enter\n");
D0F0xE4_WRAP_8014.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8015.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8012.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8011.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
Pcie
);
if (Wrapper->Features.ClkGating == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.TxclkPrbsGateEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifB2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifC2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.PcieGatePifD2p5xEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkLcntGateEnable = 0x1;
D0F0xE4_WRAP_8011.Field.Bitfield_16_16 = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkPermGateEven = 0x1;
D0F0xE4_WRAP_8011.Field.TxclkDynGateLatency = 0x3f;
D0F0xE4_WRAP_8011.Field.TxclkRegsGateLatency = 0x3f;
D0F0xE4_WRAP_8011.Field.TxclkPermGateLatency = 0x3f;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif2p5xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleResumeLatency = 0x7;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateEnable = 0x1;
D0F0xE4_WRAP_8012.Field.Pif1xIdleGateLatency = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkBphyGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkBphyGateLatency = 0x0;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateEnable = 0x1;
D0F0xE4_WRAP_8015.Field.RefclkRegsGateLatency = 0x3f;
D0F0xE4_WRAP_8015.Field.Bitfield_2_2 = 0x0;
D0F0xE4_WRAP_8015.Field.Bitfield_3_3 = 0x0;
D0F0xE4_WRAP_8015.Field.Bitfield_5_4 = 0x3;
D0F0xE4_WRAP_8015.Field.Bitfield_7_6 = 0x1;
D0F0xE4_WRAP_8015.Field.Bitfield_9_9 = 0x0;
D0F0xE4_WRAP_8015.Field.Bitfield_10_10 = 0x0;
D0F0xE4_WRAP_8015.Field.Bitfield_11_11 = 0x0;
D0F0xE4_WRAP_8015.Field.Bitfield_13_12 = 0x1;
D0F0xE4_WRAP_8015.Field.Bitfield_15_14 = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGateDigAEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGateDigBEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGateDigCEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGateDigDEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifA1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifB1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifC1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifD1xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifA2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifB2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifC2p5xEnable = 0x1;
D0F0xE4_WRAP_8014.Field.DdiGatePifD2p5xEnable = 0x1;
}
if (Wrapper->Features.TxclkGatingPllPowerDown == 0x1) {
D0F0xE4_WRAP_8014.Field.TxclkPermGateOnlyWhenPllPwrDn = 0x1;
}
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8014_ADDRESS),
D0F0xE4_WRAP_8014.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8015_ADDRESS),
D0F0xE4_WRAP_8015.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8012_ADDRESS),
D0F0xE4_WRAP_8012.Value,
TRUE,
Pcie
);
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8011_ADDRESS),
D0F0xE4_WRAP_8011.Value,
TRUE,
Pcie
);
for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
PcieRegisterWriteField (
Wrapper,
CORE_SPACE (CoreId, D0F0xE4_CORE_0011_ADDRESS),
D0F0xE4_CORE_0011_DynClkLatency_OFFSET,
D0F0xE4_CORE_0011_DynClkLatency_WIDTH,
0xf,
TRUE,
Pcie
);
}
if (Wrapper->Features.LclkGating == 0x1) {
D0F0xE4_WRAP_8016.Value = PcieRegisterRead (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8016.Field.LclkDynGateEnable = 0x1;
D0F0xE4_WRAP_8016.Field.LclkGateFree = 0x1;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8016_ADDRESS),
D0F0xE4_WRAP_8016.Value,
TRUE,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrClockGatingV4 Exit\n");
}
